[clang] ce5fb1b - [CIR][NFC] Consolidate AArch64 tests (#180919)

[via cfe-commits]

Author: Andrzej Warzyński
Date: 2026-02-12T09:23:26Z
New Revision: ce5fb1b501f4713665561740b9df67293bf94767

URL: https://github.com/llvm/llvm-project/commit/ce5fb1b501f4713665561740b9df67293bf94767
DIFF: https://github.com/llvm/llvm-project/commit/ce5fb1b501f4713665561740b9df67293bf94767.diff

LOG: [CIR][NFC] Consolidate AArch64 tests (#180919)

As initiated in #180597 (*), ensure that CIR tests reuse the default
Clang lowering tests. To this end, consolidate the AArch64 tests for
unconstrained -fullfp16 builtins into:

  * clang/test/CodeGen/AArch64/neon/fullfp16.c

(*) See also https://github.com/llvm/llvm-project/issues/179952 for
more context.

Added: 
    

Modified: 
    clang/test/CodeGen/AArch64/neon/fullfp16.c
    clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c

Removed: 
    clang/test/CIR/CodeGenBuiltins/AArch64/neon/fullfp16.c


################################################################################
diff  --git a/clang/test/CIR/CodeGenBuiltins/AArch64/neon/fullfp16.c b/clang/test/CIR/CodeGenBuiltins/AArch64/neon/fullfp16.c
deleted file mode 100644
index 3943c4e57e1d1..0000000000000
--- a/clang/test/CIR/CodeGenBuiltins/AArch64/neon/fullfp16.c
+++ /dev/null
@@ -1,35 +0,0 @@
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64 -target-feature +fullfp16 -disable-O0-optnone -Werror -Wall -fclangir -emit-cir  -o - %s                                       | FileCheck %s --check-prefixes=ALL,CIR
-// RUN: %clang_cc1 -triple aarch64 -target-feature +fullfp16 -disable-O0-optnone -Werror -Wall -fclangir -emit-llvm -o - %s |  opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM
-// RUN: %clang_cc1 -triple aarch64 -target-feature +fullfp16 -disable-O0-optnone -Werror -Wall           -emit-llvm -o - %s |  opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM
-
-
-//=============================================================================
-// NOTES
-//
-// Tests for unconstrained intrinsics that require the fullfp16 extension.
-//
-// As these intrinsics expand to code with multiple compound and declaration
-// stmts, the LLVM output has been simplified with opt. `simplifycfg` was added
-// specifically for the CIR lowering path.
-//
-// Minor 
diff erences between RUNs (e.g. presence of `noundef` attached to
-// argumens, align` attribute attached to pointers), are matched using
-// catch-alls like {{.*}}.
-//
-// TODO: Merge this file with clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
-// (the source of these tests).
-//=============================================================================
-
-#include <arm_fp16.h>
-
-// ALL-LABEL: @test_vabsh_f16
-float16_t test_vabsh_f16(float16_t a) {
-// CIR: {{%.*}}  = cir.fabs {{%.*}} : !cir.f16
-
-// LLVM-SAME: (half{{.*}} [[A:%.*]])
-// LLVM:  [[ABS:%.*]] =  call half @llvm.fabs.f16(half [[A]])
-// LLVM:  ret half [[ABS]]
-  return vabsh_f16(a);
-}

diff  --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c
index b4aca52372bf7..f3268df2f4165 100644
--- a/clang/test/CodeGen/AArch64/neon/fullfp16.c
+++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c
@@ -31,6 +31,16 @@
 
 #include <arm_fp16.h>
 
+// ALL-LABEL: @test_vabsh_f16
+float16_t test_vabsh_f16(float16_t a) {
+// CIR: {{%.*}} = cir.fabs {{%.*}} : !cir.f16
+
+// LLVM-SAME: (half{{.*}} [[A:%.*]])
+// LLVM:  [[ABS:%.*]] = call half @llvm.fabs.f16(half [[A]])
+// LLVM:  ret half [[ABS]]
+  return vabsh_f16(a);
+}
+
 // ALL-LABEL: @test_vnegh_f16
 float16_t test_vnegh_f16(float16_t a) {
 // CIR: cir.unary(minus, {{.*}}) : !cir.f16

diff  --git a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
index a4d544d26ae27..353f02195721f 100644
--- a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
@@ -7,13 +7,6 @@
 
 #include <arm_fp16.h>
 
-// CHECK-LABEL: test_vabsh_f16
-// CHECK:  [[ABS:%.*]] =  call half @llvm.fabs.f16(half %a)
-// CHECK:  ret half [[ABS]]
-float16_t test_vabsh_f16(float16_t a) {
-  return vabsh_f16(a);
-}
-
 // CHECK-LABEL: test_vceqzh_f16
 // CHECK:  [[TMP1:%.*]] = fcmp oeq half %a, 0xH0000
 // CHECK:  [[TMP2:%.*]] = sext i1 [[TMP1]] to i16