[clang] [llvm] [AMDGPU] Add dot4 fp8/bf8 instructions for gfx1170 (PR #180516)
Mirko BrkuĊĦanin via cfe-commits
cfe-commits at lists.llvm.org
Mon Feb 9 04:59:17 PST 2026
https://github.com/mbrkusanin created https://github.com/llvm/llvm-project/pull/180516
None
>From 015c3b9ca9b76aadd8526ffc4be72edd620525b2 Mon Sep 17 00:00:00 2001
From: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Date: Fri, 6 Feb 2026 14:43:26 +0100
Subject: [PATCH] [AMDGPU] Add dot4 fp8/bf8 instructions for gfx1170
---
.../builtins-amdgcn-dl-insts-gfx12.cl | 1 +
llvm/lib/Target/AMDGPU/AMDGPU.td | 3 +-
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 10 +-
llvm/lib/TargetParser/TargetParser.cpp | 1 +
.../CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll | 128 +++++++++++++++-
llvm/test/MC/AMDGPU/gfx1170_asm_vop3p.s | 122 +++++++++++++++
llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16.s | 25 +++
.../MC/AMDGPU/gfx1170_asm_vop3p_dpp16_err.s | 24 +++
llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8.s | 25 +++
.../MC/AMDGPU/gfx1170_asm_vop3p_dpp8_err.s | 27 ++++
llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_err.s | 133 ++++++++++++++++
.../AMDGPU/gfx1170_dasm_vop3p.txt | 122 +++++++++++++++
.../AMDGPU/gfx1170_dasm_vop3p_dpp16.txt | 25 +++
.../AMDGPU/gfx1170_dasm_vop3p_dpp8.txt | 25 +++
.../AMDGPU/gfx1170_dasm_vop3p_err.txt | 144 ++++++++++++++++++
15 files changed, 807 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/gfx1170_asm_vop3p.s
create mode 100644 llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16.s
create mode 100644 llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16_err.s
create mode 100644 llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8.s
create mode 100644 llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8_err.s
create mode 100644 llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_err.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p.txt
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp16.txt
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp8.txt
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_err.txt
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx12.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx12.cl
index 2eb8b6d5f1069..576fb475f883d 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx12.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx12.cl
@@ -1,5 +1,6 @@
// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1170 -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -emit-llvm -o - %s | FileCheck %s
typedef unsigned int uint;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 9d723c86031f2..723b064afd64e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1885,7 +1885,8 @@ def FeatureISAVersion11_7_0 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features,
[FeatureSALUFloatInsts,
FeatureDPPSrc1SGPR,
- FeatureFP8ConversionInsts])>;
+ FeatureFP8ConversionInsts,
+ FeatureDot11Insts])>;
def FeatureISAVersion12 : FeatureSet<
[FeatureGFX12,
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 256dd0bb027ad..063546e1a5bc2 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -693,7 +693,6 @@ def VOP3P_DOTF8_Profile : VOP3P_Profile<VOPProfile <[f32, i32, i32, f32]>,
multiclass VOP3PDOTF8Inst <string OpName, SDPatternOperator intrinsic_node> {
defm NAME : VOP3PInst<OpName, VOP3P_DOTF8_Profile, null_frag, 1>;
- let SubtargetPredicate = isGFX12Plus in
def : GCNPat <(intrinsic_node i32:$src0, i32:$src1,
(VOP3Mods f32:$src2, i32:$src2_modifiers)),
(!cast<Instruction>(NAME) i32:$src0, i32:$src1,
@@ -2493,6 +2492,11 @@ multiclass VOP3P_Realtriple<GFXGen Gen, bits<8> op, string backing_ps_name = NAM
multiclass VOP3P_Realtriple_gfx11_gfx12<bits<8> op>
: VOP3P_Realtriple<GFX11Gen, op>, VOP3P_Realtriple<GFX12Gen, op>;
+defm V_DOT4_F32_FP8_BF8 : VOP3P_Realtriple_gfx11_gfx12<0x24>;
+defm V_DOT4_F32_BF8_FP8 : VOP3P_Realtriple_gfx11_gfx12<0x25>;
+defm V_DOT4_F32_FP8_FP8 : VOP3P_Realtriple_gfx11_gfx12<0x26>;
+defm V_DOT4_F32_BF8_BF8 : VOP3P_Realtriple_gfx11_gfx12<0x27>;
+
//===----------------------------------------------------------------------===//
// GFX12
//===----------------------------------------------------------------------===//
@@ -2546,10 +2550,6 @@ def : AMDGPUMnemonicAlias<"v_fma_mix_f32_f16", "v_fma_mix_f32">;
defm V_PK_MINIMUM_F16 : VOP3P_Real_gfx12<0x1d>;
defm V_PK_MAXIMUM_F16 : VOP3P_Real_gfx12<0x1e>;
-defm V_DOT4_F32_FP8_BF8 : VOP3P_Realtriple<GFX12Gen, 0x24>;
-defm V_DOT4_F32_BF8_FP8 : VOP3P_Realtriple<GFX12Gen, 0x25>;
-defm V_DOT4_F32_FP8_FP8 : VOP3P_Realtriple<GFX12Gen, 0x26>;
-defm V_DOT4_F32_BF8_BF8 : VOP3P_Realtriple<GFX12Gen, 0x27>;
//===----------------------------------------------------------------------===//
// GFX11
diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp
index d317ca4e1194a..fc5d7519bdffe 100644
--- a/llvm/lib/TargetParser/TargetParser.cpp
+++ b/llvm/lib/TargetParser/TargetParser.cpp
@@ -519,6 +519,7 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T,
break;
case GK_GFX1170:
// TODO-GFX1170: Update features map for gfx1170
+ Features["dot11-insts"] = true;
Features["fp8-conversion-insts"] = true;
[[fallthrough]];
case GK_GFX1153:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
index 796f6b84b1d14..5891456364fa7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
@@ -1,8 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 < %s | FileCheck -check-prefixes=GCN,GFX1170 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1170 < %s | FileCheck -check-prefixes=GCN,GFX1170 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
define float @test_amdgcn_dot4_f32_fp8_bf8(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_bf8 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -18,6 +26,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_bf8_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -34,6 +48,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_bf8_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -50,6 +70,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_bf8_fabs_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -67,6 +93,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_bf8_fneg_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -84,6 +116,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_fp8(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_fp8 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -99,6 +137,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_fp8_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -115,6 +159,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_fp8_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -131,6 +181,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_fp8_fabs_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -148,6 +204,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_fp8_fneg_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -165,6 +227,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_fp8(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_fp8 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -180,6 +248,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_fp8_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -196,6 +270,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_fp8_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -212,6 +292,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_fp8_fabs_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -229,6 +315,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_fp8_fp8_fneg_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -246,6 +338,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_bf8(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_bf8 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -261,6 +359,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_bf8_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -277,6 +381,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_bf8_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -293,6 +403,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_bf8_fabs_fneg(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs_fneg:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs_fneg:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -310,6 +426,12 @@ entry:
}
define float @test_amdgcn_dot4_f32_bf8_bf8_fneg_fabs(i32 %a, i32 %b, float %c) {
+; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg_fabs:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg_fabs:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -333,3 +455,5 @@ declare float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %c)
declare float @llvm.fabs.f32(float %a)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}
diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p.s
new file mode 100644
index 0000000000000..eb2ad1c3faa15
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p.s
@@ -0,0 +1,122 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1170 %s | FileCheck --check-prefix=GFX1170 %s
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_lo:[0,0,1]
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x9c]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_hi:[0,0,1]
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x24,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_fp8_bf8 v0, s0, v2, v3
+// GFX1170: v_dot4_f32_fp8_bf8 v0, s0, v2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x00,0x04,0x0e,0x1c]
+
+v_dot4_f32_fp8_bf8 v0, v1, s0, v3
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, s0, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x01,0x0c,0x1c]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, s0
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, s0 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x02,0x18]
+
+v_dot4_f32_fp8_bf8 v0, 1.0, v2, v3
+// GFX1170: v_dot4_f32_fp8_bf8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0xf2,0x04,0x0e,0x1c]
+
+v_dot4_f32_fp8_bf8 v0, v1, 1.0, v3
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0xe5,0x0d,0x1c]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, 1.0
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0xca,0x1b]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, 1
+// GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x06,0x1a]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_lo:[0,0,1]
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x9c]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_hi:[0,0,1]
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x25,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_bf8_fp8 v0, s0, v2, v3
+// GFX1170: v_dot4_f32_bf8_fp8 v0, s0, v2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x00,0x04,0x0e,0x1c]
+
+v_dot4_f32_bf8_fp8 v0, v1, s0, v3
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, s0, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x01,0x0c,0x1c]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, s0
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, s0 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x02,0x18]
+
+v_dot4_f32_bf8_fp8 v0, 1.0, v2, v3
+// GFX1170: v_dot4_f32_bf8_fp8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0xf2,0x04,0x0e,0x1c]
+
+v_dot4_f32_bf8_fp8 v0, v1, 1.0, v3
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0xe5,0x0d,0x1c]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, 1.0
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0xca,0x1b]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, 1
+// GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x06,0x1a]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_lo:[0,0,1]
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x9c]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_hi:[0,0,1]
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x26,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_fp8_fp8 v0, s0, v2, v3
+// GFX1170: v_dot4_f32_fp8_fp8 v0, s0, v2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x00,0x04,0x0e,0x1c]
+
+v_dot4_f32_fp8_fp8 v0, v1, s0, v3
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, s0, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x01,0x0c,0x1c]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, s0
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, s0 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x02,0x18]
+
+v_dot4_f32_fp8_fp8 v0, 1.0, v2, v3
+// GFX1170: v_dot4_f32_fp8_fp8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0xf2,0x04,0x0e,0x1c]
+
+v_dot4_f32_fp8_fp8 v0, v1, 1.0, v3
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0xe5,0x0d,0x1c]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, 1.0
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0xca,0x1b]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, 1
+// GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x06,0x1a]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_lo:[0,0,1]
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x9c]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[0,0,1]
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x27,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot4_f32_bf8_bf8 v0, s0, v2, v3
+// GFX1170: v_dot4_f32_bf8_bf8 v0, s0, v2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x00,0x04,0x0e,0x1c]
+
+v_dot4_f32_bf8_bf8 v0, v1, s0, v3
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, s0, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x01,0x0c,0x1c]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, s0
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, s0 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x02,0x18]
+
+v_dot4_f32_bf8_bf8 v0, 1.0, v2, v3
+// GFX1170: v_dot4_f32_bf8_bf8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0xf2,0x04,0x0e,0x1c]
+
+v_dot4_f32_bf8_bf8 v0, v1, 1.0, v3
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0xe5,0x0d,0x1c]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, 1.0
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0xca,0x1b]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, 1
+// GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x06,0x1a]
diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16.s
new file mode 100644
index 0000000000000..5e393987e9f0f
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16.s
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x24,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x1b,0x00,0xff]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 row_shr:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX12: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 row_shr:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x24,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x1f,0x0d,0x11]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 row_shl:15
+// GFX12: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x25,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x0f,0x01,0xff]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 row_ror:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX12: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 row_ror:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x25,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x2f,0x0d,0x11]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 row_mirror
+// GFX12: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x26,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x40,0x01,0xff]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 row_half_mirror row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX12: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 row_half_mirror row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x26,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x41,0x0d,0x11]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 row_share:15
+// GFX12: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 row_share:15 row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x27,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x5f,0x01,0xff]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 row_xmask:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX12: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 row_xmask:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x27,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x6f,0x0d,0x11]
diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16_err.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16_err.s
new file mode 100644
index 0000000000000..27e49e3a9877b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp16_err.s
@@ -0,0 +1,24 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1170 %s 2>&1 | FileCheck --check-prefix=GFX1170 --implicit-check-not=error: %s
+
+// check for error with sgpr or imm operands
+
+v_dot4_f32_fp8_bf8 v0, s0, v2, v3 quad_perm:[3,2,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_bf8 v0, v1, s0, v3 row_shr:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, s0 row_shl:15
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_fp8 v0, 1.0, v2, v3 row_ror:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_fp8 v0, v1, 1.0, v3 row_mirror
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, 1.0 row_half_mirror row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, 1 row_share:15
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8.s
new file mode 100644
index 0000000000000..5785cd9bd44ec
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8.s
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x24,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1
+// GFX1170: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x24,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x25,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1
+// GFX1170: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x25,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x26,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1
+// GFX1170: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x26,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x27,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1
+// GFX1170: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x27,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8_err.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8_err.s
new file mode 100644
index 0000000000000..ca17d103eb651
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_dpp8_err.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1170 %s 2>&1 | FileCheck --check-prefix=GFX1170 --implicit-check-not=error: %s
+
+// check for error with sgpr or imm operands
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] row_mask:0x1
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_bf8 v0, s0, v2, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_fp8 v0, v1, s0, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, s0 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_fp8 v0, 1.0, v2, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_fp8 v0, v1, 1.0, v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, 1.0 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, 1 dpp8:[0,1,2,3,4,5,6,7]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_err.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_err.s
new file mode 100644
index 0000000000000..d69c751006e03
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3p_err.s
@@ -0,0 +1,133 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1170 %s 2>&1 | FileCheck --check-prefix=GFX1170 --implicit-check-not=error: %s
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 clamp
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 op_sel:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 op_sel:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 op_sel:[0,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 op_sel_hi:[0,1,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 op_sel_hi:[1,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 op_sel_hi:[1,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_lo:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_lo:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_hi:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_hi:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 clamp
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 op_sel:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 op_sel:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 op_sel:[0,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 op_sel_hi:[0,1,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 op_sel_hi:[1,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 op_sel_hi:[1,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_lo:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_lo:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_hi:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_hi:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 clamp
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 op_sel:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 op_sel:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 op_sel:[0,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 op_sel_hi:[0,1,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 op_sel_hi:[1,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 op_sel_hi:[1,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_lo:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_lo:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_hi:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_hi:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 clamp
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 op_sel:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 op_sel:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 op_sel:[0,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 op_sel_hi:[0,1,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 op_sel_hi:[1,0,1]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 op_sel_hi:[1,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_lo:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_lo:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_lo operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[1,0,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
+
+v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[0,1,0]
+// GFX1170: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p.txt
new file mode 100644
index 0000000000000..6a0590bb485ee
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p.txt
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1170 %s
+
+0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x9c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x9c]
+
+0x00,0x44,0x24,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x24,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x24,0xcc,0x01,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, s1, v2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x04,0x0e,0x1c]
+
+0x00,0x40,0x24,0xcc,0x01,0x05,0x0c,0x1c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, s2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x0c,0x1c]
+
+0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x18
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, s3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x18]
+
+0x00,0x40,0x24,0xcc,0xf2,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x24,0xcc,0xf2,0x04,0x0e,0x1c]
+
+0x00,0x40,0x24,0xcc,0x01,0xe5,0x0d,0x1c
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0xe5,0x0d,0x1c]
+
+0x00,0x40,0x24,0xcc,0x01,0x05,0xca,0x1b
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0xca,0x1b]
+
+0x00,0x40,0x24,0xcc,0x01,0x05,0x06,0x1a
+# GFX1170: v_dot4_f32_fp8_bf8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x24,0xcc,0x01,0x05,0x06,0x1a]
+
+0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x9c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x9c]
+
+0x00,0x44,0x25,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x25,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x25,0xcc,0x01,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, s1, v2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x04,0x0e,0x1c]
+
+0x00,0x40,0x25,0xcc,0x01,0x05,0x0c,0x1c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, s2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x0c,0x1c]
+
+0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x18
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, s3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x18]
+
+0x00,0x40,0x25,0xcc,0xf2,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x25,0xcc,0xf2,0x04,0x0e,0x1c]
+
+0x00,0x40,0x25,0xcc,0x01,0xe5,0x0d,0x1c
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0xe5,0x0d,0x1c]
+
+0x00,0x40,0x25,0xcc,0x01,0x05,0xca,0x1b
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0xca,0x1b]
+
+0x00,0x40,0x25,0xcc,0x01,0x05,0x06,0x1a
+# GFX1170: v_dot4_f32_bf8_fp8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x25,0xcc,0x01,0x05,0x06,0x1a]
+
+0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x9c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x9c]
+
+0x00,0x44,0x26,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x26,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x26,0xcc,0x01,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, s1, v2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x04,0x0e,0x1c]
+
+0x00,0x40,0x26,0xcc,0x01,0x05,0x0c,0x1c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, s2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x0c,0x1c]
+
+0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x18
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, s3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x18]
+
+0x00,0x40,0x26,0xcc,0xf2,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x26,0xcc,0xf2,0x04,0x0e,0x1c]
+
+0x00,0x40,0x26,0xcc,0x01,0xe5,0x0d,0x1c
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0xe5,0x0d,0x1c]
+
+0x00,0x40,0x26,0xcc,0x01,0x05,0xca,0x1b
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0xca,0x1b]
+
+0x00,0x40,0x26,0xcc,0x01,0x05,0x06,0x1a
+# GFX1170: v_dot4_f32_fp8_fp8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x26,0xcc,0x01,0x05,0x06,0x1a]
+
+0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x9c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x9c]
+
+0x00,0x44,0x27,0xcc,0x01,0x05,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0x27,0xcc,0x01,0x05,0x0e,0x1c]
+
+0x00,0x40,0x27,0xcc,0x01,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, s1, v2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x04,0x0e,0x1c]
+
+0x00,0x40,0x27,0xcc,0x01,0x05,0x0c,0x1c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, s2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x0c,0x1c]
+
+0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x18
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, s3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x18]
+
+0x00,0x40,0x27,0xcc,0xf2,0x04,0x0e,0x1c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, 1.0, v2, v3 ; encoding: [0x00,0x40,0x27,0xcc,0xf2,0x04,0x0e,0x1c]
+
+0x00,0x40,0x27,0xcc,0x01,0xe5,0x0d,0x1c
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, 1.0, v3 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0xe5,0x0d,0x1c]
+
+0x00,0x40,0x27,0xcc,0x01,0x05,0xca,0x1b
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, 1.0 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0xca,0x1b]
+
+0x00,0x40,0x27,0xcc,0x01,0x05,0x06,0x1a
+# GFX1170: v_dot4_f32_bf8_bf8 v0, v1, v2, 1 ; encoding: [0x00,0x40,0x27,0xcc,0x01,0x05,0x06,0x1a]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp16.txt
new file mode 100644
index 0000000000000..6842ec47d4f6d
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp16.txt
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1170 %s
+
+# GFX1170: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x24,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x1b,0x00,0xff]
+0x00,0x40,0x24,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x1b,0x00,0xff
+
+# GFX1170: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 row_shr:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x24,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x1f,0x0d,0x11]
+0x00,0x40,0x24,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x1f,0x0d,0x11
+
+# GFX1170: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x25,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x0f,0x01,0xff]
+0x00,0x40,0x25,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x0f,0x01,0xff
+
+# GFX1170: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 row_ror:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x25,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x2f,0x0d,0x11]
+0x00,0x40,0x25,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x2f,0x0d,0x11
+
+# GFX1170: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x26,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x40,0x01,0xff]
+0x00,0x40,0x26,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x40,0x01,0xff
+
+# GFX1170: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 row_half_mirror row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x26,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x41,0x0d,0x11]
+0x00,0x40,0x26,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x41,0x0d,0x11
+
+# GFX1170: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 row_share:15 row_mask:0xf bank_mask:0xf ; encoding: [0x00,0x40,0x27,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x5f,0x01,0xff]
+0x00,0x40,0x27,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x5f,0x01,0xff
+
+# GFX1170: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 row_xmask:15 row_mask:0x1 bank_mask:0x1 bound_ctrl:1 fi:1 ; encoding: [0x00,0x40,0x27,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x6f,0x0d,0x11]
+0x00,0x40,0x27,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x6f,0x0d,0x11
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp8.txt
new file mode 100644
index 0000000000000..dc3cc999d5930
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_dpp8.txt
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1170 %s
+
+# GFX1170: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x24,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x24,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_fp8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x24,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x24,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x25,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x25,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_bf8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x25,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x25,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x26,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x26,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_fp8_fp8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x26,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x26,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x40,0x27,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x27,0xcc,0xe9,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
+
+# GFX1170: v_dot4_f32_bf8_bf8_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0x00,0x40,0x27,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa]
+0x00,0x40,0x27,0xcc,0xea,0x04,0x0e,0x1c,0x01,0x88,0xc6,0xfa
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_err.txt
new file mode 100644
index 0000000000000..fdd49927f74a5
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3p_err.txt
@@ -0,0 +1,144 @@
+# RUN: not llvm-mc -disassemble -triple=amdgcn -mcpu=gfx1170 -show-encoding %s 2>&1 | FileCheck --implicit-check-not=warning: --check-prefix=GFX1170 %s
+
+# v_dot4_f32_fp8_bf8
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0xc0,0x24,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x48,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x50,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x60,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x00,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x41,0x24,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x42,0x24,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
+
+
+# v_dot4_f32_bf8_fp8
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0xc0,0x25,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x48,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x50,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x60,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x00,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x41,0x25,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x42,0x25,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
+
+
+# v_dot4_f32_fp8_fp8
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0xc0,0x26,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x48,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x50,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x60,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x00,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x41,0x26,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x42,0x26,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
+
+
+# v_dot4_f32_bf8_bf8
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0xc0,0x27,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x48,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x50,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x60,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x00,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x41,0x27,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX1170: warning: invalid instruction encoding
+[0x00,0x42,0x27,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
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