[clang] [CIR][NEON] Add lowering support for `vceqzd_s64` (PR #179779)

[Andrzej Warzyński via cfe-commits]

================
@@ -1941,7 +1941,9 @@ def CIR_CmpOpKind : CIR_I32EnumAttr<"CmpOpKind", "compare operation kind", [
   I32EnumAttrCase<"gt", 2>,
   I32EnumAttrCase<"ge", 3>,
   I32EnumAttrCase<"eq", 4>,
-  I32EnumAttrCase<"ne", 5>
+  I32EnumAttrCase<"ne", 5>,
+  // Floating-point only predicates
+  I32EnumAttrCase<"fcmp_first", 20> // TODO: Replace with a real FP compare
----------------
banach-space wrote:

Thanks for sharing this context!

> This does mean that we can't express things like "ordered and not equal" but so far that's been OK because you can't express that directly in C/C++.

Looks like all existing tests for AArch64 builtins use the ordered variants, which means that we don't need to model the difference at the CIR level. At least not for AArch64 builtins. Let me revert this.

https://github.com/llvm/llvm-project/pull/179779