[clang] [mlir] [CIR][AArch64] Add lowering for predicated SVE svdup builtins (zeroing) (PR #175976)
Andrzej WarzyĆski via cfe-commits
cfe-commits at lists.llvm.org
Thu Feb 5 06:55:29 PST 2026
================
@@ -126,6 +126,81 @@ bool CIRGenFunction::getAArch64SVEProcessedOperands(
return true;
}
+// Reinterpret the input predicate so that it can be used to correctly isolate
+// the elements of the specified datatype.
+mlir::Value CIRGenFunction::emitSVEpredicateCast(mlir::Value *pred,
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banach-space wrote:
Good catch, thank you!
https://github.com/llvm/llvm-project/pull/175976
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