[clang] [llvm] [RISCV] Add SpacemiT A100 processor definition (PR #174052)

[Mark Zhuang via cfe-commits]

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@@ -735,6 +735,38 @@ def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
                                                TuneZExtWFusion,
                                                TuneShiftedZExtWFusion]>;
 
+def SPACEMIT_A100 : RISCVProcessorModel<"spacemit-a100",
+                                        SpacemitX60Model,
+                                        !listconcat(
+                                        !listremove(RVA23S64Features,
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zqb-all wrote:

The kernel directly uses macro definitions and self-defined CSR values, without relying on the compiler.

[#define CSR_SSTATEEN0		0x10c](https://github.com/torvalds/linux/blob/5fd0a1df5d05ad066e5618ccdd3d0fa6cb686c27/arch/riscv/include/asm/csr.h#L313)


 If a project does not define its own CSR macros but depends on CSR names defined in the compiler

https://github.com/llvm/llvm-project/blob/85c50299172bbd36ac345d5f50bce4bfee1e5667/llvm/lib/Target/RISCV/RISCVSystemOperands.td#L194-L196

we could consider adding checks based on `-march` in the future

https://github.com/llvm/llvm-project/pull/174052