[clang] [llvm] [RISCV][llvm] Rename zvqdotq to zvdot4a8i (PR #179393)
Brandon Wu via cfe-commits
cfe-commits at lists.llvm.org
Mon Feb 2 22:55:19 PST 2026
https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/179393
>From 4ba96947706fd231c10c13f10c160d659b01af22 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 2 Feb 2026 21:05:19 -0800
Subject: [PATCH 1/4] [RISCV][llvm] Rename zvqdotq to zvdot4a8i
The renaming PR is here: https://github.com/riscv/riscv-isa-manual/pull/2576
---
clang/include/clang/Basic/riscv_vector.td | 16 +-
.../non-policy/non-overloaded/vdota4_vv.c} | 103 ++--
.../non-policy/non-overloaded/vdota4_vx.c} | 102 ++--
.../non-policy/non-overloaded/vdota4su_vv.c | 118 ++++
.../non-policy/non-overloaded/vdota4su_vx.c} | 82 +--
.../non-policy/non-overloaded/vdota4u_vv.c} | 84 +--
.../non-policy/non-overloaded/vdota4u_vx.c} | 82 +--
.../non-policy/non-overloaded/vdota4us_vx.c | 117 ++++
.../non-policy/overloaded/vdota4_vv.c} | 103 ++--
.../non-policy/overloaded/vdota4_vx.c} | 102 ++--
.../non-policy/overloaded/vdota4su_vv.c | 118 ++++
.../non-policy/overloaded/vdota4su_vx.c} | 82 +--
.../non-policy/overloaded/vdota4u_vv.c} | 84 +--
.../non-policy/overloaded/vdota4u_vx.c} | 82 +--
.../non-policy/overloaded/vdota4us_vx.c | 117 ++++
.../policy/non-overloaded/vdota4_vv.c} | 215 ++++---
.../policy/non-overloaded/vdota4_vx.c} | 205 +++----
.../policy/non-overloaded/vdota4su_vv.c | 232 +++++++
.../policy/non-overloaded/vdota4su_vx.c} | 162 ++---
.../policy/non-overloaded/vdota4u_vv.c} | 194 +++---
.../policy/non-overloaded/vdota4u_vx.c} | 178 +++---
.../policy/non-overloaded/vdota4us_vx.c | 230 +++++++
.../policy/overloaded/vdota4_vv.c} | 215 ++++---
.../policy/overloaded/vdota4_vx.c} | 205 +++----
.../zvdot4a8i/policy/overloaded/vdota4su_vv.c | 232 +++++++
.../policy/overloaded/vdota4su_vx.c} | 162 ++---
.../policy/overloaded/vdota4u_vv.c} | 194 +++---
.../policy/overloaded/vdota4u_vx.c} | 178 +++---
.../zvdot4a8i/policy/overloaded/vdota4us_vx.c | 230 +++++++
.../non-policy/non-overloaded/vqdot_vv.c | 117 ----
.../non-policy/non-overloaded/vqdot_vx.c | 117 ----
.../zvqdotq/non-policy/overloaded/vqdot_vv.c | 117 ----
.../zvqdotq/non-policy/overloaded/vqdot_vx.c | 117 ----
.../zvqdotq/policy/non-overloaded/vqdot_vv.c | 229 -------
.../zvqdotq/policy/non-overloaded/vqdot_vx.c | 227 -------
.../zvqdotq/policy/overloaded/vqdot_vv.c | 229 -------
.../zvqdotq/policy/overloaded/vqdot_vx.c | 227 -------
.../Driver/print-supported-extensions-riscv.c | 2 +-
.../test/Preprocessor/riscv-target-features.c | 12 +-
llvm/docs/RISCVUsage.rst | 2 +-
llvm/include/llvm/IR/IntrinsicsRISCV.td | 20 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 48 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
...oZvqdotq.td => RISCVInstrInfoZvdot4a8i.td} | 68 +--
.../Target/RISCV/RISCVSelectionDAGInfo.cpp | 6 +-
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 6 +-
llvm/test/CodeGen/RISCV/attributes.ll | 8 +-
llvm/test/CodeGen/RISCV/features-info.ll | 2 +-
llvm/test/CodeGen/RISCV/pr148084.ll | 2 +-
...-zvqdotq.ll => fixed-vectors-zvdot4a8i.ll} | 262 ++++----
.../RISCV/rvv/{vqdotu.ll => vdota4.ll} | 164 ++---
llvm/test/CodeGen/RISCV/rvv/vdota4su.ll | 337 ++++++++++
.../RISCV/rvv/{vqdotsu.ll => vdota4u.ll} | 164 ++---
llvm/test/CodeGen/RISCV/rvv/vdota4us.ll | 170 ++++++
llvm/test/CodeGen/RISCV/rvv/vqdot.ll | 337 ----------
llvm/test/CodeGen/RISCV/rvv/vqdotus.ll | 170 ------
...{zvqdotq-sdnode.ll => zvdot4a8i-sdnode.ll} | 148 ++---
llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll | 6 +-
llvm/test/MC/RISCV/attribute-arch.s | 4 +-
...{zvqdotq-invalid.s => zvdot4a8i-invalid.s} | 10 +-
llvm/test/MC/RISCV/rvv/zvdot4a8i.s | 93 +++
llvm/test/MC/RISCV/rvv/zvqdotq.s | 93 ---
.../RISCV/partial-reduce-dot-product.ll | 574 +++++++++---------
.../TargetParser/RISCVISAInfoTest.cpp | 2 +-
65 files changed, 4162 insertions(+), 4162 deletions(-)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/non-overloaded/vqdotu_vv.c => zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c} (65%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/non-overloaded/vqdotu_vx.c => zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c} (65%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/non-overloaded/vqdotsu_vx.c => zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c} (60%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/non-overloaded/vqdotsu_vv.c => zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c} (71%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/non-overloaded/vqdotus_vx.c => zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c} (71%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/overloaded/vqdotu_vv.c => zvdot4a8i/non-policy/overloaded/vdota4_vv.c} (66%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/overloaded/vqdotu_vx.c => zvdot4a8i/non-policy/overloaded/vdota4_vx.c} (66%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/overloaded/vqdotsu_vx.c => zvdot4a8i/non-policy/overloaded/vdota4su_vx.c} (61%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/overloaded/vqdotsu_vv.c => zvdot4a8i/non-policy/overloaded/vdota4u_vv.c} (72%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/non-policy/overloaded/vqdotus_vx.c => zvdot4a8i/non-policy/overloaded/vdota4u_vx.c} (72%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/overloaded/vqdotu_vv.c => zvdot4a8i/policy/non-overloaded/vdota4_vv.c} (63%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/overloaded/vqdotu_vx.c => zvdot4a8i/policy/non-overloaded/vdota4_vx.c} (65%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/non-overloaded/vqdotsu_vx.c => zvdot4a8i/policy/non-overloaded/vdota4su_vx.c} (60%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/non-overloaded/vqdotsu_vv.c => zvdot4a8i/policy/non-overloaded/vdota4u_vv.c} (66%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/non-overloaded/vqdotus_vx.c => zvdot4a8i/policy/non-overloaded/vdota4u_vx.c} (70%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/non-overloaded/vqdotu_vv.c => zvdot4a8i/policy/overloaded/vdota4_vv.c} (63%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/non-overloaded/vqdotu_vx.c => zvdot4a8i/policy/overloaded/vdota4_vx.c} (65%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/overloaded/vqdotsu_vx.c => zvdot4a8i/policy/overloaded/vdota4su_vx.c} (61%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/overloaded/vqdotsu_vv.c => zvdot4a8i/policy/overloaded/vdota4u_vv.c} (67%)
rename clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/{zvqdotq/policy/overloaded/vqdotus_vx.c => zvdot4a8i/policy/overloaded/vdota4u_vx.c} (70%)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vv.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vx.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vv.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vx.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vv.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vx.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vv.c
delete mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vx.c
rename llvm/lib/Target/RISCV/{RISCVInstrInfoZvqdotq.td => RISCVInstrInfoZvdot4a8i.td} (66%)
rename llvm/test/CodeGen/RISCV/rvv/{fixed-vectors-zvqdotq.ll => fixed-vectors-zvdot4a8i.ll} (89%)
rename llvm/test/CodeGen/RISCV/rvv/{vqdotu.ll => vdota4.ll} (62%)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
rename llvm/test/CodeGen/RISCV/rvv/{vqdotsu.ll => vdota4u.ll} (62%)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vdota4us.ll
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vqdot.ll
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
rename llvm/test/CodeGen/RISCV/rvv/{zvqdotq-sdnode.ll => zvdot4a8i-sdnode.ll} (91%)
rename llvm/test/MC/RISCV/rvv/{zvqdotq-invalid.s => zvdot4a8i-invalid.s} (50%)
create mode 100644 llvm/test/MC/RISCV/rvv/zvdot4a8i.s
delete mode 100644 llvm/test/MC/RISCV/rvv/zvqdotq.s
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index c899dc70fc0b7..718725555c845 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2085,8 +2085,8 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
}
}
-// Zvqdotq
-multiclass RVVVQDOTQBuiltinSet<list<list<string>> suffixes_prototypes> {
+// Zvdot4a8i
+multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> {
let UnMaskedPolicyScheme = HasPolicyOperand,
HasMaskedOffOperand = false,
OverloadedName = NAME,
@@ -2095,14 +2095,14 @@ multiclass RVVVQDOTQBuiltinSet<list<list<string>> suffixes_prototypes> {
}
}
-// Only SEW=32 is defined for zvqdotq so far, and since inputs are in fact four
+// Only SEW=32 is defined for zvdot4a8i so far, and since inputs are in fact four
// 8-bit integer bundles, we use unsigned type to represent all of them
-let RequiredFeatures = ["zvqdotq"] in {
- defm vqdot : RVVVQDOTQBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"],
+let RequiredFeatures = ["zvdot4a8i"] in {
+ defm vdota4 : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"],
["vx", "v", "vv(FixedSEW:8)vUe"]]>;
- defm vqdotu : RVVVQDOTQBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"],
+ defm vdota4u : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"],
["vx", "Uv", "UvUv(FixedSEW:8)UvUe"]]>;
- defm vqdotsu : RVVVQDOTQBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"],
+ defm vdota4su : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"],
["vx", "v", "vv(FixedSEW:8)vUe"]]>;
- defm vqdotus : RVVVQDOTQBuiltinSet<[["vx", "v", "vv(FixedSEW:8)UvUe"]]>;
+ defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vv(FixedSEW:8)UvUe"]]>;
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c
similarity index 65%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c
index cd43ecf51ee11..2c95e12dbd0ab 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c
@@ -1,118 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
- vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32mf2(vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32mf2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1(vuint32m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m1(vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m1(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2(vuint32m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m2(vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4(vuint32m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m4(vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8(vuint32m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m8(vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m8(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32mf2_m(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
+ vint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m1_m(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m1_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m2_m(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m4_m(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m4_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m8_m(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m8_m(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c
similarity index 65%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c
index a4c446cc92949..421a96b2191b0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c
@@ -1,117 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32mf2(vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1(vuint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32m1(vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2(vuint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32m2(vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4(vuint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32m4(vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8(vuint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32m8(vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32mf2_m(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m1_m(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m2_m(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m4_m(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m8_m(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c
new file mode 100644
index 0000000000000..107edf58c4ed3
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c
@@ -0,0 +1,118 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2,
+ vuint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32mf2(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vuint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32m1(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vuint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32m2(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vuint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32m4(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vuint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32m8(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_m(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_m(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m1_m(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_m(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m2_m(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_m(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m4_m(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_m(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m8_m(vm, vd, vs2, vs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotsu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c
similarity index 60%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotsu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c
index 69fe2912ef868..13ca40622de6d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotsu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c
@@ -1,117 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
+vint32mf2_t test_vdota4su_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32mf2(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdota4su_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m1(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdota4su_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m2(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdota4su_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m4(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdota4su_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m8(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vint32m1_t test_vdota4su_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m1_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vint32m2_t test_vdota4su_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m4_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m8_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotsu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c
similarity index 71%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotsu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c
index 370ada7a61210..ca314eede5e59 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotsu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c
@@ -1,118 +1,118 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vv_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32mf2(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32mf2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vuint8m1_t vs1,
+vuint32m1_t test_vdota4u_vv_u32m1(vuint32m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32m1(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m1(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vuint8m2_t vs1,
+vuint32m2_t test_vdota4u_vv_u32m2(vuint32m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32m2(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vuint8m4_t vs1,
+vuint32m4_t test_vdota4u_vv_u32m4(vuint32m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32m4(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vuint8m8_t vs1,
+vuint32m8_t test_vdota4u_vv_u32m8(vuint32m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32m8(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m8(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32mf2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vuint32m1_t test_vdota4u_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m1_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m1_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vuint32m2_t test_vdota4u_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vuint32m4_t test_vdota4u_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m4_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m4_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vuint32m8_t test_vdota4u_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m8_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m8_m(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotus_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c
similarity index 71%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotus_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c
index a48d0ac16c036..6997e11de90d7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotus_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c
@@ -1,117 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2(vint32mf2_t vd, vuint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vx_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32mf2(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
+vuint32m1_t test_vdota4u_vx_u32m1(vuint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32m1(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
+vuint32m2_t test_vdota4u_vx_u32m2(vuint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32m2(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
+vuint32m4_t test_vdota4u_vx_u32m4(vuint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32m4(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
+vuint32m8_t test_vdota4u_vx_u32m8(vuint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32m8(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
+vuint32m1_t test_vdota4u_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m1_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
+vuint32m2_t test_vdota4u_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+vuint32m4_t test_vdota4u_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m4_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+vuint32m8_t test_vdota4u_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m8_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c
new file mode 100644
index 0000000000000..6cf6620f59a39
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c
@@ -0,0 +1,117 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2(vint32mf2_t vd, vuint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32mf2(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m1(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m2(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m4(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m8(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_m(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_m(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m1_m(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_m(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m2_m(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_m(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m4_m(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_m(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m8_m(vm, vd, vs2, rs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c
similarity index 66%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c
index a48a6ea979f9e..43a42ae69b56f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c
@@ -1,118 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
- vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotu(vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1(vuint32m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2(vuint32m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4(vuint32m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8(vuint32m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
+ vint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c
similarity index 66%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c
index 146246337a717..b823c6820c14c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c
@@ -1,117 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu(vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1(vuint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2(vuint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4(vuint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8(vuint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu(vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c
new file mode 100644
index 0000000000000..a388d95ce0dda
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c
@@ -0,0 +1,118 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2,
+ vuint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4su(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vuint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vuint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vuint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vuint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_m(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_m(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_m(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_m(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_m(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotsu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c
similarity index 61%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotsu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c
index 18cdd8505021b..04744d117ccc0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotsu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c
@@ -1,117 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
+vint32mf2_t test_vdota4su_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdota4su_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdota4su_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdota4su_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdota4su_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vint32m1_t test_vdota4su_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vint32m2_t test_vdota4su_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotsu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c
similarity index 72%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotsu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c
index 51194c376200d..96326a92842d1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotsu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c
@@ -1,118 +1,118 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vv_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotsu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vuint8m1_t vs1,
+vuint32m1_t test_vdota4u_vv_u32m1(vuint32m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vuint8m2_t vs1,
+vuint32m2_t test_vdota4u_vv_u32m2(vuint32m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vuint8m4_t vs1,
+vuint32m4_t test_vdota4u_vv_u32m4(vuint32m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vuint8m8_t vs1,
+vuint32m8_t test_vdota4u_vv_u32m8(vuint32m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1,
size_t vl) {
- return __riscv_vqdotsu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vuint32m1_t test_vdota4u_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vuint32m2_t test_vdota4u_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vuint32m4_t test_vdota4u_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vuint32m8_t test_vdota4u_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotus_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c
similarity index 72%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotus_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c
index 280753edef991..f99ffec09ac3e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdotus_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c
@@ -1,117 +1,117 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2(vint32mf2_t vd, vuint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vx_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus(vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
+vuint32m1_t test_vdota4u_vx_u32m1(vuint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus(vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
+vuint32m2_t test_vdota4u_vx_u32m2(vuint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus(vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
+vuint32m4_t test_vdota4u_vx_u32m4(vuint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus(vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
+vuint32m8_t test_vdota4u_vx_u32m8(vuint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus(vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
+vuint32m1_t test_vdota4u_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
+vuint32m2_t test_vdota4u_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+vuint32m4_t test_vdota4u_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+vuint32m8_t test_vdota4u_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c
new file mode 100644
index 0000000000000..567e69af7c493
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c
@@ -0,0 +1,117 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2(vint32mf2_t vd, vuint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_m(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_m(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_m(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_m(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_m(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c
similarity index 63%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c
index fd6bea58855c5..3876109d14542 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c
@@ -1,238 +1,229 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
- vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+ vint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32mf2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m1_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32m8_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, vuint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, vuint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, vuint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, vuint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, vuint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, vuint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, vuint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, vuint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c
similarity index 65%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c
index b8064b08391d9..8d1fec7845353 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c
@@ -1,230 +1,227 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tu(vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_vx_i32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c
new file mode 100644
index 0000000000000..b7c4af525c0d0
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c
@@ -0,0 +1,232 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tu(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+ vuint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32mf2_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tu(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m1_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tu(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m2_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tu(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m4_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tu(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m8_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tum(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tum(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tum(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tum(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tum(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tumu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tumu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+ vint8m1_t vs2, vuint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tumu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+ vint8m2_t vs2, vuint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tumu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tumu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_mu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_mu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_mu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_mu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_mu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotsu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c
similarity index 60%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotsu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c
index ee0fef5f79a1a..75fb6881b9b01 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotsu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c
@@ -1,229 +1,229 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+vint32mf2_t test_vdota4su_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32mf2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdota4su_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m1_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdota4su_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdota4su_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdota4su_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32m8_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vint32m1_t test_vdota4su_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vint32m2_t test_vdota4su_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdota4su_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdota4su_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vint32m1_t test_vdota4su_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vint32m2_t test_vdota4su_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotsu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c
similarity index 66%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotsu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c
index 40a37f334b17b..605502201bd57 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotsu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c
@@ -1,232 +1,238 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vv_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32mf2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32mf2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2,
+vuint32m1_t test_vdota4u_vv_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m1_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m1_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2,
+vuint32m2_t test_vdota4u_vv_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2,
+vuint32m4_t test_vdota4u_vv_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2,
+vuint32m8_t test_vdota4u_vv_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m8_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m8_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32mf2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
+vuint32m1_t test_vdota4u_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, vuint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_vv_u32m1_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
+vuint32m2_t test_vdota4u_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, vuint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_vv_u32m2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
+vuint32m4_t test_vdota4u_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+ vuint8m4_t vs2, vuint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_vv_u32m4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
+vuint32m8_t test_vdota4u_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+ vuint8m8_t vs2, vuint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_vv_u32m8_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32mf2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
- vint8m1_t vs2, vuint8m1_t vs1,
+vuint32m1_t test_vdota4u_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, vuint8m1_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m1_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
- vint8m2_t vs2, vuint8m2_t vs1,
+vuint32m2_t test_vdota4u_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, vuint8m2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
+vuint32m4_t test_vdota4u_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
+ vuint8m4_t vs2, vuint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_vv_u32m4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
+vuint32m8_t test_vdota4u_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
+ vuint8m8_t vs2, vuint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_vv_u32m8_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32mf2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
+vuint32m1_t test_vdota4u_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4u_vv_u32m1_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
+vuint32m2_t test_vdota4u_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4u_vv_u32m2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vuint32m4_t test_vdota4u_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vuint32m8_t test_vdota4u_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_vv_u32m8_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotus_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c
similarity index 70%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotus_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c
index ccf7a763623cf..1202186875053 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotus_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c
@@ -1,230 +1,230 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_tu(vint32mf2_t vd, vuint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vx_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32mf2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_tu(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_vx_i32m1_tu(vd, vs2, rs1, vl);
+vuint32m1_t test_vdota4u_vx_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_tu(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_vx_i32m2_tu(vd, vs2, rs1, vl);
+vuint32m2_t test_vdota4u_vx_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_tu(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_vx_i32m4_tu(vd, vs2, rs1, vl);
+vuint32m4_t test_vdota4u_vx_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_tu(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_vx_i32m8_tu(vd, vs2, rs1, vl);
+vuint32m8_t test_vdota4u_vx_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
+vuint32m1_t test_vdota4u_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
+vuint32m2_t test_vdota4u_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
+vuint32m4_t test_vdota4u_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+ vuint8m4_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
+vuint32m8_t test_vdota4u_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+ vuint8m8_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vuint32m1_t test_vdota4u_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vuint32m2_t test_vdota4u_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
+vuint32m4_t test_vdota4u_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint8m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
+vuint32m8_t test_vdota4u_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint8m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
+vuint32m1_t test_vdota4u_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
+vuint32m2_t test_vdota4u_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_vx_u32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+vuint32m4_t test_vdota4u_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+vuint32m8_t test_vdota4u_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_vx_u32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c
new file mode 100644
index 0000000000000..86bd3c21ec0c5
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c
@@ -0,0 +1,230 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tu(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_tu(vint32mf2_t vd, vuint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32mf2_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tu(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_tu(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m1_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tu(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_tu(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m2_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tu(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_tu(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m4_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tu(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_tu(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32m8_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tum(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tum(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
+ vuint8m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tum(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
+ vuint8m2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tum(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tum(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tumu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tumu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+ vuint8m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tumu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+ vuint8m2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tumu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
+ vuint8m4_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tumu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
+ vuint8m8_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_mu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_mu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_mu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_mu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_mu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c
similarity index 63%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c
index b12e5e1672fb8..577efdca1c6aa 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c
@@ -1,238 +1,229 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
- vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32mf2_tu(vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+ vint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m1_tu(vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m2_tu(vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m4_tu(vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m8_tu(vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32mf2_tum(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, vuint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m1_tum(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, vuint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m2_tum(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, vuint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m4_tum(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, vuint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m8_tum(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32mf2_tumu(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, vuint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m1_tumu(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, vuint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m2_tumu(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, vuint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m4_tumu(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, vuint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32m8_tumu(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, vuint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdotu_vv_u32mf2_mu(vm, vd, vs2, vs1, vl);
+vint32mf2_t test_vdota4_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m1_mu(vm, vd, vs2, vs1, vl);
+vint32m1_t test_vdota4_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m2_mu(vm, vd, vs2, vs1, vl);
+vint32m2_t test_vdota4_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m4_mu(vm, vd, vs2, vs1, vl);
+vint32m4_t test_vdota4_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotu_vv_u32m8_mu(vm, vd, vs2, vs1, vl);
+vint32m8_t test_vdota4_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c
similarity index 65%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c
index 9679c217933e4..b0102987ad72b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdotu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c
@@ -1,230 +1,227 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32mf2_tu(vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m1_tu(vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m2_tu(vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m4_tu(vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m8_tu(vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32mf2_tum(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m1_tum(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m2_tum(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m4_tum(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m8_tum(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32mf2_tumu(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m1_tumu(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m2_tumu(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint8m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m4_tumu(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
- vuint8m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m8_tumu(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vqdotu_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotu_vx_u32mf2_mu(vm, vd, vs2, rs1, vl);
+vint32mf2_t test_vdota4_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vqdotu_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m1_mu(vm, vd, vs2, rs1, vl);
+vint32m1_t test_vdota4_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vqdotu_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m2_mu(vm, vd, vs2, rs1, vl);
+vint32m2_t test_vdota4_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vqdotu_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m4_mu(vm, vd, vs2, rs1, vl);
+vint32m4_t test_vdota4_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vqdotu_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotu_vx_u32m8_mu(vm, vd, vs2, rs1, vl);
+vint32m8_t test_vdota4_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c
new file mode 100644
index 0000000000000..9fe9742eed25b
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c
@@ -0,0 +1,232 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tu(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+ vuint8mf2_t vs1, size_t vl) {
+ return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tu(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tu(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tu(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tu(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tum(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tum(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tum(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tum(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tum(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tumu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tumu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+ vint8m1_t vs2, vuint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tumu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+ vint8m2_t vs2, vuint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tumu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tumu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_mu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4su_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vint8mf2_t vs2, vuint8mf2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_mu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4su_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+ vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_mu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4su_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+ vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_mu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4su_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+ vuint8m4_t vs1, size_t vl) {
+ return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_mu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4su_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+ vuint8m8_t vs1, size_t vl) {
+ return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotsu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c
similarity index 61%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotsu_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c
index ecf714d8ad7a6..2508cc19f16c6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotsu_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c
@@ -1,229 +1,229 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+vint32mf2_t test_vdota4su_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdota4su_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdota4su_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdota4su_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdota4su_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vint32m1_t test_vdota4su_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vint32m2_t test_vdota4su_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdota4su_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdota4su_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdota4su_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
+vint32m1_t test_vdota4su_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
+vint32m2_t test_vdota4su_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vint32m4_t test_vdota4su_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vint32m8_t test_vdota4su_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotsu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c
similarity index 67%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotsu_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c
index ec07f00e105fe..9c6527ab686e3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotsu_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c
@@ -1,232 +1,238 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vv_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2,
+vuint32m1_t test_vdota4u_vv_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2,
+vuint32m2_t test_vdota4u_vv_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2,
+vuint32m4_t test_vdota4u_vv_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2,
+vuint32m8_t test_vdota4u_vv_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_tu(vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, vs1, vl);
+vuint32m1_t test_vdota4u_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, vuint8m1_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, vs1, vl);
+vuint32m2_t test_vdota4u_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, vuint8m2_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, vs1, vl);
+vuint32m4_t test_vdota4u_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+ vuint8m4_t vs2, vuint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_tum(vm, vd, vs2, vs1, vl);
+vuint32m8_t test_vdota4u_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+ vuint8m8_t vs2, vuint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
- vint8m1_t vs2, vuint8m1_t vs1,
+vuint32m1_t test_vdota4u_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, vuint8m1_t vs1,
size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
- vint8m2_t vs2, vuint8m2_t vs1,
+vuint32m2_t test_vdota4u_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, vuint8m2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, vs1, vl);
+vuint32m4_t test_vdota4u_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
+ vuint8m4_t vs2, vuint8m4_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_tumu(vm, vd, vs2, vs1, vl);
+vuint32m8_t test_vdota4u_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
+ vuint8m8_t vs2, vuint8m8_t vs1,
+ size_t vl) {
+ return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotsu_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vuint8mf2_t vs1,
+vuint32mf2_t test_vdota4u_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
+ vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotsu_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vuint8m1_t vs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, vs1, vl);
+vuint32m1_t test_vdota4u_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
+ return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotsu_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vuint8m2_t vs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, vs1, vl);
+vuint32m2_t test_vdota4u_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
+ return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotsu_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
+vuint32m4_t test_vdota4u_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotsu_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
+vuint32m8_t test_vdota4u_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
vuint8m8_t vs1, size_t vl) {
- return __riscv_vqdotsu_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotus_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c
similarity index 70%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotus_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c
index 0e39d69aa197a..e364a86a46684 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdotus_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c
@@ -1,230 +1,230 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_tu(vint32mf2_t vd, vuint8mf2_t vs2,
+vuint32mf2_t test_vdota4u_vx_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tu(vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_tu(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_tu(vd, vs2, rs1, vl);
+vuint32m1_t test_vdota4u_vx_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_tu(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_tu(vd, vs2, rs1, vl);
+vuint32m2_t test_vdota4u_vx_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_tu(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_tu(vd, vs2, rs1, vl);
+vuint32m4_t test_vdota4u_vx_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_tu(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdotus_tu(vd, vs2, rs1, vl);
+vuint32m8_t test_vdota4u_vx_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
+vuint32m1_t test_vdota4u_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
+vuint32m2_t test_vdota4u_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tum(vm, vd, vs2, rs1, vl);
+vuint32m4_t test_vdota4u_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+ vuint8m4_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tum(vm, vd, vs2, rs1, vl);
+vuint32m8_t test_vdota4u_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+ vuint8m8_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vuint32m1_t test_vdota4u_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint8m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vuint32m2_t test_vdota4u_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint8m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
+vuint32m4_t test_vdota4u_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint8m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
+vuint32m8_t test_vdota4u_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint8m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotus_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vqdotus_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vuint32mf2_t test_vdota4u_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
vuint8mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vqdotus_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotus_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vqdotus_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_mu(vm, vd, vs2, rs1, vl);
+vuint32m1_t test_vdota4u_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+ vuint8m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotus_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vqdotus_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_mu(vm, vd, vs2, rs1, vl);
+vuint32m2_t test_vdota4u_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+ vuint8m2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotus_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vqdotus_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+vuint32m4_t test_vdota4u_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotus_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vqdotus_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+vuint32m8_t test_vdota4u_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vqdotus_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c
new file mode 100644
index 0000000000000..b4b7f6ee8653c
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c
@@ -0,0 +1,230 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <sifive_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tu(
+// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_tu(vint32mf2_t vd, vuint8mf2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tu(
+// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_tu(vint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tu(
+// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_tu(vint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tu(
+// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_tu(vint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tu(
+// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_tu(vint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tum(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tum(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
+ vuint8m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tum(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
+ vuint8m2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tum(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tum(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tumu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tumu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+ vuint8m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tumu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+ vuint8m2_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tumu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
+ vuint8m4_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tumu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
+ vuint8m8_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_mu(
+// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vdota4us_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+ vuint8mf2_t vs2, uint32_t rs1,
+ size_t vl) {
+ return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_mu(
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vdota4us_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint8m1_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_mu(
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vdota4us_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint8m2_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_mu(
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vdota4us_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint8m4_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_mu(
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vdota4us_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint8m8_t vs2,
+ uint32_t rs1, size_t vl) {
+ return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vv.c
deleted file mode 100644
index b755708b374ea..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vv.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32mf2(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m1(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m2(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m4(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m8(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
- vint8mf2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m1_m(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m2_m(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m4_m(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m8_m(vm, vd, vs2, vs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vx.c
deleted file mode 100644
index 6e3bc5dabe42f..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vx.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32mf2(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m1(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m2(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m4(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m8(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m1_m(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m2_m(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m4_m(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m8_m(vm, vd, vs2, rs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vv.c
deleted file mode 100644
index d4c1a8c1e886e..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vv.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
- vint8mf2_t vs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, vs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vx.c
deleted file mode 100644
index 1be0af5ebab81..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vx.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot(vm, vd, vs2, rs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vv.c
deleted file mode 100644
index 8062c9378bf8d..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vv.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_tu(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
- vint8mf2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32mf2_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_tu(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m1_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_tu(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m2_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_tu(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m4_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_tu(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32m8_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdot_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vx.c
deleted file mode 100644
index f5286550676b1..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vx.c
+++ /dev/null
@@ -1,227 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_tu(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32mf2_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_tu(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m1_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_tu(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m2_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_tu(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m4_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_tu(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_vx_i32m8_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vv.c
deleted file mode 100644
index 23aeac87cfed9..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vv.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_tu(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
- vint8mf2_t vs1, size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_tu(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_tu(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_tu(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_tu(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vint8mf2_t vs1,
- size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vv_i32mf2_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vv_i32m1_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- vint8m1_t vs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vv_i32m2_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- vint8m2_t vs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vv_i32m4_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- vint8m4_t vs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, vs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vv_i32m8_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- vint8m8_t vs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, vs1, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vx.c
deleted file mode 100644
index 7c1ab30ddd595..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vx.c
+++ /dev/null
@@ -1,227 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <sifive_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_tu(
-// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_tu(
-// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_tu(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_tu(
-// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_tu(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_tu(
-// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_tu(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_tu(
-// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_tu(vint32m8_t vd, vint8m8_t vs2, uint32_t rs1,
- size_t vl) {
- return __riscv_vqdot_tu(vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tum(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_tumu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdot_vx_i32mf2_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vqdot_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint8mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdot_vx_i32m1_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vqdot_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdot_vx_i32m2_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vqdot_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdot_vx_i32m4_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vqdot_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, rs1, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdot_vx_i32m8_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
-//
-vint32m8_t test_vqdot_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,
- uint32_t rs1, size_t vl) {
- return __riscv_vqdot_mu(vm, vd, vs2, rs1, vl);
-}
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 8337d9f12fabd..521550ebe4539 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -249,7 +249,7 @@
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
-// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
+// CHECK-NEXT: zvdot4a8i 0.0 'Zvdot4a8i' (Vector quad widening 4D Dot Product)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index e315f75b15614..1bd18ec65cb7e 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -185,7 +185,7 @@
// CHECK-NOT: __riscv_zvfbfa {{.*$}}
// CHECK-NOT: __riscv_zvfofp8min {{.*$}}
// CHECK-NOT: __riscv_zvkgs {{.*$}}
-// CHECK-NOT: __riscv_zvqdotq {{.*$}}
+// CHECK-NOT: __riscv_zvdot4a8i {{.*$}}
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ia -E -dM %s \
@@ -1636,12 +1636,12 @@
// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvqdotq0p0 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQDOTQ-EXT %s
+// RUN: -march=rv32i_zve32x_zvdot4a8i0p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvqdotq0p0 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQDOTQ-EXT %s
-// CHECK-ZVQDOTQ-EXT: __riscv_zvqdotq 0{{$}}
+// RUN: -march=rv64i_zve32x_zvdot4a8i0p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
+// CHECK-ZVDOT4A8I-EXT: __riscv_zvdot4a8i 0{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izicfiss1p0 -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b58ecc105620a..8a9d3702ecd19 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -350,7 +350,7 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-svukte``
LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__.
-``experimental-zvqdotq``
+``experimental-zvdot4a8i``
LLVM implements the `0.0.1 draft specification <https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1>`__.
``experimental-smpmpmt``
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index f194ce99b52d1..555f81f7bbf1e 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1908,7 +1908,7 @@ let TargetPrefix = "riscv" in {
} // TargetPrefix = "riscv"
//===----------------------------------------------------------------------===//
-// Zvqdotq - Vector quad widening 4D Dot Product
+// Zvdot4a8i - Vector quad widening 4D Dot Product
//
// 8-bit Integer dot-product instructions performing the dot product between two
// 4-element vectors of 8-bit integer elements and accumulating it into a 32-bit
@@ -1917,7 +1917,7 @@ let TargetPrefix = "riscv" in {
// We use llvm_anyvector_ty and llvm_anyint_ty for future extensibility
// purpose but only EEW=32 is defined for now
// Input: (vector_in, vector_in, vector_in/scalar_in, vl, policy)
- class RISCVVQDOTUnMasked<bit HasVV>
+ class RISCVVDOTA4UnMasked<bit HasVV>
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty,
!if(HasVV, llvm_any_ty, llvm_anyint_ty),
@@ -1928,7 +1928,7 @@ let TargetPrefix = "riscv" in {
let VLOperand = 3;
}
// Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl, policy)
- class RISCVVQDOTMasked<bit HasVV>
+ class RISCVVDOTA4Masked<bit HasVV>
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty,
!if(HasVV, llvm_any_ty, llvm_anyint_ty),
@@ -1940,15 +1940,15 @@ let TargetPrefix = "riscv" in {
let VLOperand = 4;
}
- multiclass RISCVVQDOT<bit HasVV = 1> {
- def "int_riscv_" # NAME : RISCVVQDOTUnMasked<HasVV=HasVV>;
- def "int_riscv_" # NAME # "_mask" : RISCVVQDOTMasked<HasVV=HasVV>;
+ multiclass RISCVVDOTA4<bit HasVV = 1> {
+ def "int_riscv_" # NAME : RISCVVDOTA4UnMasked<HasVV=HasVV>;
+ def "int_riscv_" # NAME # "_mask" : RISCVVDOTA4Masked<HasVV=HasVV>;
}
- defm vqdot : RISCVVQDOT;
- defm vqdotu : RISCVVQDOT;
- defm vqdotsu : RISCVVQDOT;
- defm vqdotus : RISCVVQDOT<HasVV=0>;
+ defm vdota4 : RISCVVDOTA4;
+ defm vdota4u : RISCVVDOTA4;
+ defm vdota4su : RISCVVDOTA4;
+ defm vdota4us : RISCVVDOTA4<HasVV=0>;
} // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d681bb78014af..0033daf8c486b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -876,12 +876,12 @@ def FeatureStdExtZvksg
// Vector quad widening dot product
-def FeatureStdExtZvqdotq
+def FeatureStdExtZvdot4a8i
: RISCVExperimentalExtension<0, 0, "Vector quad widening 4D Dot Product",
[FeatureStdExtZve32x]>;
-def HasStdExtZvqdotq : Predicate<"Subtarget->hasStdExtZvqdotq()">,
- AssemblerPredicate<(all_of FeatureStdExtZvqdotq),
- "'Zvqdotq' (Vector quad widening 4D Dot Product)">;
+def HasStdExtZvdot4a8i : Predicate<"Subtarget->hasStdExtZvdot4a8i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvdot4a8i),
+ "'Zvdot4a8i' (Vector quad widening 4D Dot Product)">;
// Vector instruction predicates
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fd7de727e0f00..ba7622781ddfa 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1797,7 +1797,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
// zve32x is broken for partial_reduce_umla, but let's not make it worse.
- if (Subtarget.hasStdExtZvqdotq() && Subtarget.getELen() >= 64) {
+ if (Subtarget.hasStdExtZvdot4a8i() && Subtarget.getELen() >= 64) {
static const unsigned MLAOps[] = {ISD::PARTIAL_REDUCE_SMLA,
ISD::PARTIAL_REDUCE_UMLA,
ISD::PARTIAL_REDUCE_SUMLA};
@@ -9222,7 +9222,7 @@ SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
SelectionDAG &DAG) const {
- // Currently, only the vqdot and vqdotu case (from zvqdotq) should be legal.
+ // Currently, only the vdota4 and vdota4u case (from zvdot4a8i) should be legal.
// TODO: There are many other sub-cases we could potentially lower, are
// any of them worthwhile? Ex: via vredsum, vwredsum, vwwmaccu, etc..
SDLoc DL(Op);
@@ -9237,7 +9237,7 @@ SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
ArgVT.getVectorElementType() == MVT::i8);
(void)ArgVT;
- // The zvqdotq pseudos are defined with sources and destination both
+ // The zvdot4a8i pseudos are defined with sources and destination both
// being i32. This cast is needed for correctness to avoid incorrect
// .vx matching of i8 splats.
A = DAG.getBitcast(VT, A);
@@ -9254,13 +9254,13 @@ SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
unsigned Opc;
switch (Op.getOpcode()) {
case ISD::PARTIAL_REDUCE_SMLA:
- Opc = RISCVISD::VQDOT_VL;
+ Opc = RISCVISD::VDOTA4_VL;
break;
case ISD::PARTIAL_REDUCE_UMLA:
- Opc = RISCVISD::VQDOTU_VL;
+ Opc = RISCVISD::VDOTA4U_VL;
break;
case ISD::PARTIAL_REDUCE_SUMLA:
- Opc = RISCVISD::VQDOTSU_VL;
+ Opc = RISCVISD::VDOTA4SU_VL;
break;
default:
llvm_unreachable("Unexpected opcode");
@@ -20005,10 +20005,10 @@ static SDValue getZeroPaddedAdd(const SDLoc &DL, SDValue A, SDValue B,
return DAG.getInsertSubvector(DL, B, Res, 0);
}
-static SDValue foldReduceOperandViaVQDOT(SDValue InVec, const SDLoc &DL,
- SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget,
- const RISCVTargetLowering &TLI) {
+static SDValue foldReduceOperandViaVDOTA4(SDValue InVec, const SDLoc &DL,
+ SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget,
+ const RISCVTargetLowering &TLI) {
using namespace SDPatternMatch;
// Note: We intentionally do not check the legality of the reduction type.
// We want to handle the m4/m8 *src* types, and thus need to let illegal
@@ -20021,8 +20021,8 @@ static SDValue foldReduceOperandViaVQDOT(SDValue InVec, const SDLoc &DL,
// form).
SDValue A, B;
if (sd_match(InVec, m_AddLike(m_Value(A), m_Value(B)))) {
- SDValue AOpt = foldReduceOperandViaVQDOT(A, DL, DAG, Subtarget, TLI);
- SDValue BOpt = foldReduceOperandViaVQDOT(B, DL, DAG, Subtarget, TLI);
+ SDValue AOpt = foldReduceOperandViaVDOTA4(A, DL, DAG, Subtarget, TLI);
+ SDValue BOpt = foldReduceOperandViaVDOTA4(B, DL, DAG, Subtarget, TLI);
if (AOpt || BOpt) {
if (AOpt)
A = AOpt;
@@ -20094,13 +20094,13 @@ static SDValue foldReduceOperandViaVQDOT(SDValue InVec, const SDLoc &DL,
static SDValue performVECREDUCECombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget,
const RISCVTargetLowering &TLI) {
- if (!Subtarget.hasStdExtZvqdotq())
+ if (!Subtarget.hasStdExtZvdot4a8i())
return SDValue();
SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue InVec = N->getOperand(0);
- if (SDValue V = foldReduceOperandViaVQDOT(InVec, DL, DAG, Subtarget, TLI))
+ if (SDValue V = foldReduceOperandViaVDOTA4(InVec, DL, DAG, Subtarget, TLI))
return DAG.getNode(ISD::VECREDUCE_ADD, DL, VT, V);
return SDValue();
}
@@ -20424,8 +20424,8 @@ static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(Opc, DL, VT, Ops);
}
-static SDValue combineVqdotAccum(SDNode *N, SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget) {
+static SDValue combineVdota4Accum(SDNode *N, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
assert(N->getOpcode() == RISCVISD::ADD_VL || N->getOpcode() == ISD::ADD);
@@ -20441,21 +20441,21 @@ static SDValue combineVqdotAccum(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
- auto IsVqdotqOpc = [](unsigned Opc) {
+ auto IsVdota4Opc = [](unsigned Opc) {
switch (Opc) {
- case RISCVISD::VQDOT_VL:
- case RISCVISD::VQDOTU_VL:
- case RISCVISD::VQDOTSU_VL:
+ case RISCVISD::VDOTA4_VL:
+ case RISCVISD::VDOTA4U_VL:
+ case RISCVISD::VDOTA4SU_VL:
return true;
default:
return false;
}
};
- if (!IsVqdotqOpc(DotOp.getOpcode()))
+ if (!IsVdota4Opc(DotOp.getOpcode()))
std::swap(Addend, DotOp);
- if (!IsVqdotqOpc(DotOp.getOpcode()))
+ if (!IsVdota4Opc(DotOp.getOpcode()))
return SDValue();
auto [AddMask, AddVL] = [](SDNode *N, SelectionDAG &DAG,
@@ -21108,7 +21108,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return V;
if (SDValue V = combineToVWMACC(N, DAG, Subtarget))
return V;
- if (SDValue V = combineVqdotAccum(N, DAG, Subtarget))
+ if (SDValue V = combineVdota4Accum(N, DAG, Subtarget))
return V;
return performADDCombine(N, DCI, Subtarget);
}
@@ -21647,7 +21647,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return V;
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
return V;
- if (SDValue V = combineVqdotAccum(N, DAG, Subtarget))
+ if (SDValue V = combineVdota4Accum(N, DAG, Subtarget))
return V;
return combineToVWMACC(N, DAG, Subtarget);
case RISCVISD::VWADD_W_VL:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 21cc5b49f04ce..bd6f60308230a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2352,7 +2352,7 @@ include "RISCVInstrInfoZk.td"
// Vector
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvk.td"
-include "RISCVInstrInfoZvqdotq.td"
+include "RISCVInstrInfoZvdot4a8i.td"
include "RISCVInstrInfoZvfofp8min.td"
// Packed SIMD
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
similarity index 66%
rename from llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
rename to llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
index d27aaa64098b0..21d6aced16219 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
@@ -1,4 +1,4 @@
-//===-- RISCVInstrInfoZvqdot.td - 'Zvqdotq' instructions ---*- tablegen -*-===//
+//==-- RISCVInstrInfoZvdot4a8i.td - 'Zvdot4a8i' instructions -*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
//
-// This file describes the RISC-V instructions from the standard 'Zvqdotq'
+// This file describes the RISC-V instructions from the standard 'Zvdot4a8i'
// extension.
-// This version is still experimental as the 'Zvqdotq' extension hasn't been
+// This version is still experimental as the 'Zvdot4a8i' extension hasn't been
// ratified yet.
//
//===----------------------------------------------------------------------===//
@@ -17,7 +17,7 @@
// Instructions
//===----------------------------------------------------------------------===//
-class VQDOTVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VDOTA4VV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $vs1$vm"> {
@@ -27,7 +27,7 @@ class VQDOTVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
let Constraints = "$vd = $vd_wb";
}
-class VQDOTVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VDOTA4VX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVX<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, GPR:$rs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $rs1$vm"> {
@@ -37,31 +37,31 @@ class VQDOTVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
let Constraints = "$vd = $vd_wb";
}
-let Predicates = [HasStdExtZvqdotq] in {
- def VQDOT_VV : VQDOTVV<0b101100, OPMVV, "vqdot.vv">;
- def VQDOT_VX : VQDOTVX<0b101100, OPMVX, "vqdot.vx">;
- def VQDOTU_VV : VQDOTVV<0b101000, OPMVV, "vqdotu.vv">;
- def VQDOTU_VX : VQDOTVX<0b101000, OPMVX, "vqdotu.vx">;
- def VQDOTSU_VV : VQDOTVV<0b101010, OPMVV, "vqdotsu.vv">;
- def VQDOTSU_VX : VQDOTVX<0b101010, OPMVX, "vqdotsu.vx">;
- def VQDOTUS_VX : VQDOTVX<0b101110, OPMVX, "vqdotus.vx">;
-} // Predicates = [HasStdExtZvqdotq]
+let Predicates = [HasStdExtZvdot4a8i] in {
+ def VDOTA4_VV : VDOTA4VV<0b101100, OPMVV, "vdota4.vv">;
+ def VDOTA4_VX : VDOTA4VX<0b101100, OPMVX, "vdota4.vx">;
+ def VDOTA4U_VV : VDOTA4VV<0b101000, OPMVV, "vdota4u.vv">;
+ def VDOTA4U_VX : VDOTA4VX<0b101000, OPMVX, "vdota4u.vx">;
+ def VDOTA4SU_VV : VDOTA4VV<0b101010, OPMVV, "vdota4su.vv">;
+ def VDOTA4SU_VX : VDOTA4VX<0b101010, OPMVX, "vdota4su.vx">;
+ def VDOTA4US_VX : VDOTA4VX<0b101110, OPMVX, "vdota4us.vx">;
+} // Predicates = [HasStdExtZvdot4a8i]
//===----------------------------------------------------------------------===//
// Helpers to define the VL patterns.
//===----------------------------------------------------------------------===//
let HasPassthruOp = true, HasMaskOp = true in {
- def riscv_vqdot_vl : RVSDNode<"VQDOT_VL", SDT_RISCVIntBinOp_VL>;
- def riscv_vqdotu_vl : RVSDNode<"VQDOTU_VL", SDT_RISCVIntBinOp_VL>;
- def riscv_vqdotsu_vl : RVSDNode<"VQDOTSU_VL", SDT_RISCVIntBinOp_VL>;
+ def riscv_vdota4_vl : RVSDNode<"VDOTA4_VL", SDT_RISCVIntBinOp_VL>;
+ def riscv_vdota4u_vl : RVSDNode<"VDOTA4U_VL", SDT_RISCVIntBinOp_VL>;
+ def riscv_vdota4su_vl : RVSDNode<"VDOTA4SU_VL", SDT_RISCVIntBinOp_VL>;
} // let HasPassthruOp = true, HasMaskOp = true
//===----------------------------------------------------------------------===//
// Pseudo Instructions for CodeGen
//===----------------------------------------------------------------------===//
-multiclass VPseudoVQDOT_VV_VX {
+multiclass VPseudoVDOTA4_VV_VX {
foreach m = MxSet<32>.m in {
defm "" : VPseudoBinaryV_VV<m>,
SchedBinary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", m.MX,
@@ -72,15 +72,15 @@ multiclass VPseudoVQDOT_VV_VX {
}
}
-// TODO: Add isCommutable for VQDOT and VQDOTU
-let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0,
+// TODO: Add isCommutable for VDOTA4 and VDOTA4U
+let Predicates = [HasStdExtZvdot4a8i], mayLoad = 0, mayStore = 0,
hasSideEffects = 0 in {
- defm PseudoVQDOT : VPseudoVQDOT_VV_VX;
- defm PseudoVQDOTU : VPseudoVQDOT_VV_VX;
- defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX;
- // VQDOTUS does not have a VV variant
+ defm PseudoVDOTA4 : VPseudoVDOTA4_VV_VX;
+ defm PseudoVDOTA4U : VPseudoVDOTA4_VV_VX;
+ defm PseudoVDOTA4SU : VPseudoVDOTA4_VV_VX;
+ // VDOTA4US does not have a VV variant
foreach m = MxListVF4 in {
- defm "PseudoVQDOTUS_VX" : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m>;
+ defm "PseudoVDOTA4US_VX" : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m>;
}
}
@@ -89,11 +89,11 @@ let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0,
//===----------------------------------------------------------------------===//
defvar AllE32Vectors = [VI32MF2, VI32M1, VI32M2, VI32M4, VI32M8];
-defm : VPatBinaryVL_VV_VX<riscv_vqdot_vl, "PseudoVQDOT", AllE32Vectors, ExtraPreds=[HasStdExtZvqdotq]>;
-defm : VPatBinaryVL_VV_VX<riscv_vqdotu_vl, "PseudoVQDOTU", AllE32Vectors, ExtraPreds=[HasStdExtZvqdotq]>;
-defm : VPatBinaryVL_VV_VX<riscv_vqdotsu_vl, "PseudoVQDOTSU", AllE32Vectors, ExtraPreds=[HasStdExtZvqdotq]>;
+defm : VPatBinaryVL_VV_VX<riscv_vdota4_vl, "PseudoVDOTA4", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
+defm : VPatBinaryVL_VV_VX<riscv_vdota4u_vl, "PseudoVDOTA4U", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
+defm : VPatBinaryVL_VV_VX<riscv_vdota4su_vl, "PseudoVDOTA4SU", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
-// These VPat definitions are for vqdot because they have a different operand
+// These VPat definitions are for vdota4 because they have a different operand
// order with other ternary instructions (i.e. vop.vx vd, vs2, rs1)
multiclass VPatTernaryV_VX_AABX<string intrinsic, string instruction,
list<VTypeInfoToWide> info_pairs,
@@ -133,7 +133,7 @@ multiclass VPatTernaryV_VV_VX_AABX<string intrinsic, string instruction,
: VPatTernaryV_VV_AABX<intrinsic, instruction, info_pairs, ExtraPreds>,
VPatTernaryV_VX_AABX<intrinsic, instruction, info_pairs, ExtraPreds>;
-defset list<VTypeInfoToWide> VQDOTInfoPairs = {
+defset list<VTypeInfoToWide> VDOTA4InfoPairs = {
def : VTypeInfoToWide<VI8MF2, VI32MF2>;
def : VTypeInfoToWide<VI8M1, VI32M1>;
def : VTypeInfoToWide<VI8M2, VI32M2>;
@@ -141,7 +141,7 @@ defset list<VTypeInfoToWide> VQDOTInfoPairs = {
def : VTypeInfoToWide<VI8M8, VI32M8>;
}
-defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vqdot", "PseudoVQDOT", VQDOTInfoPairs, [HasStdExtZvqdotq]>;
-defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vqdotu", "PseudoVQDOTU", VQDOTInfoPairs, [HasStdExtZvqdotq]>;
-defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vqdotsu", "PseudoVQDOTSU", VQDOTInfoPairs, [HasStdExtZvqdotq]>;
-defm : VPatTernaryV_VX_AABX<"int_riscv_vqdotus", "PseudoVQDOTUS", VQDOTInfoPairs, [HasStdExtZvqdotq]>;
+defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vdota4", "PseudoVDOTA4", VDOTA4InfoPairs, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vdota4u", "PseudoVDOTA4U", VDOTA4InfoPairs, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vdota4su", "PseudoVDOTA4SU", VDOTA4InfoPairs, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VX_AABX<"int_riscv_vdota4us", "PseudoVDOTA4US", VDOTA4InfoPairs, [HasStdExtZvdot4a8i]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
index 8b66aa12c9be4..2315a7802f7c5 100644
--- a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
@@ -35,9 +35,9 @@ void RISCVSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
assert(N->getOperand(2).getOpcode() == ISD::TargetConstant &&
"Expected index to be a target constant!");
break;
- case RISCVISD::VQDOT_VL:
- case RISCVISD::VQDOTU_VL:
- case RISCVISD::VQDOTSU_VL: {
+ case RISCVISD::VDOTA4_VL:
+ case RISCVISD::VDOTA4U_VL:
+ case RISCVISD::VDOTA4SU_VL: {
EVT VT = N->getValueType(0);
assert(VT.isScalableVector() && VT.getVectorElementType() == MVT::i32 &&
"Expected result to be an i32 scalable vector");
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index dc4bf0784e2d1..a81d38af9c358 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -349,7 +349,7 @@ InstructionCost RISCVTTIImpl::getPartialReductionCost(
// zve32x is broken for partial_reduce_umla, but let's make sure we
// don't generate them.
- if (!ST->hasStdExtZvqdotq() || ST->getELen() < 64 ||
+ if (!ST->hasStdExtZvdot4a8i() || ST->getELen() < 64 ||
Opcode != Instruction::Add || !BinOp || *BinOp != Instruction::Mul ||
InputTypeA != InputTypeB || !InputTypeA->isIntegerTy(8) ||
!AccumType->isIntegerTy(32) || !VF.isKnownMultipleOf(4))
@@ -357,9 +357,9 @@ InstructionCost RISCVTTIImpl::getPartialReductionCost(
Type *Tp = VectorType::get(AccumType, VF.divideCoefficientBy(4));
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp);
- // Note: Asuming all vqdot* variants are equal cost
+ // Note: Asuming all vdota4* variants are equal cost
return LT.first *
- getRISCVInstructionCost(RISCV::VQDOT_VV, LT.second, CostKind);
+ getRISCVInstructionCost(RISCV::VDOTA4_VV, LT.second, CostKind);
}
bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 522dc3579deb1..26922fd413acb 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -109,7 +109,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV32ZVQDOTQ %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvdot4a8i %s -o - | FileCheck --check-prefix=RV32ZVDOT4A8I %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+zilsd %s -o - | FileCheck --check-prefix=RV32ZILSD %s
@@ -263,7 +263,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV64ZVQDOTQ %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvdot4a8i %s -o - | FileCheck --check-prefix=RV64ZVDOT4A8I %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
@@ -428,7 +428,7 @@
; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
-; RV32ZVQDOTQ: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0"
+; RV32ZVDOT4A8I: .attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p0_zve32x1p0_zvl32b1p0"
; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0"
@@ -580,7 +580,7 @@
; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
-; RV64ZVQDOTQ: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0"
+; RV64ZVDOT4A8I: .attribute 5, "rv64i2p1_zicsr2p0_zvdot4a8i0p0_zve32x1p0_zvl32b1p0"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index a8d2be4ace515..b0e3a80217bf4 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -40,10 +40,10 @@
; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).
; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).
; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements).
+; CHECK-NEXT: experimental-zvdot4a8i - 'Zvdot4a8i' (Vector quad widening 4D Dot Product).
; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).
; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).
; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
-; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product).
; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point).
; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available.
; CHECK-NEXT: h - 'H' (Hypervisor).
diff --git a/llvm/test/CodeGen/RISCV/pr148084.ll b/llvm/test/CodeGen/RISCV/pr148084.ll
index faeecb267a9da..b207374d4d41e 100644
--- a/llvm/test/CodeGen/RISCV/pr148084.ll
+++ b/llvm/test/CodeGen/RISCV/pr148084.ll
@@ -276,4 +276,4 @@ get_tx_mask.exit: ; preds = %._crit_edge.i, %bb
ret void
}
-attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
similarity index 89%
rename from llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
rename to llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
index e6ca6875e1412..f1211adcd2c09 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NODOT
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NODOT
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT64
-define i32 @vqdot_vv(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vqdot_vv:
+define i32 @vdota4_vv(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdota4_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -17,11 +17,11 @@ define i32 @vqdot_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv:
+; DOT-LABEL: vdota4_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -34,8 +34,8 @@ entry:
ret i32 %res
}
-define i32 @vqdot_vx_constant(<16 x i8> %a) {
-; CHECK-LABEL: vqdot_vx_constant:
+define i32 @vdota4_vx_constant(<16 x i8> %a) {
+; CHECK-LABEL: vdota4_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v8
@@ -53,8 +53,8 @@ entry:
ret i32 %res
}
-define i32 @vqdot_vx_constant_swapped(<16 x i8> %a) {
-; CHECK-LABEL: vqdot_vx_constant_swapped:
+define i32 @vdota4_vx_constant_swapped(<16 x i8> %a) {
+; CHECK-LABEL: vdota4_vx_constant_swapped:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v8
@@ -72,8 +72,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotu_vv(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vqdotu_vv:
+define i32 @vdota4u_vv(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdota4u_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -85,11 +85,11 @@ define i32 @vqdotu_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv:
+; DOT-LABEL: vdota4u_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotu.vv v10, v8, v9
+; DOT-NEXT: vdota4u.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -102,8 +102,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotu_vx_constant(<16 x i8> %a) {
-; CHECK-LABEL: vqdotu_vx_constant:
+define i32 @vdota4u_vx_constant(<16 x i8> %a) {
+; CHECK-LABEL: vdota4u_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
@@ -121,8 +121,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotsu_vv(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv:
+define i32 @vdota4su_vv(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -134,11 +134,11 @@ define i32 @vqdotsu_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv:
+; DOT-LABEL: vdota4su_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotsu.vv v10, v8, v9
+; DOT-NEXT: vdota4su.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -151,8 +151,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotsu_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv_swapped:
+define i32 @vdota4su_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv_swapped:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -164,11 +164,11 @@ define i32 @vqdotsu_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_swapped:
+; DOT-LABEL: vdota4su_vv_swapped:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotsu.vv v10, v8, v9
+; DOT-NEXT: vdota4su.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -236,7 +236,7 @@ define i32 @reduce_of_sext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v9, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -263,7 +263,7 @@ define i32 @reduce_of_zext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v9, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotu.vv v10, v8, v9
+; DOT-NEXT: vdota4u.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -274,8 +274,8 @@ entry:
ret i32 %res
}
-define i32 @vqdot_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vqdot_vv_accum:
+define i32 @vdota4_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdota4_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -287,11 +287,11 @@ define i32 @vqdot_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_accum:
+; DOT-LABEL: vdota4_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vqdot.vv v16, v8, v9
+; DOT-NEXT: vdota4.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -308,8 +308,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdotu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vqdotu_vv_accum:
+define i32 @vdota4u_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdota4u_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -321,11 +321,11 @@ define i32 @vqdotu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv_accum:
+; DOT-LABEL: vdota4u_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vqdotu.vv v16, v8, v9
+; DOT-NEXT: vdota4u.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -342,8 +342,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdotsu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vqdotsu_vv_accum:
+define i32 @vdota4su_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdota4su_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -355,11 +355,11 @@ define i32 @vqdotsu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_accum:
+; DOT-LABEL: vdota4su_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vqdotsu.vv v16, v8, v9
+; DOT-NEXT: vdota4su.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -376,8 +376,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdot_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vqdot_vv_scalar_add:
+define i32 @vdota4_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdota4_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -389,11 +389,11 @@ define i32 @vqdot_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_scalar_add:
+; DOT-LABEL: vdota4_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -407,8 +407,8 @@ entry:
ret i32 %add
}
-define i32 @vqdotu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vqdotu_vv_scalar_add:
+define i32 @vdota4u_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdota4u_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -420,11 +420,11 @@ define i32 @vqdotu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv_scalar_add:
+; DOT-LABEL: vdota4u_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotu.vv v10, v8, v9
+; DOT-NEXT: vdota4u.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -438,8 +438,8 @@ entry:
ret i32 %add
}
-define i32 @vqdotsu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vqdotsu_vv_scalar_add:
+define i32 @vdota4su_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdota4su_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -451,11 +451,11 @@ define i32 @vqdotsu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_scalar_add:
+; DOT-LABEL: vdota4su_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotsu.vv v10, v8, v9
+; DOT-NEXT: vdota4su.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -469,8 +469,8 @@ entry:
ret i32 %add
}
-define i32 @vqdot_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
-; NODOT-LABEL: vqdot_vv_split:
+define i32 @vdota4_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
+; NODOT-LABEL: vdota4_vv_split:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -485,12 +485,12 @@ define i32 @vqdot_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_split:
+; DOT-LABEL: vdota4_vv_split:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdot.vv v12, v8, v9
-; DOT-NEXT: vqdot.vv v12, v10, v11
+; DOT-NEXT: vdota4.vv v12, v8, v9
+; DOT-NEXT: vdota4.vv v12, v10, v11
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -507,8 +507,8 @@ entry:
ret i32 %sum
}
-define <1 x i32> @vqdot_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vqdot_vv_partial_reduce_v1i32_v4i8:
+define <1 x i32> @vdota4_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdota4_vv_partial_reduce_v1i32_v4i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -526,11 +526,11 @@ define <1 x i32> @vqdot_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_partial_reduce_v1i32_v4i8:
+; DOT-LABEL: vdota4_vv_partial_reduce_v1i32_v4i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -541,8 +541,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vqdotu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vqdotu_vv_partial_reduce_v1i32_v4i8:
+define <1 x i32> @vdota4u_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdota4u_vv_partial_reduce_v1i32_v4i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -559,11 +559,11 @@ define <1 x i32> @vqdotu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b)
; NODOT-NEXT: vadd.vv v8, v8, v9
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv_partial_reduce_v1i32_v4i8:
+; DOT-LABEL: vdota4u_vv_partial_reduce_v1i32_v4i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vqdotu.vv v10, v8, v9
+; DOT-NEXT: vdota4u.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -574,8 +574,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vqdotu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vqdotu_vx_partial_reduce:
+define <1 x i32> @vdota4u_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdota4u_vx_partial_reduce:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vzext.vf4 v9, v8
@@ -591,7 +591,7 @@ define <1 x i32> @vqdotu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v9
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vx_partial_reduce:
+; DOT-LABEL: vdota4u_vx_partial_reduce:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; DOT-NEXT: vmv.s.x v9, zero
@@ -599,7 +599,7 @@ define <1 x i32> @vqdotu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; DOT-NEXT: vmv.v.x v10, a0
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; DOT-NEXT: vqdotu.vv v9, v8, v10
+; DOT-NEXT: vdota4u.vv v9, v8, v10
; DOT-NEXT: vmv1r.v v8, v9
; DOT-NEXT: ret
entry:
@@ -609,8 +609,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vqdot_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vqdot_vx_partial_reduce:
+define <1 x i32> @vdota4_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdota4_vx_partial_reduce:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vsext.vf4 v9, v8
@@ -627,7 +627,7 @@ define <1 x i32> @vqdot_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v9
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vx_partial_reduce:
+; DOT-LABEL: vdota4_vx_partial_reduce:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; DOT-NEXT: vmv.s.x v9, zero
@@ -635,7 +635,7 @@ define <1 x i32> @vqdot_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; DOT-NEXT: vmv.v.x v10, a0
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; DOT-NEXT: vqdot.vv v9, v8, v10
+; DOT-NEXT: vdota4.vv v9, v8, v10
; DOT-NEXT: vmv1r.v v8, v9
; DOT-NEXT: ret
entry:
@@ -645,8 +645,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vqdotsu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv_partial_reduce_v1i32_v4i8:
+define <1 x i32> @vdota4su_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv_partial_reduce_v1i32_v4i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -664,11 +664,11 @@ define <1 x i32> @vqdotsu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b)
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_partial_reduce_v1i32_v4i8:
+; DOT-LABEL: vdota4su_vv_partial_reduce_v1i32_v4i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vqdotsu.vv v10, v8, v9
+; DOT-NEXT: vdota4su.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -679,8 +679,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vqdotsu_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv_partial_reduce_swapped:
+define <1 x i32> @vdota4su_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv_partial_reduce_swapped:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -698,11 +698,11 @@ define <1 x i32> @vqdotsu_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_partial_reduce_swapped:
+; DOT-LABEL: vdota4su_vv_partial_reduce_swapped:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vqdotsu.vv v10, v8, v9
+; DOT-NEXT: vdota4su.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -713,8 +713,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vqdotsu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-LABEL: vqdotsu_vx_partial_reduce:
+define <1 x i32> @vdota4su_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
+; CHECK-LABEL: vdota4su_vx_partial_reduce:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsext.vf4 v9, v8
@@ -737,8 +737,8 @@ entry:
}
-define <2 x i32> @vqdot_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
-; NODOT-LABEL: vqdot_vv_partial_reduce_v2i32_v8i8:
+define <2 x i32> @vdota4_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
+; NODOT-LABEL: vdota4_vv_partial_reduce_v2i32_v8i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -757,11 +757,11 @@ define <2 x i32> @vqdot_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v12
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_partial_reduce_v2i32_v8i8:
+; DOT-LABEL: vdota4_vv_partial_reduce_v2i32_v8i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -772,8 +772,8 @@ entry:
ret <2 x i32> %res
}
-define <2 x i32> @vqdot_vv_partial_reduce_v2i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
-; CHECK-LABEL: vqdot_vv_partial_reduce_v2i32_v64i8:
+define <2 x i32> @vdota4_vv_partial_reduce_v2i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; CHECK-LABEL: vdota4_vv_partial_reduce_v2i32_v64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -949,8 +949,8 @@ entry:
ret <2 x i32> %res
}
-define <4 x i32> @vqdot_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vqdot_vv_partial_reduce_v4i32_v16i8:
+define <4 x i32> @vdota4_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdota4_vv_partial_reduce_v4i32_v16i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -969,11 +969,11 @@ define <4 x i32> @vqdot_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %b
; NODOT-NEXT: vadd.vv v8, v8, v16
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_partial_reduce_v4i32_v16i8:
+; DOT-LABEL: vdota4_vv_partial_reduce_v4i32_v16i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -984,8 +984,8 @@ entry:
ret <4 x i32> %res
}
-define <16 x i32> @vqdot_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
-; NODOT-LABEL: vqdot_vv_partial_reduce_v16i32_v64i8:
+define <16 x i32> @vdota4_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; NODOT-LABEL: vdota4_vv_partial_reduce_v16i32_v64i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: li a0, 32
; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -1012,11 +1012,11 @@ define <16 x i32> @vqdot_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8>
; NODOT-NEXT: vadd.vv v8, v8, v24
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_partial_reduce_v16i32_v64i8:
+; DOT-LABEL: vdota4_vv_partial_reduce_v16i32_v64i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; DOT-NEXT: vmv.v.i v16, 0
-; DOT-NEXT: vqdot.vv v16, v8, v12
+; DOT-NEXT: vdota4.vv v16, v8, v12
; DOT-NEXT: vmv.v.v v8, v16
; DOT-NEXT: ret
entry:
@@ -1027,8 +1027,8 @@ entry:
ret <16 x i32> %res
}
-define <4 x i32> @vqdot_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b, <4 x i32> %accum) {
-; NODOT-LABEL: vqdot_vv_partial_reduce_m1_accum:
+define <4 x i32> @vdota4_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b, <4 x i32> %accum) {
+; NODOT-LABEL: vdota4_vv_partial_reduce_m1_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -1049,10 +1049,10 @@ define <4 x i32> @vqdot_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b, <
; NODOT-NEXT: vadd.vv v8, v8, v16
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_partial_reduce_m1_accum:
+; DOT-LABEL: vdota4_vv_partial_reduce_m1_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -1063,8 +1063,8 @@ entry:
ret <4 x i32> %res
}
-define <16 x i32> @vqdot_vv_partial_reduce3(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: vqdot_vv_partial_reduce3:
+define <16 x i32> @vdota4_vv_partial_reduce3(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: vdota4_vv_partial_reduce3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v8
@@ -1080,8 +1080,8 @@ entry:
}
; Test legalization - type split
-define <64 x i32> @vqdotsu_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv_partial_v64i32_v256i8:
+define <64 x i32> @vdota4su_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv_partial_v64i32_v256i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: addi sp, sp, -16
; NODOT-NEXT: .cfi_def_cfa_offset 16
@@ -1298,7 +1298,7 @@ define <64 x i32> @vqdotsu_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b
; NODOT-NEXT: .cfi_def_cfa_offset 0
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_partial_v64i32_v256i8:
+; DOT-LABEL: vdota4su_vv_partial_v64i32_v256i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: addi sp, sp, -16
; DOT-NEXT: .cfi_def_cfa_offset 16
@@ -1345,7 +1345,7 @@ define <64 x i32> @vqdotsu_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b
; DOT-NEXT: add a0, sp, a0
; DOT-NEXT: addi a0, a0, 16
; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vqdotsu.vv v0, v16, v8
+; DOT-NEXT: vdota4su.vv v0, v16, v8
; DOT-NEXT: csrr a0, vlenb
; DOT-NEXT: slli a0, a0, 3
; DOT-NEXT: mv a1, a0
@@ -1356,7 +1356,7 @@ define <64 x i32> @vqdotsu_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b
; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; DOT-NEXT: addi a0, sp, 16
; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vqdotsu.vv v24, v16, v8
+; DOT-NEXT: vdota4su.vv v24, v16, v8
; DOT-NEXT: vmv.v.v v8, v0
; DOT-NEXT: vmv.v.v v16, v24
; DOT-NEXT: csrr a0, vlenb
@@ -1375,8 +1375,8 @@ entry:
}
; Test legalization - integer promote
-define <4 x i31> @vqdotsu_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
-; NODOT-LABEL: vqdotsu_vv_partial_v4i31_v16i7:
+define <4 x i31> @vdota4su_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
+; NODOT-LABEL: vdota4su_vv_partial_v4i31_v16i7:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vzext.vf4 v12, v8
@@ -1404,7 +1404,7 @@ define <4 x i31> @vqdotsu_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v16
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_partial_v4i31_v16i7:
+; DOT-LABEL: vdota4su_vv_partial_v4i31_v16i7:
; DOT: # %bb.0: # %entry
; DOT-NEXT: li a0, 127
; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
@@ -1413,7 +1413,7 @@ define <4 x i31> @vqdotsu_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
; DOT-NEXT: vsra.vi v10, v8, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v8, 0
-; DOT-NEXT: vqdotsu.vv v8, v10, v9
+; DOT-NEXT: vdota4su.vv v8, v10, v9
; DOT-NEXT: ret
entry:
%a.ext = sext <16 x i7> %a to <16 x i31>
@@ -1425,8 +1425,8 @@ entry:
; Test legalization - expand
-define <1 x i32> @vqdotsu_vv_partial_v1i32_v2i8(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: vqdotsu_vv_partial_v1i32_v2i8:
+define <1 x i32> @vdota4su_vv_partial_v1i32_v2i8(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: vdota4su_vv_partial_v1i32_v2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsext.vf2 v10, v8
@@ -1446,10 +1446,10 @@ entry:
}
; TODO: This isn't legal, but we could split it into two halves, and use
-; a pair of slides + two vqdotsu_vv here. Or alternatively, the mul
+; a pair of slides + two vdota4su_vv here. Or alternatively, the mul
; sequence + one vredsum, or a vadd reduce tree.
-define <1 x i32> @vqdotsu_vv_partial_v1i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: vqdotsu_vv_partial_v1i32_v8i8:
+define <1 x i32> @vdota4su_vv_partial_v1i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: vdota4su_vv_partial_v1i32_v8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsext.vf2 v10, v8
@@ -1511,7 +1511,7 @@ define <4 x i32> @partial_of_sext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
-; DOT-NEXT: vqdot.vv v9, v8, v10
+; DOT-NEXT: vdota4.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
@@ -1544,7 +1544,7 @@ define <4 x i32> @partial_of_zext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
-; DOT-NEXT: vqdotu.vv v9, v8, v10
+; DOT-NEXT: vdota4u.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
@@ -1553,8 +1553,8 @@ entry:
ret <4 x i32> %res
}
-define i32 @vqdot_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vqdot_vv_accum_disjoint_or:
+define i32 @vdota4_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdota4_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -1567,11 +1567,11 @@ define i32 @vqdot_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_accum_disjoint_or:
+; DOT-LABEL: vdota4_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vqdot.vv v16, v8, v9
+; DOT-NEXT: vdota4.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -1588,8 +1588,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdot_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; CHECK-LABEL: vqdot_vv_accum_or:
+define i32 @vdota4_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; CHECK-LABEL: vdota4_vv_accum_or:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
@@ -1610,8 +1610,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdotu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vqdotu_vv_accum_disjoint_or:
+define i32 @vdota4u_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdota4u_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -1623,11 +1623,11 @@ define i32 @vqdotu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv_accum_disjoint_or:
+; DOT-LABEL: vdota4u_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vqdotu.vv v16, v8, v9
+; DOT-NEXT: vdota4u.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -1644,8 +1644,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdotsu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vqdotsu_vv_accum_disjoint_or:
+define i32 @vdota4su_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdota4su_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -1658,11 +1658,11 @@ define i32 @vqdotsu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32>
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_accum_disjoint_or:
+; DOT-LABEL: vdota4su_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vqdotsu.vv v16, v8, v9
+; DOT-NEXT: vdota4su.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
diff --git a/llvm/test/CodeGen/RISCV/rvv/vqdotu.ll b/llvm/test/CodeGen/RISCV/rvv/vdota4.ll
similarity index 62%
rename from llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdota4.ll
index 1c9f42ead5f70..981265b506073 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdota4.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-define <vscale x 1 x i32> @intrinsic_vqdotu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdota4_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
-; CHECK-NEXT: vqdotu.vv v8, v9, v10
+; CHECK-NEXT: vdota4.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
@@ -20,14 +20,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdota4_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; CHECK-NEXT: vqdotu.vv v8, v9, v10
+; CHECK-NEXT: vdota4.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
@@ -36,14 +36,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdota4_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
-; CHECK-NEXT: vqdotu.vv v8, v10, v12
+; CHECK-NEXT: vdota4.vv v8, v10, v12
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
@@ -52,14 +52,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdota4_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vqdotu.vv v8, v12, v16
+; CHECK-NEXT: vdota4.vv v8, v12, v16
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
@@ -68,15 +68,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotu_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdota4_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdotu.vv v8, v16, v24
+; CHECK-NEXT: vdota4.vv v8, v16, v24
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
@@ -85,14 +85,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vqdotu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdota4_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vqdotu.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdota4.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
@@ -102,14 +102,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdota4_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vqdotu.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdota4.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
@@ -119,14 +119,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdota4_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vqdotu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vdota4.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
@@ -136,14 +136,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdota4_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vqdotu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vdota4.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
@@ -153,15 +153,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotu_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdota4_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdotu.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vdota4.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
@@ -171,14 +171,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vqdotu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdota4_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vqdotu.vx v8, v9, a0
+; CHECK-NEXT: vdota4.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
i32 %2,
@@ -187,14 +187,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdota4_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vqdotu.vx v8, v9, a0
+; CHECK-NEXT: vdota4.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
i32 %2,
@@ -203,14 +203,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdota4_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vqdotu.vx v8, v10, a0
+; CHECK-NEXT: vdota4.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
i32 %2,
@@ -219,14 +219,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdota4_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vqdotu.vx v8, v12, a0
+; CHECK-NEXT: vdota4.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
i32 %2,
@@ -235,14 +235,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotu_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdota4_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdotu.vx v8, v16, a0
+; CHECK-NEXT: vdota4.vx v8, v16, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
i32 %2,
@@ -251,14 +251,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vqdotu_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdota4_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vqdotu.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdota4.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
i32 %2,
@@ -268,14 +268,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotu_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdota4_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vqdotu.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdota4.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
i32 %2,
@@ -285,14 +285,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotu_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdota4_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vqdotu.vx v8, v10, a0, v0.t
+; CHECK-NEXT: vdota4.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
i32 %2,
@@ -302,14 +302,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotu_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdota4_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vqdotu.vx v8, v12, a0, v0.t
+; CHECK-NEXT: vdota4.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
i32 %2,
@@ -319,14 +319,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotu_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotu_mask_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdota4_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdotu.vx v8, v16, a0, v0.t
+; CHECK-NEXT: vdota4.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
i32 %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdota4su.ll b/llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
new file mode 100644
index 0000000000000..66953a54cc6ff
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
@@ -0,0 +1,337 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvdot4a8i \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i32> @intrinsic_vdota4su_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vv_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vdota4su.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i8> %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vdota4su_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vv_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vdota4su.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> %0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i8> %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vdota4su_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vv_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vdota4su.vv v8, v10, v12
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> %0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i8> %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vdota4su_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vv_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vdota4su.vv v8, v12, v16
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> %0,
+ <vscale x 32 x i8> %1,
+ <vscale x 32 x i8> %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vdota4su_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vv_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vl8r.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT: vdota4su.vv v8, v16, v24
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> %0,
+ <vscale x 64 x i8> %1,
+ <vscale x 64 x i8> %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vdota4su_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
+; CHECK-NEXT: vdota4su.vv v8, v9, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i8> %2,
+ <vscale x 1 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vdota4su_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT: vdota4su.vv v8, v9, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> %0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i8> %2,
+ <vscale x 2 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vdota4su_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
+; CHECK-NEXT: vdota4su.vv v8, v10, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> %0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i8> %2,
+ <vscale x 4 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vdota4su_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
+; CHECK-NEXT: vdota4su.vv v8, v12, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> %0,
+ <vscale x 32 x i8> %1,
+ <vscale x 32 x i8> %2,
+ <vscale x 8 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vdota4su_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vl8r.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
+; CHECK-NEXT: vdota4su.vv v8, v16, v24, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> %0,
+ <vscale x 64 x i8> %1,
+ <vscale x 64 x i8> %2,
+ <vscale x 16 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vdota4su_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vx_nxv1i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT: vdota4su.vx v8, v9, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 4 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vdota4su_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vx_nxv2i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT: vdota4su.vx v8, v9, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.i32(
+ <vscale x 2 x i32> %0,
+ <vscale x 8 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vdota4su_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vx_nxv4i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT: vdota4su.vx v8, v10, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.i32(
+ <vscale x 4 x i32> %0,
+ <vscale x 16 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vdota4su_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vx_nxv8i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT: vdota4su.vx v8, v12, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.i32(
+ <vscale x 8 x i32> %0,
+ <vscale x 32 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vdota4su_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_vx_nxv16i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT: vdota4su.vx v8, v16, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.i32(
+ <vscale x 16 x i32> %0,
+ <vscale x 64 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vdota4su_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv1i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT: vdota4su.vx v8, v9, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 4 x i8> %1,
+ i32 %2,
+ <vscale x 1 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vdota4su_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv2i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT: vdota4su.vx v8, v9, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32(
+ <vscale x 2 x i32> %0,
+ <vscale x 8 x i8> %1,
+ i32 %2,
+ <vscale x 2 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vdota4su_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv4i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT: vdota4su.vx v8, v10, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32(
+ <vscale x 4 x i32> %0,
+ <vscale x 16 x i8> %1,
+ i32 %2,
+ <vscale x 4 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vdota4su_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv8i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT: vdota4su.vx v8, v12, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32(
+ <vscale x 8 x i32> %0,
+ <vscale x 32 x i8> %1,
+ i32 %2,
+ <vscale x 8 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vdota4su_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv16i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
+; CHECK-NEXT: vdota4su.vx v8, v16, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32(
+ <vscale x 16 x i32> %0,
+ <vscale x 64 x i8> %1,
+ i32 %2,
+ <vscale x 16 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll b/llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
similarity index 62%
rename from llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
index f54ec9b4308fd..4a36bac18bcaf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-define <vscale x 1 x i32> @intrinsic_vqdotsu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdota4u_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
-; CHECK-NEXT: vqdotsu.vv v8, v9, v10
+; CHECK-NEXT: vdota4u.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
@@ -20,14 +20,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotsu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdota4u_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; CHECK-NEXT: vqdotsu.vv v8, v9, v10
+; CHECK-NEXT: vdota4u.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
@@ -36,14 +36,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotsu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdota4u_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
-; CHECK-NEXT: vqdotsu.vv v8, v10, v12
+; CHECK-NEXT: vdota4u.vv v8, v10, v12
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
@@ -52,14 +52,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotsu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdota4u_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vqdotsu.vv v8, v12, v16
+; CHECK-NEXT: vdota4u.vv v8, v12, v16
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
@@ -68,15 +68,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotsu_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdota4u_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdotsu.vv v8, v16, v24
+; CHECK-NEXT: vdota4u.vv v8, v16, v24
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
@@ -85,14 +85,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vqdotsu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdota4u_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vqdotsu.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdota4u.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
@@ -102,14 +102,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotsu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdota4u_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vqdotsu.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdota4u.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
@@ -119,14 +119,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotsu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdota4u_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vqdotsu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vdota4u.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
@@ -136,14 +136,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotsu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdota4u_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vqdotsu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vdota4u.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
@@ -153,15 +153,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotsu_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdota4u_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdotsu.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vdota4u.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
@@ -171,14 +171,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vqdotsu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdota4u_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vqdotsu.vx v8, v9, a0
+; CHECK-NEXT: vdota4u.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
i32 %2,
@@ -187,14 +187,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotsu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdota4u_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vqdotsu.vx v8, v9, a0
+; CHECK-NEXT: vdota4u.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
i32 %2,
@@ -203,14 +203,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotsu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdota4u_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vqdotsu.vx v8, v10, a0
+; CHECK-NEXT: vdota4u.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
i32 %2,
@@ -219,14 +219,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotsu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdota4u_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vqdotsu.vx v8, v12, a0
+; CHECK-NEXT: vdota4u.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
i32 %2,
@@ -235,14 +235,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotsu_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdota4u_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdotsu.vx v8, v16, a0
+; CHECK-NEXT: vdota4u.vx v8, v16, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
i32 %2,
@@ -251,14 +251,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vqdotsu_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdota4u_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vqdotsu.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdota4u.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 4 x i8> %1,
i32 %2,
@@ -268,14 +268,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vqdotsu_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdota4u_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vqdotsu.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdota4u.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
i32 %2,
@@ -285,14 +285,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vqdotsu_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdota4u_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vqdotsu.vx v8, v10, a0, v0.t
+; CHECK-NEXT: vdota4u.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 16 x i8> %1,
i32 %2,
@@ -302,14 +302,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vqdotsu_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdota4u_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vqdotsu.vx v8, v12, a0, v0.t
+; CHECK-NEXT: vdota4u.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 32 x i8> %1,
i32 %2,
@@ -319,14 +319,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vqdotsu_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdota4u_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdotsu.vx v8, v16, a0, v0.t
+; CHECK-NEXT: vdota4u.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 64 x i8> %1,
i32 %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdota4us.ll b/llvm/test/CodeGen/RISCV/rvv/vdota4us.ll
new file mode 100644
index 0000000000000..4dd4095e538dd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vdota4us.ll
@@ -0,0 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvdot4a8i \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i32> @intrinsic_vdota4us_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_vx_nxv1i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT: vdota4us.vx v8, v9, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 4 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vdota4us_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_vx_nxv2i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT: vdota4us.vx v8, v9, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.i32(
+ <vscale x 2 x i32> %0,
+ <vscale x 8 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vdota4us_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_vx_nxv4i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT: vdota4us.vx v8, v10, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.i32(
+ <vscale x 4 x i32> %0,
+ <vscale x 16 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vdota4us_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_vx_nxv8i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT: vdota4us.vx v8, v12, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.i32(
+ <vscale x 8 x i32> %0,
+ <vscale x 32 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vdota4us_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_vx_nxv16i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT: vdota4us.vx v8, v16, a0
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.i32(
+ <vscale x 16 x i32> %0,
+ <vscale x 64 x i8> %1,
+ i32 %2,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vdota4us_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv1i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT: vdota4us.vx v8, v9, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 4 x i8> %1,
+ i32 %2,
+ <vscale x 1 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vdota4us_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv2i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT: vdota4us.vx v8, v9, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32(
+ <vscale x 2 x i32> %0,
+ <vscale x 8 x i8> %1,
+ i32 %2,
+ <vscale x 2 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vdota4us_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv4i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT: vdota4us.vx v8, v10, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32(
+ <vscale x 4 x i32> %0,
+ <vscale x 16 x i8> %1,
+ i32 %2,
+ <vscale x 4 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vdota4us_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv8i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT: vdota4us.vx v8, v12, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32(
+ <vscale x 8 x i32> %0,
+ <vscale x 32 x i8> %1,
+ i32 %2,
+ <vscale x 8 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vdota4us_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv16i32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
+; CHECK-NEXT: vdota4us.vx v8, v16, a0, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32(
+ <vscale x 16 x i32> %0,
+ <vscale x 64 x i8> %1,
+ i32 %2,
+ <vscale x 16 x i1> %m,
+ iXLen %3, iXLen 0)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vqdot.ll b/llvm/test/CodeGen/RISCV/rvv/vqdot.ll
deleted file mode 100644
index 6014c8aceb599..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vqdot.ll
+++ /dev/null
@@ -1,337 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \
-; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \
-; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-
-define <vscale x 1 x i32> @intrinsic_vqdot_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vv_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
-; CHECK-NEXT: vqdot.vv v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vqdot_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vv_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; CHECK-NEXT: vqdot.vv v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vqdot_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vv_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
-; CHECK-NEXT: vqdot.vv v8, v10, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vqdot_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vv_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vqdot.vv v8, v12, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vqdot_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vv_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdot.vv v8, v16, v24
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vqdot_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vv_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vqdot.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 1 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vqdot_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vv_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vqdot.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vqdot_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vv_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vqdot.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 4 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vqdot_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vv_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vqdot.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 8 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vqdot_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vv_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdot.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 16 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vqdot_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vx_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vqdot.vx v8, v9, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdot.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 4 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vqdot_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vx_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vqdot.vx v8, v9, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdot.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vqdot_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vx_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vqdot.vx v8, v10, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdot.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 16 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vqdot_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vx_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vqdot.vx v8, v12, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdot.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 32 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vqdot_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_vx_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdot.vx v8, v16, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdot.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 64 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vqdot_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vx_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vqdot.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdot.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 4 x i8> %1,
- i32 %2,
- <vscale x 1 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vqdot_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vx_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vqdot.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdot.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i8> %1,
- i32 %2,
- <vscale x 2 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vqdot_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vx_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vqdot.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdot.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 16 x i8> %1,
- i32 %2,
- <vscale x 4 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vqdot_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vx_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vqdot.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdot.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 32 x i8> %1,
- i32 %2,
- <vscale x 8 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vqdot_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdot_mask_vx_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdot.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdot.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 64 x i8> %1,
- i32 %2,
- <vscale x 16 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 16 x i32> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vqdotus.ll b/llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
deleted file mode 100644
index e4df6e146eef2..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
+++ /dev/null
@@ -1,170 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \
-; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \
-; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-
-define <vscale x 1 x i32> @intrinsic_vqdotus_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_vx_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vqdotus.vx v8, v9, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 4 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vqdotus_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_vx_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vqdotus.vx v8, v9, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vqdotus_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_vx_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vqdotus.vx v8, v10, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 16 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vqdotus_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_vx_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vqdotus.vx v8, v12, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 32 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vqdotus_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_vx_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vqdotus.vx v8, v16, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 64 x i8> %1,
- i32 %2,
- iXLen %3, iXLen 0)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vqdotus_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vqdotus.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 4 x i8> %1,
- i32 %2,
- <vscale x 1 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vqdotus_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vqdotus.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i8> %1,
- i32 %2,
- <vscale x 2 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vqdotus_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vqdotus.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 16 x i8> %1,
- i32 %2,
- <vscale x 4 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vqdotus_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vqdotus.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 32 x i8> %1,
- i32 %2,
- <vscale x 8 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vqdotus_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vqdotus.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 64 x i8> %1,
- i32 %2,
- <vscale x 16 x i1> %m,
- iXLen %3, iXLen 0)
-
- ret <vscale x 16 x i32> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
similarity index 91%
rename from llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
index d6384a6913efe..7a54cee626e4b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NODOT
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NODOT
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT64
-define i32 @vqdot_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vqdot_vv:
+define i32 @vdota4_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdota4_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -17,11 +17,11 @@ define i32 @vqdot_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv:
+; DOT-LABEL: vdota4_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdot.vv v12, v8, v10
+; DOT-NEXT: vdota4.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -34,8 +34,8 @@ entry:
ret i32 %res
}
-define i32 @vqdot_vx_constant(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: vqdot_vx_constant:
+define i32 @vdota4_vx_constant(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vdota4_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
@@ -53,8 +53,8 @@ entry:
ret i32 %res
}
-define i32 @vqdot_vx_constant_swapped(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: vqdot_vx_constant_swapped:
+define i32 @vdota4_vx_constant_swapped(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vdota4_vx_constant_swapped:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
@@ -72,8 +72,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotu_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vqdotu_vv:
+define i32 @vdota4u_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdota4u_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; NODOT-NEXT: vwmulu.vv v12, v8, v10
@@ -85,11 +85,11 @@ define i32 @vqdotu_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv:
+; DOT-LABEL: vdota4u_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdotu.vv v12, v8, v10
+; DOT-NEXT: vdota4u.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -102,8 +102,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotu_vx_constant(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: vqdotu_vx_constant:
+define i32 @vdota4u_vx_constant(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vdota4u_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
@@ -121,8 +121,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotsu_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv:
+define i32 @vdota4su_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -134,11 +134,11 @@ define i32 @vqdotsu_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv:
+; DOT-LABEL: vdota4su_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdotsu.vv v12, v8, v10
+; DOT-NEXT: vdota4su.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -151,8 +151,8 @@ entry:
ret i32 %res
}
-define i32 @vqdotsu_vv_swapped(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vqdotsu_vv_swapped:
+define i32 @vdota4su_vv_swapped(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdota4su_vv_swapped:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -164,11 +164,11 @@ define i32 @vqdotsu_vv_swapped(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_swapped:
+; DOT-LABEL: vdota4su_vv_swapped:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdotsu.vv v12, v8, v10
+; DOT-NEXT: vdota4su.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -236,7 +236,7 @@ define i32 @reduce_of_sext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdot.vv v12, v8, v10
+; DOT-NEXT: vdota4.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -263,7 +263,7 @@ define i32 @reduce_of_zext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdotu.vv v12, v8, v10
+; DOT-NEXT: vdota4u.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -274,8 +274,8 @@ entry:
ret i32 %res
}
-define i32 @vqdot_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
-; NODOT-LABEL: vqdot_vv_accum:
+define i32 @vdota4_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
+; NODOT-LABEL: vdota4_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -287,11 +287,11 @@ define i32 @vqdot_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_accum:
+; DOT-LABEL: vdota4_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.s.x v12, zero
-; DOT-NEXT: vqdot.vv v16, v8, v10
+; DOT-NEXT: vdota4.vv v16, v8, v10
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vredsum.vs v8, v16, v12
; DOT-NEXT: vmv.x.s a0, v8
@@ -305,8 +305,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdotu_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
-; NODOT-LABEL: vqdotu_vv_accum:
+define i32 @vdota4u_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
+; NODOT-LABEL: vdota4u_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; NODOT-NEXT: vwmulu.vv v12, v8, v10
@@ -318,11 +318,11 @@ define i32 @vqdotu_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscal
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv_accum:
+; DOT-LABEL: vdota4u_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.s.x v12, zero
-; DOT-NEXT: vqdotu.vv v16, v8, v10
+; DOT-NEXT: vdota4u.vv v16, v8, v10
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vredsum.vs v8, v16, v12
; DOT-NEXT: vmv.x.s a0, v8
@@ -336,8 +336,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdotsu_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
-; NODOT-LABEL: vqdotsu_vv_accum:
+define i32 @vdota4su_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
+; NODOT-LABEL: vdota4su_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -349,11 +349,11 @@ define i32 @vqdotsu_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vsca
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_accum:
+; DOT-LABEL: vdota4su_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.s.x v12, zero
-; DOT-NEXT: vqdotsu.vv v16, v8, v10
+; DOT-NEXT: vdota4su.vv v16, v8, v10
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vredsum.vs v8, v16, v12
; DOT-NEXT: vmv.x.s a0, v8
@@ -367,8 +367,8 @@ entry:
ret i32 %sum
}
-define i32 @vqdot_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vqdot_vv_scalar_add:
+define i32 @vdota4_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdota4_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -380,11 +380,11 @@ define i32 @vqdot_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i3
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_scalar_add:
+; DOT-LABEL: vdota4_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdot.vv v12, v8, v10
+; DOT-NEXT: vdota4.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -398,8 +398,8 @@ entry:
ret i32 %add
}
-define i32 @vqdotu_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vqdotu_vv_scalar_add:
+define i32 @vdota4u_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdota4u_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; NODOT-NEXT: vwmulu.vv v12, v8, v10
@@ -411,11 +411,11 @@ define i32 @vqdotu_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotu_vv_scalar_add:
+; DOT-LABEL: vdota4u_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdotu.vv v12, v8, v10
+; DOT-NEXT: vdota4u.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -429,8 +429,8 @@ entry:
ret i32 %add
}
-define i32 @vqdotsu_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vqdotsu_vv_scalar_add:
+define i32 @vdota4su_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdota4su_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -442,11 +442,11 @@ define i32 @vqdotsu_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b,
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdotsu_vv_scalar_add:
+; DOT-LABEL: vdota4su_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdotsu.vv v12, v8, v10
+; DOT-NEXT: vdota4su.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -460,8 +460,8 @@ entry:
ret i32 %add
}
-define i32 @vqdot_vv_split(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) {
-; NODOT-LABEL: vqdot_vv_split:
+define i32 @vdota4_vv_split(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) {
+; NODOT-LABEL: vdota4_vv_split:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -476,12 +476,12 @@ define i32 @vqdot_vv_split(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vqdot_vv_split:
+; DOT-LABEL: vdota4_vv_split:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v16, 0
-; DOT-NEXT: vqdot.vv v16, v8, v10
-; DOT-NEXT: vqdot.vv v16, v12, v14
+; DOT-NEXT: vdota4.vv v16, v8, v10
+; DOT-NEXT: vdota4.vv v16, v12, v14
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v16, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -521,7 +521,7 @@ define <vscale x 1 x i32> @partial_reduce_nf2(<vscale x 4 x i8> %a, <vscale x 4
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -549,7 +549,7 @@ define <vscale x 2 x i32> @partial_reduce_m1(<vscale x 8 x i8> %a, <vscale x 8 x
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v9
+; DOT-NEXT: vdota4.vv v10, v8, v9
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -577,7 +577,7 @@ define <vscale x 4 x i32> @partial_reduce_m2(<vscale x 16 x i8> %a, <vscale x 16
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vqdot.vv v12, v8, v10
+; DOT-NEXT: vdota4.vv v12, v8, v10
; DOT-NEXT: vmv.v.v v8, v12
; DOT-NEXT: ret
entry:
@@ -608,7 +608,7 @@ define <vscale x 8 x i32> @partial_reduce_m4(<vscale x 32 x i8> %a, <vscale x 32
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; DOT-NEXT: vmv.v.i v16, 0
-; DOT-NEXT: vqdot.vv v16, v8, v12
+; DOT-NEXT: vdota4.vv v16, v8, v12
; DOT-NEXT: vmv.v.v v8, v16
; DOT-NEXT: ret
entry:
@@ -657,7 +657,7 @@ define <vscale x 16 x i32> @partial_reduce_m8(<vscale x 64 x i8> %a, <vscale x 6
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vmv.v.i v24, 0
-; DOT-NEXT: vqdot.vv v24, v8, v16
+; DOT-NEXT: vdota4.vv v24, v8, v16
; DOT-NEXT: vmv.v.v v8, v24
; DOT-NEXT: ret
entry:
@@ -803,7 +803,7 @@ define <vscale x 32 x i32> @partial_reduce_m16(<vscale x 128 x i8> %a, <vscale x
; DOT-NEXT: add a0, sp, a0
; DOT-NEXT: addi a0, a0, 16
; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vqdot.vv v0, v16, v8
+; DOT-NEXT: vdota4.vv v0, v16, v8
; DOT-NEXT: csrr a0, vlenb
; DOT-NEXT: slli a0, a0, 4
; DOT-NEXT: add a0, sp, a0
@@ -811,7 +811,7 @@ define <vscale x 32 x i32> @partial_reduce_m16(<vscale x 128 x i8> %a, <vscale x
; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; DOT-NEXT: addi a0, sp, 16
; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vqdot.vv v24, v8, v16
+; DOT-NEXT: vdota4.vv v24, v8, v16
; DOT-NEXT: vmv.v.v v8, v0
; DOT-NEXT: vmv.v.v v16, v24
; DOT-NEXT: csrr a0, vlenb
@@ -849,7 +849,7 @@ define <vscale x 4 x i32> @partial_reduce_accum(<vscale x 16 x i8> %a, <vscale x
; DOT-LABEL: partial_reduce_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; DOT-NEXT: vqdot.vv v12, v8, v10
+; DOT-NEXT: vdota4.vv v12, v8, v10
; DOT-NEXT: vmv.v.v v8, v12
; DOT-NEXT: ret
entry:
@@ -876,8 +876,8 @@ entry:
ret <vscale x 16 x i32> %res
}
-define <vscale x 1 x i32> @partial_reduce_vqdotu(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
-; NODOT-LABEL: partial_reduce_vqdotu:
+define <vscale x 1 x i32> @partial_reduce_vdota4u(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
+; NODOT-LABEL: partial_reduce_vdota4u:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -894,11 +894,11 @@ define <vscale x 1 x i32> @partial_reduce_vqdotu(<vscale x 4 x i8> %a, <vscale x
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: partial_reduce_vqdotu:
+; DOT-LABEL: partial_reduce_vdota4u:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotu.vv v10, v8, v9
+; DOT-NEXT: vdota4u.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -909,8 +909,8 @@ entry:
ret <vscale x 1 x i32> %res
}
-define <vscale x 1 x i32> @partial_reduce_vqdotsu(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
-; NODOT-LABEL: partial_reduce_vqdotsu:
+define <vscale x 1 x i32> @partial_reduce_vdota4su(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
+; NODOT-LABEL: partial_reduce_vdota4su:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -927,11 +927,11 @@ define <vscale x 1 x i32> @partial_reduce_vqdotsu(<vscale x 4 x i8> %a, <vscale
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: partial_reduce_vqdotsu:
+; DOT-LABEL: partial_reduce_vdota4su:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotsu.vv v10, v8, v9
+; DOT-NEXT: vdota4su.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -960,7 +960,7 @@ define <vscale x 4 x i32> @partial_of_sext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v12, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdot.vv v10, v8, v12
+; DOT-NEXT: vdota4.vv v10, v8, v12
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -986,7 +986,7 @@ define <vscale x 4 x i32> @partial_of_zext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v12, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vqdotu.vv v10, v8, v12
+; DOT-NEXT: vdota4u.vv v10, v8, v12
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -1018,7 +1018,7 @@ define <vscale x 2 x i32> @partial_reduce_select(<vscale x 8 x i8> %a, <vscale x
; DOT-NEXT: vmerge.vvm v10, v10, v9, v0
; DOT-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
-; DOT-NEXT: vqdot.vv v9, v8, v10
+; DOT-NEXT: vdota4.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
diff --git a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
index 547ecd2e74f1d..36d2c75ce527c 100644
--- a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
+++ b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
@@ -158,9 +158,9 @@ define dso_local noundef signext i32 @main() #2 !dbg !28 {
ret i32 %6, !dbg !36
}
-attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
-attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
-attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3, !4, !5, !6, !8, !9}
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 61b7c0b12480c..c0ff3ef740ca4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -177,8 +177,8 @@
.attribute arch, "rv32i_zvkt1p0"
# CHECK: attribute 5, "rv32i2p1_zvkt1p0"
-.attribute arch, "rv32i_zvqdotq0p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0"
+.attribute arch, "rv32i_zvdot4a8i0p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p1_zbs1p0"
diff --git a/llvm/test/MC/RISCV/rvv/zvqdotq-invalid.s b/llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
similarity index 50%
rename from llvm/test/MC/RISCV/rvv/zvqdotq-invalid.s
rename to llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
index c0f36798d9cfe..bca90029286e2 100644
--- a/llvm/test/MC/RISCV/rvv/zvqdotq-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
@@ -1,10 +1,10 @@
-# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zvqdotq %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zvdot4a8i %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-vqdot.vv v0, v2, v4, v0.t
+vdota4.vv v0, v2, v4, v0.t
# CHECK-ERROR: the destination vector register group cannot overlap the mask register
-# CHECK-ERROR-LABEL: vqdot.vv v0, v2, v4, v0.t
+# CHECK-ERROR-LABEL: vdota4.vv v0, v2, v4, v0.t
-vqdot.vx v0, v2, a0, v0.t
+vdota4.vx v0, v2, a0, v0.t
# CHECK-ERROR: the destination vector register group cannot overlap the mask register
-# CHECK-ERROR-LABEL: vqdot.vx v0, v2, a0, v0.t
+# CHECK-ERROR-LABEL: vdota4.vx v0, v2, a0, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvdot4a8i.s b/llvm/test/MC/RISCV/rvv/zvdot4a8i.s
new file mode 100644
index 0000000000000..25cec6db4735e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvdot4a8i.s
@@ -0,0 +1,93 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvdot4a8i %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvdot4a8i %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zvdot4a8i - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvdot4a8i %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vdota4.vv v8, v4, v20, v0.t
+# CHECK-INST: vdota4.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: b04a2457 <unknown>
+
+vdota4.vv v8, v4, v20
+# CHECK-INST: vdota4.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: b24a2457 <unknown>
+
+vdota4u.vv v8, v4, v20, v0.t
+# CHECK-INST: vdota4u.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: a04a2457 <unknown>
+
+vdota4u.vv v8, v4, v20
+# CHECK-INST: vdota4u.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: a24a2457 <unknown>
+
+vdota4su.vv v8, v4, v20, v0.t
+# CHECK-INST: vdota4su.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: a84a2457 <unknown>
+
+vdota4su.vv v8, v4, v20
+# CHECK-INST: vdota4su.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: aa4a2457 <unknown>
+
+vdota4.vx v8, v4, s4, v0.t
+# CHECK-INST: vdota4.vx v8, v4, s4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: b04a6457 <unknown>
+
+vdota4.vx v8, v4, s4
+# CHECK-INST: vdota4.vx v8, v4, s4
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: b24a6457 <unknown>
+
+vdota4u.vx v8, v4, s4, v0.t
+# CHECK-INST: vdota4u.vx v8, v4, s4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: a04a6457 <unknown>
+
+vdota4u.vx v8, v4, s4
+# CHECK-INST: vdota4u.vx v8, v4, s4
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: a24a6457 <unknown>
+
+vdota4su.vx v8, v4, s4, v0.t
+# CHECK-INST: vdota4su.vx v8, v4, s4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: a84a6457 <unknown>
+
+vdota4su.vx v8, v4, s4
+# CHECK-INST: vdota4su.vx v8, v4, s4
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: aa4a6457 <unknown>
+
+vdota4us.vx v8, v4, s4, v0.t
+# CHECK-INST: vdota4us.vx v8, v4, s4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: b84a6457 <unknown>
+
+vdota4us.vx v8, v4, s4
+# CHECK-INST: vdota4us.vx v8, v4, s4
+# CHECK-ENCODING: [0x57,0x64,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector quad widening 4D Dot Product){{$}}
+# CHECK-UNKNOWN: ba4a6457 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvqdotq.s b/llvm/test/MC/RISCV/rvv/zvqdotq.s
deleted file mode 100644
index 603cbdfabae96..0000000000000
--- a/llvm/test/MC/RISCV/rvv/zvqdotq.s
+++ /dev/null
@@ -1,93 +0,0 @@
-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvqdotq %s \
-# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqdotq %s \
-# RUN: | llvm-objdump -d --mattr=+experimental-zvqdotq - \
-# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqdotq %s \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-
-vqdot.vv v8, v4, v20, v0.t
-# CHECK-INST: vqdot.vv v8, v4, v20, v0.t
-# CHECK-ENCODING: [0x57,0x24,0x4a,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: b04a2457 <unknown>
-
-vqdot.vv v8, v4, v20
-# CHECK-INST: vqdot.vv v8, v4, v20
-# CHECK-ENCODING: [0x57,0x24,0x4a,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: b24a2457 <unknown>
-
-vqdotu.vv v8, v4, v20, v0.t
-# CHECK-INST: vqdotu.vv v8, v4, v20, v0.t
-# CHECK-ENCODING: [0x57,0x24,0x4a,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: a04a2457 <unknown>
-
-vqdotu.vv v8, v4, v20
-# CHECK-INST: vqdotu.vv v8, v4, v20
-# CHECK-ENCODING: [0x57,0x24,0x4a,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: a24a2457 <unknown>
-
-vqdotsu.vv v8, v4, v20, v0.t
-# CHECK-INST: vqdotsu.vv v8, v4, v20, v0.t
-# CHECK-ENCODING: [0x57,0x24,0x4a,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: a84a2457 <unknown>
-
-vqdotsu.vv v8, v4, v20
-# CHECK-INST: vqdotsu.vv v8, v4, v20
-# CHECK-ENCODING: [0x57,0x24,0x4a,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: aa4a2457 <unknown>
-
-vqdot.vx v8, v4, s4, v0.t
-# CHECK-INST: vqdot.vx v8, v4, s4, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: b04a6457 <unknown>
-
-vqdot.vx v8, v4, s4
-# CHECK-INST: vqdot.vx v8, v4, s4
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: b24a6457 <unknown>
-
-vqdotu.vx v8, v4, s4, v0.t
-# CHECK-INST: vqdotu.vx v8, v4, s4, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: a04a6457 <unknown>
-
-vqdotu.vx v8, v4, s4
-# CHECK-INST: vqdotu.vx v8, v4, s4
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: a24a6457 <unknown>
-
-vqdotsu.vx v8, v4, s4, v0.t
-# CHECK-INST: vqdotsu.vx v8, v4, s4, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: a84a6457 <unknown>
-
-vqdotsu.vx v8, v4, s4
-# CHECK-INST: vqdotsu.vx v8, v4, s4
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: aa4a6457 <unknown>
-
-vqdotus.vx v8, v4, s4, v0.t
-# CHECK-INST: vqdotus.vx v8, v4, s4, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: b84a6457 <unknown>
-
-vqdotus.vx v8, v4, s4
-# CHECK-INST: vqdotus.vx v8, v4, s4
-# CHECK-ENCODING: [0x57,0x64,0x4a,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
-# CHECK-UNKNOWN: ba4a6457 <unknown>
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll b/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
index d41f5e4d92e58..9bc84628a41b4 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph:" --version 4
; RUN: opt -passes=loop-vectorize -mattr=+v -prefer-predicate-over-epilogue=scalar-epilogue -S < %s | FileCheck %s --check-prefixes=CHECK,V
-; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvqdotq -prefer-predicate-over-epilogue=scalar-epilogue -S < %s | FileCheck %s --check-prefixes=CHECK,ZVQDOTQ
+; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -prefer-predicate-over-epilogue=scalar-epilogue -S < %s | FileCheck %s --check-prefixes=CHECK,ZVDOT4A8I
; RUN: opt -passes=loop-vectorize -mattr=+v -scalable-vectorization=off -prefer-predicate-over-epilogue=scalar-epilogue -S < %s | FileCheck %s --check-prefixes=FIXED,FIXED-V
-; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvqdotq -scalable-vectorization=off -prefer-predicate-over-epilogue=scalar-epilogue -S < %s | FileCheck %s --check-prefixes=FIXED,FIXED-ZVQDOTQ
-; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvqdotq -S < %s | FileCheck %s --check-prefixes=CHECK,TAILFOLD
+; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -scalable-vectorization=off -prefer-predicate-over-epilogue=scalar-epilogue -S < %s | FileCheck %s --check-prefixes=FIXED,FIXED-ZVDOT4A8I
+; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -S < %s | FileCheck %s --check-prefixes=CHECK,TAILFOLD
; TODO: Remove -prefer-predicate-over-epilogue=scalar-epilogue when partial reductions with EVL tail folding is supported.
target triple = "riscv64-none-unknown-elf"
-define i32 @vqdot(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vqdot(
+define i32 @vdota4(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdota4(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -43,40 +43,40 @@ define i32 @vqdot(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVQDOTQ-LABEL: define i32 @vqdot(
-; ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
-; ZVQDOTQ-NEXT: entry:
-; ZVQDOTQ-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
-; ZVQDOTQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
-; ZVQDOTQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; ZVQDOTQ: vector.ph:
-; ZVQDOTQ-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
-; ZVQDOTQ-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
-; ZVQDOTQ-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
-; ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; ZVQDOTQ: vector.body:
-; ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
-; ZVQDOTQ-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
-; ZVQDOTQ-NEXT: [[TMP11:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP8:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
-; ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
-; ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
-; ZVQDOTQ-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; ZVQDOTQ: middle.block:
-; ZVQDOTQ-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
-; ZVQDOTQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
-; ZVQDOTQ: scalar.ph:
+; ZVDOT4A8I-LABEL: define i32 @vdota4(
+; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; ZVDOT4A8I-NEXT: entry:
+; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; ZVDOT4A8I-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; ZVDOT4A8I-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; ZVDOT4A8I: vector.ph:
+; ZVDOT4A8I-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
+; ZVDOT4A8I-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; ZVDOT4A8I-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; ZVDOT4A8I: vector.body:
+; ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
+; ZVDOT4A8I-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
+; ZVDOT4A8I-NEXT: [[TMP11:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP8:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
+; ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
+; ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; ZVDOT4A8I-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; ZVDOT4A8I: middle.block:
+; ZVDOT4A8I-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
+; ZVDOT4A8I-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
+; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vqdot(
+; FIXED-V-LABEL: define i32 @vdota4(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -112,43 +112,43 @@ define i32 @vqdot(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVQDOTQ-LABEL: define i32 @vqdot(
-; FIXED-ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
-; FIXED-ZVQDOTQ-NEXT: entry:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_PH:%.*]]
-; FIXED-ZVQDOTQ: vector.ph:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; FIXED-ZVQDOTQ: vector.body:
-; FIXED-ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP8:%.*]] = sext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP3:%.*]] = sext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP10:%.*]] = mul <8 x i32> [[TMP8]], [[TMP3]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP10]])
-; FIXED-ZVQDOTQ-NEXT: [[TMP9:%.*]] = sext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP12:%.*]] = sext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP12]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP11]])
-; FIXED-ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
-; FIXED-ZVQDOTQ-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; FIXED-ZVQDOTQ-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; FIXED-ZVQDOTQ: middle.block:
-; FIXED-ZVQDOTQ-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
-; FIXED-ZVQDOTQ-NEXT: br label [[FOR_EXIT:%.*]]
-; FIXED-ZVQDOTQ: for.exit:
-; FIXED-ZVQDOTQ-NEXT: ret i32 [[TMP13]]
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4(
+; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; FIXED-ZVDOT4A8I-NEXT: entry:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
+; FIXED-ZVDOT4A8I: vector.ph:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; FIXED-ZVDOT4A8I: vector.body:
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP8:%.*]] = sext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP3:%.*]] = sext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP10:%.*]] = mul <8 x i32> [[TMP8]], [[TMP3]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP10]])
+; FIXED-ZVDOT4A8I-NEXT: [[TMP9:%.*]] = sext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP12:%.*]] = sext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP12]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP11]])
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; FIXED-ZVDOT4A8I-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; FIXED-ZVDOT4A8I-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; FIXED-ZVDOT4A8I: middle.block:
+; FIXED-ZVDOT4A8I-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
+; FIXED-ZVDOT4A8I-NEXT: br label [[FOR_EXIT:%.*]]
+; FIXED-ZVDOT4A8I: for.exit:
+; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vqdot(
+; TAILFOLD-LABEL: define i32 @vdota4(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
@@ -202,8 +202,8 @@ for.exit: ; preds = %for.body
}
-define i32 @vqdotu(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vqdotu(
+define i32 @vdota4u(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdota4u(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -236,40 +236,40 @@ define i32 @vqdotu(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVQDOTQ-LABEL: define i32 @vqdotu(
-; ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; ZVQDOTQ-NEXT: entry:
-; ZVQDOTQ-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
-; ZVQDOTQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
-; ZVQDOTQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; ZVQDOTQ: vector.ph:
-; ZVQDOTQ-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
-; ZVQDOTQ-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
-; ZVQDOTQ-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
-; ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; ZVQDOTQ: vector.body:
-; ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
-; ZVQDOTQ-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
-; ZVQDOTQ-NEXT: [[TMP11:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP8:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
-; ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
-; ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
-; ZVQDOTQ-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
-; ZVQDOTQ: middle.block:
-; ZVQDOTQ-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
-; ZVQDOTQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
-; ZVQDOTQ: scalar.ph:
+; ZVDOT4A8I-LABEL: define i32 @vdota4u(
+; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; ZVDOT4A8I-NEXT: entry:
+; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; ZVDOT4A8I-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; ZVDOT4A8I-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; ZVDOT4A8I: vector.ph:
+; ZVDOT4A8I-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
+; ZVDOT4A8I-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; ZVDOT4A8I-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; ZVDOT4A8I: vector.body:
+; ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
+; ZVDOT4A8I-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
+; ZVDOT4A8I-NEXT: [[TMP11:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP8:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
+; ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
+; ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; ZVDOT4A8I-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; ZVDOT4A8I: middle.block:
+; ZVDOT4A8I-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
+; ZVDOT4A8I-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
+; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vqdotu(
+; FIXED-V-LABEL: define i32 @vdota4u(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -305,43 +305,43 @@ define i32 @vqdotu(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVQDOTQ-LABEL: define i32 @vqdotu(
-; FIXED-ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; FIXED-ZVQDOTQ-NEXT: entry:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_PH:%.*]]
-; FIXED-ZVQDOTQ: vector.ph:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; FIXED-ZVQDOTQ: vector.body:
-; FIXED-ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP8:%.*]] = zext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP10:%.*]] = mul <8 x i32> [[TMP8]], [[TMP3]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP10]])
-; FIXED-ZVQDOTQ-NEXT: [[TMP9:%.*]] = zext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP12:%.*]] = zext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP12]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP11]])
-; FIXED-ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
-; FIXED-ZVQDOTQ-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; FIXED-ZVQDOTQ-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
-; FIXED-ZVQDOTQ: middle.block:
-; FIXED-ZVQDOTQ-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
-; FIXED-ZVQDOTQ-NEXT: br label [[FOR_EXIT:%.*]]
-; FIXED-ZVQDOTQ: for.exit:
-; FIXED-ZVQDOTQ-NEXT: ret i32 [[TMP13]]
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4u(
+; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; FIXED-ZVDOT4A8I-NEXT: entry:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
+; FIXED-ZVDOT4A8I: vector.ph:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; FIXED-ZVDOT4A8I: vector.body:
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP8:%.*]] = zext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP10:%.*]] = mul <8 x i32> [[TMP8]], [[TMP3]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP10]])
+; FIXED-ZVDOT4A8I-NEXT: [[TMP9:%.*]] = zext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP12:%.*]] = zext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP12]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP11]])
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; FIXED-ZVDOT4A8I-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; FIXED-ZVDOT4A8I-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; FIXED-ZVDOT4A8I: middle.block:
+; FIXED-ZVDOT4A8I-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
+; FIXED-ZVDOT4A8I-NEXT: br label [[FOR_EXIT:%.*]]
+; FIXED-ZVDOT4A8I: for.exit:
+; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vqdotu(
+; TAILFOLD-LABEL: define i32 @vdota4u(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
@@ -395,8 +395,8 @@ for.exit: ; preds = %for.body
}
-define i32 @vqdotsu(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vqdotsu(
+define i32 @vdota4su(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdota4su(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -429,40 +429,40 @@ define i32 @vqdotsu(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVQDOTQ-LABEL: define i32 @vqdotsu(
-; ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; ZVQDOTQ-NEXT: entry:
-; ZVQDOTQ-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
-; ZVQDOTQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
-; ZVQDOTQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; ZVQDOTQ: vector.ph:
-; ZVQDOTQ-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
-; ZVQDOTQ-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
-; ZVQDOTQ-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
-; ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; ZVQDOTQ: vector.body:
-; ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
-; ZVQDOTQ-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
-; ZVQDOTQ-NEXT: [[TMP11:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP8:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
-; ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
-; ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
-; ZVQDOTQ-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
-; ZVQDOTQ: middle.block:
-; ZVQDOTQ-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
-; ZVQDOTQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
-; ZVQDOTQ: scalar.ph:
+; ZVDOT4A8I-LABEL: define i32 @vdota4su(
+; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; ZVDOT4A8I-NEXT: entry:
+; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; ZVDOT4A8I-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; ZVDOT4A8I-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; ZVDOT4A8I: vector.ph:
+; ZVDOT4A8I-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
+; ZVDOT4A8I-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; ZVDOT4A8I-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; ZVDOT4A8I: vector.body:
+; ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
+; ZVDOT4A8I-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
+; ZVDOT4A8I-NEXT: [[TMP11:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP8:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
+; ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
+; ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; ZVDOT4A8I-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; ZVDOT4A8I: middle.block:
+; ZVDOT4A8I-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
+; ZVDOT4A8I-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
+; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vqdotsu(
+; FIXED-V-LABEL: define i32 @vdota4su(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -498,43 +498,43 @@ define i32 @vqdotsu(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVQDOTQ-LABEL: define i32 @vqdotsu(
-; FIXED-ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; FIXED-ZVQDOTQ-NEXT: entry:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_PH:%.*]]
-; FIXED-ZVQDOTQ: vector.ph:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; FIXED-ZVQDOTQ: vector.body:
-; FIXED-ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP9:%.*]] = sext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP4:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP4]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP11]])
-; FIXED-ZVQDOTQ-NEXT: [[TMP10:%.*]] = sext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP8:%.*]] = zext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP10]], [[TMP8]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP14]])
-; FIXED-ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
-; FIXED-ZVQDOTQ-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; FIXED-ZVQDOTQ-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
-; FIXED-ZVQDOTQ: middle.block:
-; FIXED-ZVQDOTQ-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
-; FIXED-ZVQDOTQ-NEXT: br label [[FOR_EXIT:%.*]]
-; FIXED-ZVQDOTQ: for.exit:
-; FIXED-ZVQDOTQ-NEXT: ret i32 [[TMP13]]
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4su(
+; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; FIXED-ZVDOT4A8I-NEXT: entry:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
+; FIXED-ZVDOT4A8I: vector.ph:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; FIXED-ZVDOT4A8I: vector.body:
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP9:%.*]] = sext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP4:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP4]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP11]])
+; FIXED-ZVDOT4A8I-NEXT: [[TMP10:%.*]] = sext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP8:%.*]] = zext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP10]], [[TMP8]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP14]])
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; FIXED-ZVDOT4A8I-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; FIXED-ZVDOT4A8I-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; FIXED-ZVDOT4A8I: middle.block:
+; FIXED-ZVDOT4A8I-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
+; FIXED-ZVDOT4A8I-NEXT: br label [[FOR_EXIT:%.*]]
+; FIXED-ZVDOT4A8I: for.exit:
+; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vqdotsu(
+; TAILFOLD-LABEL: define i32 @vdota4su(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
@@ -587,8 +587,8 @@ for.exit: ; preds = %for.body
ret i32 %add
}
-define i32 @vqdotsu2(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vqdotsu2(
+define i32 @vdota4su2(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdota4su2(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -621,40 +621,40 @@ define i32 @vqdotsu2(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVQDOTQ-LABEL: define i32 @vqdotsu2(
-; ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; ZVQDOTQ-NEXT: entry:
-; ZVQDOTQ-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
-; ZVQDOTQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
-; ZVQDOTQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; ZVQDOTQ: vector.ph:
-; ZVQDOTQ-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; ZVQDOTQ-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
-; ZVQDOTQ-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
-; ZVQDOTQ-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
-; ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; ZVQDOTQ: vector.body:
-; ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; ZVQDOTQ-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
-; ZVQDOTQ-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; ZVQDOTQ-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
-; ZVQDOTQ-NEXT: [[TMP11:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP8:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
-; ZVQDOTQ-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
-; ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
-; ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
-; ZVQDOTQ-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
-; ZVQDOTQ: middle.block:
-; ZVQDOTQ-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
-; ZVQDOTQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
-; ZVQDOTQ-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
-; ZVQDOTQ: scalar.ph:
+; ZVDOT4A8I-LABEL: define i32 @vdota4su2(
+; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; ZVDOT4A8I-NEXT: entry:
+; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; ZVDOT4A8I-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; ZVDOT4A8I-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; ZVDOT4A8I: vector.ph:
+; ZVDOT4A8I-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; ZVDOT4A8I-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
+; ZVDOT4A8I-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; ZVDOT4A8I-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; ZVDOT4A8I: vector.body:
+; ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 1 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; ZVDOT4A8I-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP6]], align 1
+; ZVDOT4A8I-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; ZVDOT4A8I-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP9]], align 1
+; ZVDOT4A8I-NEXT: [[TMP11:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD1]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP8:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
+; ZVDOT4A8I-NEXT: [[TMP12:%.*]] = mul <vscale x 4 x i32> [[TMP11]], [[TMP8]]
+; ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 1 x i32> @llvm.vector.partial.reduce.add.nxv1i32.nxv4i32(<vscale x 1 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP12]])
+; ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; ZVDOT4A8I-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; ZVDOT4A8I: middle.block:
+; ZVDOT4A8I-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> [[PARTIAL_REDUCE]])
+; ZVDOT4A8I-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
+; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vqdotsu2(
+; FIXED-V-LABEL: define i32 @vdota4su2(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -690,43 +690,43 @@ define i32 @vqdotsu2(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVQDOTQ-LABEL: define i32 @vqdotsu2(
-; FIXED-ZVQDOTQ-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; FIXED-ZVQDOTQ-NEXT: entry:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_PH:%.*]]
-; FIXED-ZVQDOTQ: vector.ph:
-; FIXED-ZVQDOTQ-NEXT: br label [[VECTOR_BODY:%.*]]
-; FIXED-ZVQDOTQ: vector.body:
-; FIXED-ZVQDOTQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
-; FIXED-ZVQDOTQ-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
-; FIXED-ZVQDOTQ-NEXT: [[TMP9:%.*]] = zext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP4:%.*]] = sext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP4]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP11]])
-; FIXED-ZVQDOTQ-NEXT: [[TMP10:%.*]] = zext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP8:%.*]] = sext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
-; FIXED-ZVQDOTQ-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP10]], [[TMP8]]
-; FIXED-ZVQDOTQ-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP14]])
-; FIXED-ZVQDOTQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
-; FIXED-ZVQDOTQ-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; FIXED-ZVQDOTQ-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
-; FIXED-ZVQDOTQ: middle.block:
-; FIXED-ZVQDOTQ-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; FIXED-ZVQDOTQ-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
-; FIXED-ZVQDOTQ-NEXT: br label [[FOR_EXIT:%.*]]
-; FIXED-ZVQDOTQ: for.exit:
-; FIXED-ZVQDOTQ-NEXT: ret i32 [[TMP13]]
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4su2(
+; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; FIXED-ZVDOT4A8I-NEXT: entry:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
+; FIXED-ZVDOT4A8I: vector.ph:
+; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_BODY:%.*]]
+; FIXED-ZVDOT4A8I: vector.body:
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], [[VECTOR_BODY]] ]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP5]], i64 8
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i8>, ptr [[TMP5]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i8>, ptr [[TMP7]], align 1
+; FIXED-ZVDOT4A8I-NEXT: [[TMP9:%.*]] = zext <8 x i8> [[WIDE_LOAD3]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP4:%.*]] = sext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP11:%.*]] = mul <8 x i32> [[TMP9]], [[TMP4]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP11]])
+; FIXED-ZVDOT4A8I-NEXT: [[TMP10:%.*]] = zext <8 x i8> [[WIDE_LOAD4]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP8:%.*]] = sext <8 x i8> [[WIDE_LOAD2]] to <8 x i32>
+; FIXED-ZVDOT4A8I-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP10]], [[TMP8]]
+; FIXED-ZVDOT4A8I-NEXT: [[PARTIAL_REDUCE5]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP14]])
+; FIXED-ZVDOT4A8I-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; FIXED-ZVDOT4A8I-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; FIXED-ZVDOT4A8I-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; FIXED-ZVDOT4A8I: middle.block:
+; FIXED-ZVDOT4A8I-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; FIXED-ZVDOT4A8I-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]])
+; FIXED-ZVDOT4A8I-NEXT: br label [[FOR_EXIT:%.*]]
+; FIXED-ZVDOT4A8I: for.exit:
+; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vqdotsu2(
+; TAILFOLD-LABEL: define i32 @vdota4su2(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index c07551e6cff00..79d5199ce8937 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1398,10 +1398,10 @@ Experimental extensions
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
zvbc32e 0.7
+ zvdot4a8i 0.0
zvfbfa 0.1
zvfofp8min 0.2
zvkgs 0.7
- zvqdotq 0.0
smpmpmt 0.6
svukte 0.3
xrivosvisni 0.1
>From e3c1f5f8681bdad97bbbafcba00d272769b4d6fc Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 2 Feb 2026 21:09:21 -0800
Subject: [PATCH 2/4] fixup! clang-format
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ba7622781ddfa..d1d6f7e7e31f4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9222,7 +9222,8 @@ SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
SelectionDAG &DAG) const {
- // Currently, only the vdota4 and vdota4u case (from zvdot4a8i) should be legal.
+ // Currently, only the vdota4 and vdota4u case (from zvdot4a8i) should be
+ // legal.
// TODO: There are many other sub-cases we could potentially lower, are
// any of them worthwhile? Ex: via vredsum, vwredsum, vwwmaccu, etc..
SDLoc DL(Op);
>From ad9e696aaff390bd50dd5964600fe53ea88c2daa Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 2 Feb 2026 21:26:27 -0800
Subject: [PATCH 3/4] fixup! version number
---
clang/include/clang/Basic/riscv_vector.td | 19 +++++++++++--------
.../Driver/print-supported-extensions-riscv.c | 2 +-
.../test/Preprocessor/riscv-target-features.c | 4 ++--
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++--
llvm/test/MC/RISCV/attribute-arch.s | 4 ++--
.../TargetParser/RISCVISAInfoTest.cpp | 2 +-
7 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 718725555c845..1389ffc75cb60 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2095,14 +2095,17 @@ multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> {
}
}
-// Only SEW=32 is defined for zvdot4a8i so far, and since inputs are in fact four
-// 8-bit integer bundles, we use unsigned type to represent all of them
+// Only SEW=32 is defined for zvdot4a8i so far, and since inputs are in fact
+// four 8-bit integer bundles, we use unsigned type to represent all of them
let RequiredFeatures = ["zvdot4a8i"] in {
- defm vdota4 : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"],
- ["vx", "v", "vv(FixedSEW:8)vUe"]]>;
- defm vdota4u : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"],
- ["vx", "Uv", "UvUv(FixedSEW:8)UvUe"]]>;
- defm vdota4su : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"],
- ["vx", "v", "vv(FixedSEW:8)vUe"]]>;
+ defm vdota4
+ : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"],
+ ["vx", "v", "vv(FixedSEW:8)vUe"]]>;
+ defm vdota4u
+ : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"],
+ ["vx", "Uv", "UvUv(FixedSEW:8)UvUe"]]>;
+ defm vdota4su
+ : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"],
+ ["vx", "v", "vv(FixedSEW:8)vUe"]]>;
defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vv(FixedSEW:8)UvUe"]]>;
}
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 521550ebe4539..6023f07cc577f 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -249,7 +249,7 @@
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
-// CHECK-NEXT: zvdot4a8i 0.0 'Zvdot4a8i' (Vector quad widening 4D Dot Product)
+// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector quad widening 4D Dot Product)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 1bd18ec65cb7e..bd1b1a286d5f5 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1636,10 +1636,10 @@
// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvdot4a8i0p0 -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvdot4a8i0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvdot4a8i0p0 -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvdot4a8i0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
// CHECK-ZVDOT4A8I-EXT: __riscv_zvdot4a8i 0{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 0033daf8c486b..fcd22a1ca8bb4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -877,7 +877,7 @@ def FeatureStdExtZvksg
// Vector quad widening dot product
def FeatureStdExtZvdot4a8i
- : RISCVExperimentalExtension<0, 0, "Vector quad widening 4D Dot Product",
+ : RISCVExperimentalExtension<0, 1, "Vector quad widening 4D Dot Product",
[FeatureStdExtZve32x]>;
def HasStdExtZvdot4a8i : Predicate<"Subtarget->hasStdExtZvdot4a8i()">,
AssemblerPredicate<(all_of FeatureStdExtZvdot4a8i),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 26922fd413acb..3f410518446bc 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -428,7 +428,7 @@
; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
-; RV32ZVDOT4A8I: .attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p0_zve32x1p0_zvl32b1p0"
+; RV32ZVDOT4A8I: .attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0"
@@ -580,7 +580,7 @@
; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
-; RV64ZVDOT4A8I: .attribute 5, "rv64i2p1_zicsr2p0_zvdot4a8i0p0_zve32x1p0_zvl32b1p0"
+; RV64ZVDOT4A8I: .attribute 5, "rv64i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index c0ff3ef740ca4..0e0301c8b1898 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -177,8 +177,8 @@
.attribute arch, "rv32i_zvkt1p0"
# CHECK: attribute 5, "rv32i2p1_zvkt1p0"
-.attribute arch, "rv32i_zvdot4a8i0p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p0_zve32x1p0_zvl32b1p0"
+.attribute arch, "rv32i_zvdot4a8i0p1"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p1_zbs1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 79d5199ce8937..046e7d9aa3569 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1398,7 +1398,7 @@ Experimental extensions
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
zvbc32e 0.7
- zvdot4a8i 0.0
+ zvdot4a8i 0.1
zvfbfa 0.1
zvfofp8min 0.2
zvkgs 0.7
>From 6e419db4de9b456e03fc54b31e70fc43ad4654fd Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 2 Feb 2026 22:55:02 -0800
Subject: [PATCH 4/4] fixup! version number and link
---
llvm/docs/RISCVUsage.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8a9d3702ecd19..8f364b343f979 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -351,7 +351,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__.
``experimental-zvdot4a8i``
- LLVM implements the `0.0.1 draft specification <https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1>`__.
+ LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__.
``experimental-smpmpmt``
LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__.
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