[clang] [clang-tools-extra] [compiler-rt] [llvm] [X86] AMD Zen 6 Initial enablement (PR #179150)

[via cfe-commits]

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@@ -33190,6 +33190,12 @@ static SDValue LowerBITREVERSE(SDValue Op, const X86Subtarget &Subtarget,
 
   unsigned NumElts = VT.getVectorNumElements();
 
+  // If we have BMM, we can use VPBITREVB to reverse the bits in each byte.
+  // BMM implies VLX support, so this works for 128/256/512-bit vectors.
+  if (Subtarget.hasBMM() && VT.getSizeInBits() >= 128) {
+    return DAG.getNode(X86ISD::VPBITREVB, DL, VT, In);
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ganeshgit wrote:

Yes will do it. Will split the patch into two. 
1. For znver6 skeleton enablement
2. BMM removing BITREVB and using the generics. 

https://github.com/llvm/llvm-project/pull/179150