[clang] [clang-tools-extra] [compiler-rt] [llvm] [X86] AMD Zen 6 Initial enablement (PR #179150)

[Simon Pilgrim via cfe-commits]

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@@ -145,6 +145,9 @@ def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
                       "Enable AVX-512 further Vector Byte Manipulation Instructions",
                                       [FeatureBWI]>;
+def FeatureBMM : SubtargetFeature<"avx512bmm", "HasBMM", "true",
+                 "Enable AVX512 Bit Manipulation Instructions",[FeatureVLX]>;
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RKSimon wrote:

Its unusual for an AVX512 512-bit ISA feature to depends on VLX? Also, don't you need FeatureBWI to make the mask types legal?

https://github.com/llvm/llvm-project/pull/179150