[clang] 7cf30a7 - [PowerPC] Add Support for BCDSHIFT, BCDSHIFTR, BCDTRUNC, BCDUTRUNC, and BCDUSHIFT instruction support (#154715)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Jan 21 08:04:12 PST 2026
Author: Aditi Medhane
Date: 2026-01-21T21:34:06+05:30
New Revision: 7cf30a7d3dca64b219a82a69bbd81beee41f514f
URL: https://github.com/llvm/llvm-project/commit/7cf30a7d3dca64b219a82a69bbd81beee41f514f
DIFF: https://github.com/llvm/llvm-project/commit/7cf30a7d3dca64b219a82a69bbd81beee41f514f.diff
LOG: [PowerPC] Add Support for BCDSHIFT, BCDSHIFTR, BCDTRUNC, BCDUTRUNC, and BCDUSHIFT instruction support (#154715)
Support the following BCD format conversion builtins for PowerPC.
- `__builtin_bcdshift` – Shifts a packed decimal value by a specified
number of decimal digits.
- `__builtin_bcdshiftround` – Shifts a packed decimal value by a
specified number of decimal digits, with rounding applied.
- `__builtin_bcdtruncate` –Truncates a packed decimal value to a
specified number of digits.
- `__builtin_bcdunsignedtruncate` – Truncates a packed decimal value and
returns the result as an unsigned packed decimal.
- `__builtin_bcdunsignedshift` – Shifts an unsigned packed decimal value
by a specified number of digits.
> Note: This built-in functions are valid only when all following
conditions are met:
> -qarch is set to utilize POWER9 technology.
> The bcd.h file is included.
## Prototypes
```c
vector unsigned char __builtin_bcdshift(vector unsigned char, int, unsigned char);
vector unsigned char __builtin_bcdshiftround(vector unsigned char, int, unsigned char);
vector unsigned char __builtin_bcdtruncate(vector unsigned char, int, unsigned char);
vector unsigned char __builtin_bcdunsignedtruncate(vector unsigned char, int);
vector unsigned char __builtin_bcdunsignedshift(vector unsigned char, int);
```
---------
Added:
clang/test/Sema/builtins-bcd-format-conversion.c
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaPPC.cpp
clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index f518429136e3c..75d7d92c4f9d4 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -582,6 +582,11 @@ TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "",
// P9 Binary-coded decimal (BCD) builtins.
TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", "power9-vector")
TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdshift, "V16UcV16UciUc", "t", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdshiftround, "V16UcV16UciUc", "t", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdtruncate, "V16UcV16UciUc", "t", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdunsignedtruncate, "V16UcV16Uci", "", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdunsignedshift, "V16UcV16Uci", "", "power9-vector")
TARGET_BUILTIN(__builtin_ppc_national2packed, "V16UcV16UcUc", "t", "power9-vector")
TARGET_BUILTIN(__builtin_ppc_packed2national, "V16UcV16Uc", "", "power9-vector")
TARGET_BUILTIN(__builtin_ppc_packed2zoned, "V16UcV16UcUc", "t", "power9-vector")
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 44541a4c68197..a2be7ab3791b9 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11259,6 +11259,8 @@ def err_ppc_invalid_use_mma_type : Error<
"invalid use of PPC MMA type">;
def err_ppc_invalid_test_data_class_type : Error<
"expected a 'float', 'double' or '__float128' for the first argument">;
+def err_ppc_invalid_arg_type : Error<
+ "argument %0 must be of type %1">;
def err_x86_builtin_invalid_rounding : Error<
"invalid rounding argument">;
def err_x86_builtin_invalid_scale : Error<
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index a6e1ad10568bb..a37a68ad91724 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -91,6 +91,13 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign");
Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign");
+ Builder.defineMacro("__builtin_bcdshift", "__builtin_ppc_bcdshift");
+ Builder.defineMacro("__builtin_bcdshiftround", "__builtin_ppc_bcdshiftround");
+ Builder.defineMacro("__builtin_bcdtruncate", "__builtin_ppc_bcdtruncate");
+ Builder.defineMacro("__builtin_bcdunsignedtruncate",
+ "__builtin_ppc_bcdunsignedtruncate");
+ Builder.defineMacro("__builtin_bcdunsignedshift",
+ "__builtin_ppc_bcdunsignedshift");
Builder.defineMacro("__builtin_national2packed",
"__builtin_ppc_national2packed");
Builder.defineMacro("__builtin_packed2national",
diff --git a/clang/lib/Sema/SemaPPC.cpp b/clang/lib/Sema/SemaPPC.cpp
index 1bf806d996887..149c564bd5b84 100644
--- a/clang/lib/Sema/SemaPPC.cpp
+++ b/clang/lib/Sema/SemaPPC.cpp
@@ -114,6 +114,36 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo &TI,
return Diag(TheCall->getBeginLoc(), diag::err_64_bit_builtin_32_bit_tgt)
<< TheCall->getSourceRange();
+ // Common BCD type-validation helpers
+ // Emit error diagnostics and return true on success
+ // - IsTypeVecUChar: enforces vector unsigned char
+ // - IsIntType: enforces any integer type
+ // Lambdas centralize type checks for BCD builtin handlers
+
+ // Lambda 1: verify vector unsigned char type
+ auto IsTypeVecUChar = [&](QualType ArgTy, unsigned ArgIndex) -> bool {
+ QualType VecType = Context.getVectorType(Context.UnsignedCharTy, 16,
+ VectorKind::AltiVecVector);
+ if (Context.hasSameType(ArgTy, VecType))
+ return true;
+
+ Diag(TheCall->getArg(ArgIndex)->getBeginLoc(),
+ diag::err_ppc_invalid_arg_type)
+ << ArgIndex << VecType << ArgTy;
+ return false;
+ };
+
+ // Lambda 2: verify integer type
+ auto IsIntType = [&](QualType ArgTy, unsigned ArgIndex) -> bool {
+ if (ArgTy->isIntegerType())
+ return true;
+
+ Diag(TheCall->getArg(ArgIndex)->getBeginLoc(),
+ diag::err_ppc_invalid_arg_type)
+ << ArgIndex << "integer" << ArgTy;
+ return false;
+ };
+
switch (BuiltinID) {
default:
return false;
@@ -122,6 +152,21 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo &TI,
case PPC::BI__builtin_ppc_packed2zoned:
case PPC::BI__builtin_ppc_zoned2packed:
return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1);
+ case PPC::BI__builtin_ppc_bcdshift:
+ case PPC::BI__builtin_ppc_bcdshiftround:
+ case PPC::BI__builtin_ppc_bcdtruncate: {
+
+ // Arg0 must be vector unsigned char
+ if (!IsTypeVecUChar(TheCall->getArg(0)->getType(), 0))
+ return false;
+
+ // Arg1 must be integer type
+ if (!IsIntType(TheCall->getArg(1)->getType(), 1))
+ return false;
+
+ // Restrict Arg2 constant range (0–1)
+ return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 1);
+ }
case PPC::BI__builtin_altivec_crypto_vshasigmaw:
case PPC::BI__builtin_altivec_crypto_vshasigmad:
return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) ||
diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c b/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c
index 0aeb720e545ed..885fb82fbcba8 100644
--- a/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c
+++ b/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c
@@ -27,3 +27,59 @@ vector unsigned char test_bcdsetsign_imm0(vector unsigned char a) {
vector unsigned char test_bcdsetsign_imm1(vector unsigned char a) {
return __builtin_ppc_bcdsetsign(a, '\1');
}
+
+// CHECK-LABEL: test_bcdshift_imm0
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 0)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdshift_imm0(vector unsigned char a, int b, unsigned char c){
+ return __builtin_ppc_bcdshift(a,b,'\0');
+}
+
+// CHECK-LABEL: test_bcdshift_imm1
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 1)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdshift_imm1(vector unsigned char a, int b, unsigned char c){
+ return __builtin_ppc_bcdshift(a,b,'\1');
+}
+
+// CHECK-LABEL: test_bcdshiftround_imm0
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 0)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdshiftround_imm0(vector unsigned char a,int b, unsigned char c){
+ return __builtin_ppc_bcdshiftround(a,b,'\0');
+}
+
+// CHECK-LABEL: test_bcdshiftround_imm1
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 1)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdshiftround_imm1(vector unsigned char a,int b, unsigned char c){
+ return __builtin_ppc_bcdshiftround(a,b,'\1');
+}
+
+// CHECK-LABEL: test_bcdtruncate_imm0
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 0)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdtruncate_imm0(vector unsigned char a, int b, unsigned char c){
+ return __builtin_ppc_bcdtruncate(a,b,'\0');
+}
+
+// CHECK-LABEL: test_bcdtruncate_imm1
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 1)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdtruncate_imm1(vector unsigned char a, int b, unsigned char c){
+ return __builtin_ppc_bcdtruncate(a,b,'\1');
+}
+
+// CHECK-LABEL: test_bcdunsignedtruncate
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8> %a, i32 %b)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdunsignedtruncate(vector unsigned char a, int b) {
+ return __builtin_ppc_bcdunsignedtruncate(a, b);
+}
+
+// CHECK-LABEL: test_bcdunsignedshift
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8> %a, i32 %b)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdunsignedshift(vector unsigned char a, int b){
+ return __builtin_ppc_bcdunsignedshift(a,b);
+}
diff --git a/clang/test/Sema/builtins-bcd-format-conversion.c b/clang/test/Sema/builtins-bcd-format-conversion.c
new file mode 100644
index 0000000000000..30bbd32a0f653
--- /dev/null
+++ b/clang/test/Sema/builtins-bcd-format-conversion.c
@@ -0,0 +1,40 @@
+// Testfile to verify Sema diagnostics for BCD builtins bcdshift, bcdshiftround, bcdtruncate.
+
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown -fsyntax-only -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -fsyntax-only -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown -fsyntax-only -verify %s
+
+#include <altivec.h>
+#define DECL_COMMON_VARS \
+ vector unsigned char vec = {1,2,3,4}; \
+ unsigned char scalar = 1; \
+ int i = 1; \
+ float f = 1.0f;
+
+vector unsigned char test_bcdshift(void) {
+ DECL_COMMON_VARS
+ vector unsigned char res_a = __builtin_ppc_bcdshift(scalar, i, i); // expected-error {{argument 0 must be of type '__vector unsigned char' (vector of 16 'unsigned char' values)}}
+ vector unsigned char res_b = __builtin_ppc_bcdshift(vec, f, i); // expected-error {{argument 1 must be of type integer}}
+ vector unsigned char res_c = __builtin_ppc_bcdshift(vec, i, 2); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+ vector unsigned char res_d = __builtin_ppc_bcdshift(vec, i, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+ return __builtin_ppc_bcdshift(vec, i, 1);
+}
+
+vector unsigned char test_bcdshiftround(void) {
+ DECL_COMMON_VARS
+ vector unsigned char res_a = __builtin_ppc_bcdshiftround(scalar, i, i); // expected-error {{argument 0 must be of type '__vector unsigned char' (vector of 16 'unsigned char' values)}}
+ vector unsigned char res_b = __builtin_ppc_bcdshiftround(vec, f, i); // expected-error {{argument 1 must be of type integer}}
+ vector unsigned char res_c = __builtin_ppc_bcdshiftround(vec, i, 2); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+ vector unsigned char res_d = __builtin_ppc_bcdshiftround(vec, i, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+ return __builtin_ppc_bcdshiftround(vec, i, 1);
+}
+
+vector unsigned char test_bcdtruncate(void) {
+ DECL_COMMON_VARS
+ vector unsigned char res_a = __builtin_ppc_bcdtruncate(scalar, i, i); // expected-error {{argument 0 must be of type '__vector unsigned char' (vector of 16 'unsigned char' values)}}
+ vector unsigned char res_b = __builtin_ppc_bcdtruncate(vec, f, i); // expected-error {{argument 1 must be of type integer}}
+ vector unsigned char res_c = __builtin_ppc_bcdtruncate(vec, i, 2); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+ vector unsigned char res_d = __builtin_ppc_bcdtruncate(vec, i, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+ return __builtin_ppc_bcdtruncate(vec, i, 1);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ce27e9163560b..ec33af88c72d9 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -689,6 +689,31 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
+ def int_ppc_bcdshift : ClangBuiltin<"__builtin_ppc_bcdshift">,
+ DefaultAttrsIntrinsic<
+ [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+
+ def int_ppc_bcdshiftround : ClangBuiltin<"__builtin_ppc_bcdshiftround">,
+ DefaultAttrsIntrinsic<
+ [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+
+ def int_ppc_bcdtruncate : ClangBuiltin<"__builtin_ppc_bcdtruncate">,
+ DefaultAttrsIntrinsic<
+ [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+
+ def int_ppc_bcdunsignedtruncate : ClangBuiltin<"__builtin_ppc_bcdunsignedtruncate">,
+ DefaultAttrsIntrinsic<
+ [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem]>;
+
+ def int_ppc_bcdunsignedshift : ClangBuiltin<"__builtin_ppc_bcdunsignedshift">,
+ DefaultAttrsIntrinsic<
+ [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem]>;
+
def int_ppc_bcdadd : ClangBuiltin<"__builtin_ppc_bcdadd">,
DefaultAttrsIntrinsic<
[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 641b7804097f8..1d329f21d3dcd 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11024,6 +11024,19 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
unsigned IntrinsicID = Op.getConstantOperandVal(0);
SDLoc dl(Op);
+ // Note: BCD instructions expect the immediate operand in vector form (v4i32),
+ // but the builtin provides it as a scalar. To satisfy the instruction
+ // encoding, we splat the scalar across all lanes using SPLAT_VECTOR.
+ auto MapNodeWithSplatVector =
+ [&](unsigned Opcode,
+ std::initializer_list<SDValue> ExtraOps = {}) -> SDValue {
+ SDValue SplatVal =
+ DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2));
+
+ SmallVector<SDValue, 4> Ops{SplatVal, Op.getOperand(1)};
+ Ops.append(ExtraOps.begin(), ExtraOps.end());
+ return DAG.getNode(Opcode, dl, MVT::v16i8, Ops);
+ };
switch (IntrinsicID) {
case Intrinsic::thread_pointer:
@@ -11078,6 +11091,17 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
0);
}
+ case Intrinsic::ppc_bcdshift:
+ return MapNodeWithSplatVector(PPCISD::BCDSHIFT, {Op.getOperand(3)});
+ case Intrinsic::ppc_bcdshiftround:
+ return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND, {Op.getOperand(3)});
+ case Intrinsic::ppc_bcdtruncate:
+ return MapNodeWithSplatVector(PPCISD::BCDTRUNC, {Op.getOperand(3)});
+ case Intrinsic::ppc_bcdunsignedtruncate:
+ return MapNodeWithSplatVector(PPCISD::BCDUTRUNC);
+ case Intrinsic::ppc_bcdunsignedshift:
+ return MapNodeWithSplatVector(PPCISD::BCDUSHIFT);
+
case Intrinsic::ppc_rlwnm: {
if (Op.getConstantOperandVal(3) == 0)
return DAG.getConstant(0, dl, MVT::i32);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index fe1eea2b33615..b82fbf9136e4c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1662,6 +1662,22 @@ def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>;
+// Patterns mapping BCD PPCISD nodes to machine instructions
+def : Pat<(PPCbcds v4i32:$Shift, v16i8:$Src, i32:$PS),
+ (BCDS_rec $Shift, $Src, $PS)>;
+
+def : Pat<(PPCbcdsr v4i32:$ShiftRound, v16i8:$Src, i32:$PS),
+ (BCDSR_rec $ShiftRound, $Src, $PS)>;
+
+def : Pat<(PPCbcdtrunc v4i32:$Trunc, v16i8:$Src, i32:$PS),
+ (BCDTRUNC_rec $Trunc, $Src, $PS)>;
+
+def : Pat<(PPCbcdutrunc v4i32:$Trunc, v16i8:$Src),
+ (BCDUTRUNC_rec $Trunc, $Src)>;
+
+def : Pat<(PPCbcdus v4i32:$Shift, v16i8:$Src),
+ (BCDUS_rec $Shift, $Src)>;
+
// Absolute Difference
def VABSDUB : VXForm_1<1027, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vabsdub $VD, $VA, $VB", IIC_VecGeneral,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3f9c482979e61..5e2e51ab16671 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -143,6 +143,26 @@ def SDT_PPCBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [
SDTCisVT<1, i32>,
]>;
+def SDT_PPCBcdShift : SDTypeProfile<1, 3, [ SDTCisVT<0, v16i8>,
+ SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>, SDTCisInt<3>
+]>;
+
+def SDT_PPCBcdShiftRound : SDTypeProfile<1, 3, [ SDTCisVT<0, v16i8>,
+ SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>, SDTCisInt<3>
+]>;
+
+def SDT_PPCBcdTrunc : SDTypeProfile<1, 3, [ SDTCisVT<0, v16i8>,
+ SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>, SDTCisInt<3>
+]>;
+
+def SDT_PPCBcdUTrunc : SDTypeProfile<1, 2, [ SDTCisVT<0, v16i8>,
+ SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>
+]>;
+
+def SDT_PPCBcdUShift : SDTypeProfile<1, 2, [ SDTCisVT<0, v16i8>,
+ SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>
+]>;
+
def SDT_PPCstat : SDTypeProfile<0, 3, [
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
]>;
@@ -682,6 +702,11 @@ def PPCsubc : SDNode<"PPCISD::SUBC", SDT_PPCBinaryArithWithFlagsOut,
[]>;
def PPCsube : SDNode<"PPCISD::SUBE", SDT_PPCBinaryArithWithFlagsInOut,
[]>;
+def PPCbcds : SDNode<"PPCISD::BCDSHIFT", SDT_PPCBcdShift, []>;
+def PPCbcdsr : SDNode<"PPCISD::BCDSHIFTROUND", SDT_PPCBcdShiftRound, []>;
+def PPCbcdtrunc : SDNode<"PPCISD::BCDTRUNC", SDT_PPCBcdTrunc, []>;
+def PPCbcdutrunc : SDNode<"PPCISD::BCDUTRUNC", SDT_PPCBcdUTrunc, []>;
+def PPCbcdus : SDNode<"PPCISD::BCDUSHIFT", SDT_PPCBcdUShift, []>;
def PPCstat : SDNode<"PPCISD::STAT", SDT_PPCstat,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
diff --git a/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll b/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll
index ede86254b1516..29cbda904f564 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll
@@ -6,7 +6,7 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
-define dso_local <16 x i8> @test_bcdcopysign(<16 x i8> noundef %a, <16 x i8> noundef %b) {
+define <16 x i8> @test_bcdcopysign(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_bcdcopysign:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdcpsgn. v2, v2, v3
@@ -16,7 +16,7 @@ entry:
ret <16 x i8> %0
}
-define dso_local <16 x i8> @test_bcdsetsign_imm0(<16 x i8> noundef %a) {
+define <16 x i8> @test_bcdsetsign_imm0(<16 x i8> %a) {
; CHECK-LABEL: test_bcdsetsign_imm0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsetsgn. v2, v2, 0
@@ -26,7 +26,7 @@ entry:
ret <16 x i8> %0
}
-define dso_local <16 x i8> @test_bcdsetsign_imm1(<16 x i8> noundef %a) {
+define <16 x i8> @test_bcdsetsign_imm1(<16 x i8> %a) {
; CHECK-LABEL: test_bcdsetsign_imm1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsetsgn. v2, v2, 1
@@ -36,5 +36,106 @@ entry:
ret <16 x i8> %0
}
+define <16 x i8> @test_bcdshift_imm0(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdshift_imm0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcds. v2, v3, v2, 0
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 0)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdshift_imm1(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdshift_imm1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcds. v2, v3, v2, 1
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 1)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdshiftround_imm0(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdshiftround_imm0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcdsr. v2, v3, v2, 0
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 0)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdshiftround_imm1(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdshiftround_imm1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcdsr. v2, v3, v2, 1
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 1)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdtruncate_imm0(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdtruncate_imm0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcdtrunc. v2, v3, v2, 0
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 0)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdtruncate_imm1(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdtruncate_imm1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcdtrunc. v2, v3, v2, 1
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 1)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdunsignedtruncate(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdunsignedtruncate:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcdutrunc. v2, v3, v2
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8> %a, i32 %b)
+ ret <16 x i8> %0
+}
+
+define <16 x i8> @test_bcdunsignedshift(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_bcdunsignedshift:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
+; CHECK-NEXT: bcdus. v2, v3, v2
+; CHECK-NEXT: blr
+
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8> %a, i32 %b)
+ ret <16 x i8> %0
+}
+
declare <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8>, i32)
+declare <16 x i8> @llvm.ppc.bcdshift(<16 x i8>, i32, i32)
+declare <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8>, i32, i32)
+declare <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8>, i32, i32)
+declare <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8>, i32)
+declare <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8>, i32)
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