[clang] 9040212 - [CIR][X86]Implement handling for shiftleft/shiftright builtins in CIR (#176653)

[via cfe-commits]

Author: Priyanshu Kumar
Date: 2026-01-20T10:50:41-08:00
New Revision: 9040212669c189c8c520c25693806157e563e6f8

URL: https://github.com/llvm/llvm-project/commit/9040212669c189c8c520c25693806157e563e6f8
DIFF: https://github.com/llvm/llvm-project/commit/9040212669c189c8c520c25693806157e563e6f8.diff

LOG: [CIR][X86]Implement handling for shiftleft/shiftright builtins in CIR (#176653)

Related to: #167765

---------

Co-authored-by: Roberto Turrado Camblor <rturrado at gmail.com>

Added: 
    

Modified: 
    clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
    clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 6c01cbd7f699f..a4af08a222566 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -2268,10 +2268,23 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
   }
   case X86::BI__shiftleft128:
   case X86::BI__shiftright128: {
-    cgm.errorNYI(expr->getSourceRange(),
-                 std::string("unimplemented X86 builtin call: ") +
-                     getContext().BuiltinInfo.getName(builtinID));
-    return mlir::Value{};
+    // Flip low/high ops and zero-extend amount to matching type.
+    // shiftleft128(Low, High, Amt) -> fshl(High, Low, Amt)
+    // shiftright128(Low, High, Amt) -> fshr(High, Low, Amt)
+    std::swap(ops[0], ops[1]);
+
+    // Zero-extend shift amount to i64 if needed
+    auto amtTy = mlir::cast<cir::IntType>(ops[2].getType());
+    cir::IntType i64Ty = builder.getUInt64Ty();
+
+    if (amtTy != i64Ty)
+      ops[2] = builder.createIntCast(ops[2], i64Ty);
+
+    const StringRef intrinsicName =
+        (builtinID == X86::BI__shiftleft128) ? "fshl" : "fshr";
+    return emitIntrinsicCallOp(builder, getLoc(expr->getExprLoc()),
+                               intrinsicName, i64Ty,
+                               mlir::ValueRange{ops[0], ops[1], ops[2]});
   }
   case X86::BI_ReadWriteBarrier:
   case X86::BI_ReadBarrier:

diff  --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
index 1f80a683aa3cd..e56310ac113ce 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
@@ -7,6 +7,55 @@
 // RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -emit-llvm -o %t.ll -Wall -Werror %s
 // RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s
 
+unsigned __int64 __shiftleft128(unsigned __int64 low, unsigned __int64 high,
+                                unsigned char shift);
+unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high,
+                                 unsigned char shift);
+
+// CIR-LABEL: cir.func{{.*}}@test_shiftleft128
+// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} : !cir.ptr<!u8i>, !u8i
+// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
+// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
+// CIR: cir.return
+
+// LLVM-LABEL: define {{.*}} i64 @test_shiftleft128
+// LLVM-SAME: (i64 %{{.*}}, i64 %{{.*}}, i8 %{{.*}})
+// LLVM: [[TMP1:%.*]] = zext i8 %{{.*}} to i64
+// LLVM-NEXT: {{.*}} = call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]])
+
+// OGCG-LABEL: define {{.*}} i64 @test_shiftleft128
+// OGCG-SAME: (i64 {{.*}} %{{.*}}, i64 {{.*}} %{{.*}}, i8 {{.*}} %{{.*}})
+// OGCG-NEXT: entry:
+// OGCG: [[TMP:%.*]] = zext i8 {{.*}} to i64
+// OGCG-NEXT: {{.*}} = call i64 @llvm.fshl.i64(i64 {{.*}}, i64 {{.*}}, i64 [[TMP]])
+// OGCG-NEXT: ret i64
+unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h,
+                                   unsigned char d) {
+  return __shiftleft128(l, h, d);
+}
+
+// CIR-LABEL: cir.func{{.*}}@test_shiftright128
+// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} : !cir.ptr<!u8i>, !u8i
+// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
+// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshr" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
+// CIR: cir.return
+
+// LLVM-LABEL: define {{.*}} i64 @test_shiftright128
+// LLVM-SAME: (i64 %{{.*}}, i64 %{{.*}}, i8 %{{.*}})
+// LLVM: [[TMP1:%.*]] = zext i8 %{{.*}} to i64
+// LLVM-NEXT: {{.*}} = call i64 @llvm.fshr.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]])
+
+// OGCG-LABEL: define {{.*}} i64 @test_shiftright128
+// OGCG-SAME: (i64 {{.*}} %{{.*}}, i64 {{.*}} %{{.*}}, i8 {{.*}} %{{.*}})
+// OGCG-NEXT: entry:
+// OGCG: [[TMP:%.*]] = zext i8 {{.*}} to i64
+// OGCG-NEXT: {{.*}} = call i64 @llvm.fshr.i64(i64 {{.*}}, i64 {{.*}}, i64 [[TMP]])
+// OGCG-NEXT: ret i64
+unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h,
+                                    unsigned char d) {
+  return __shiftright128(l, h, d);
+}
+
 #pragma intrinsic(__cpuid)
 #pragma intrinsic(__cpuidex)