[clang] [llvm] [RISC-V][MC] Introduce RVY extension feature (PR #176870)
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Mon Jan 19 22:59:11 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Alexander Richardson (arichardson)
<details>
<summary>Changes</summary>
This adds initial features for the base RVY extension,
other extensions such as the hybrid mode will be added later.
Co-authored-by: Jessica Clarke <jrtc27@<!-- -->jrtc27.com>
Co-authored-by: Petr Vesely <petr.vesely@<!-- -->codasip.com>
---
Full diff: https://github.com/llvm/llvm-project/pull/176870.diff
5 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+22-1)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (+2)
- (modified) llvm/test/MC/RISCV/invalid-attribute.s (+2-2)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1)
``````````diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 548a0d5cf6200..9eb2d2e25d01b 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -239,6 +239,7 @@
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: p 0.18 'P' ('Base P' (Packed SIMD))
+// CHECK-NEXT: y 0.96 'Y' ('Base Y' (CHERI))
// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index b8d1f775ff322..b818a356d6ce5 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1119,6 +1119,28 @@ def HasStdExtZbkbOrP
"'Zbkb' (Bitmanip instructions for Cryptography) or "
"'Base P' (Packed-SIMD)">;
+// "Y" extension (CHERI support)
+
+def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">;
+def HasStdExtY
+ : Predicate<"Subtarget->hasStdExtY()">,
+ AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">;
+
+// When enabled all memory operations (e.g. loads/stores) uses capability
+// registers as the base operand instead of the address sub-register.
+// Currently, capability mode needs to be chosen at assembly time, but follow-up
+// commits will add support for "hybrid" mode that adds instructions to
+// dynamically switch between capability mode and address mode (the latter being
+// fully backwards compatible with non-Y code).
+def FeatureCapMode : SubtargetFeature<"cap-mode", "IsCapMode", "true",
+ "Capability pointer mode">;
+def IsCapMode
+ : Predicate<"Subtarget->isCapMode()">,
+ AssemblerPredicate<(all_of FeatureCapMode), "Capability Pointer Mode">;
+def NotCapMode : Predicate<"!Subtarget->isCapMode()">,
+ AssemblerPredicate<(all_of(not FeatureCapMode)),
+ "Not Capability Pointer Mode">;
+
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
@@ -1980,4 +2002,3 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
"Ventana Veyron-Series processors">;
-
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 1bafca4dff945..6f8b37f3a06d3 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -14,6 +14,7 @@
; CHECK-NEXT: b - 'B' (the collection of the Zba, Zbb, Zbs extensions).
; CHECK-NEXT: bfext-fusion - Enable SLLI+SRLI (bitfield extract) macrofusion.
; CHECK-NEXT: c - 'C' (Compressed Instructions).
+; CHECK-NEXT: cap-mode - Capability pointer mode.
; CHECK-NEXT: conditional-cmv-fusion - Enable branch+c.mv fusion.
; CHECK-NEXT: d - 'D' (Double-Precision Floating-Point).
; CHECK-NEXT: disable-latency-sched-heuristic - Disable latency scheduling heuristic.
@@ -34,6 +35,7 @@
; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).
+; CHECK-NEXT: experimental-y - 'Y' ('Base Y' (CHERI)).
; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions).
; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate).
; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).
diff --git a/llvm/test/MC/RISCV/invalid-attribute.s b/llvm/test/MC/RISCV/invalid-attribute.s
index c640fccd15ae5..bdc10790157d7 100644
--- a/llvm/test/MC/RISCV/invalid-attribute.s
+++ b/llvm/test/MC/RISCV/invalid-attribute.s
@@ -13,8 +13,8 @@
.attribute arch, "foo"
# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g}, rv64{i,e,g}, or a supported profile name{{$}}
-.attribute arch, "rv32i2p1_y2p0"
-# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_y2p0', invalid standard user-level extension 'y'
+.attribute arch, "rv32i2p1_o2p0"
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_o2p0', invalid standard user-level extension 'o'
.attribute stack_align, "16"
# CHECK: [[@LINE-1]]:25: error: expected numeric constant
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 6d078b56ec30a..f77c9d0e7655b 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1392,6 +1392,7 @@ R"(All available -march extensions for RISC-V
Experimental extensions
p 0.18
+ y 0.96
zibi 0.1
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
``````````
</details>
https://github.com/llvm/llvm-project/pull/176870
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