[clang] [llvm] [RISCV] Add SpacemiT A100 processor definition (PR #174052)

[Alex Bradbury via cfe-commits]

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@@ -735,6 +735,38 @@ def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
                                                TuneZExtWFusion,
                                                TuneShiftedZExtWFusion]>;
 
+def SPACEMIT_A100 : RISCVProcessorModel<"spacemit-a100",
+                                        SpacemitX60Model,
+                                        !listconcat(
+                                        !listremove(RVA23S64Features,
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asb wrote:

@wangpc-pp what downside do you see to listing the S* features? Although we don't currently do anything in terms of gating CSRs or warning if they refer to extensions that weren't specifically enabled, we potentially could in the future.

https://github.com/llvm/llvm-project/pull/174052