[clang] [llvm] [RISCV] AI Foundry ET extensions for RISC-V (PR #174571)
Abel Bernabeu via cfe-commits
cfe-commits at lists.llvm.org
Mon Jan 12 23:50:33 PST 2026
https://github.com/abel-bernabeu updated https://github.com/llvm/llvm-project/pull/174571
>From db7e7fbdf98cc4a0084f6978772093ddf6c5de6b Mon Sep 17 00:00:00 2001
From: Abel Bernabeu <abel.bernabeu at gmail.com>
Date: Wed, 31 Dec 2025 23:20:26 +0000
Subject: [PATCH] [RISCV] AI Foundry ET extensions for RISC-V
This patch is part of an ongoing effort for upstreaming the AI Foundry ET
extensions for RISC-V, formerly known as the ET-SoC-1 Minion extensions by
Esperanto Technologies.
Changes
=======
The changes in this patch are:
- Defining the XAIFET feature as an "umbrella" extension under which
all the vendor extensions from ET-SoC-1 are included.
- Defining Esperanto Technologies's ET-SoC-1 Minion processor (et-soc1).
- Defining Ainekko's Erbium Minion processor (an-erbium), using the same
ISA.
- Adding the XAIFET vector register and mask register classes.
- Adding all the custsom machine instructions
Reference manual
================
Full documentation for these extensions is publicly available at the
following URL:
https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
Note on gather/scatter syntax
=============================
The assembly syntax for gather/scatter instructions used by Esperanto
Technologies used a complex source operand consisting on two registers.
For example, consider the syntax that the manual proposed for `fg32w.ps`:
fg32w.ps fd, fs1(rs1)
Note that the second operand (the source) is composed of two register
names.
While Esperanto Technologies fork of LLVM 11 supported this syntax,
it is easier to fit on the existing RISCV infrastructure if a comma is
inserted between the two source register names:
fg32w.ps fd, fs1, (rs1)
That way is as clear as the proposal from the manual and does not
require defining a complex operand consisting on two registers.
This subject was discussed on the #et-platform Discord channel, with
enough agreement on streamlining the syntax as proposed here for
llvm/clang.
Note on instruction prefixes
============================
The `aif.` prefix has been added to all the instructions under these
extensions, in line with the RISC-V toolchain practices, so an
instruction from the manual like `fadd.pi` becomes `aif.fadd.pi`
with the upstream toolchain.
The same goes for CSRs, so `fcc` becomes `aif.fcc`.
Authors
=======
This patch contains code rebased from the LLVM 11 fork by Esperanto
Technologies as published at the following URL:
https://github.com/aifoundry-org/llvm/tree/et
The list of authors that contributed to that fork follow:
- Abel Bernabeu <abel.bernabeu at esperantotech.com>, maintainer.
- David Callahan <callahan at reservoir.com>, project founder.
- Josep M. Perez <josep.m.perez at esperantotech.com>, contributor.
- Muhammad Kamran <muhammad.kamran at esperantotech.com>, contributor.
- Pere Munt <pere.munt at esperantotech.com>, contributor.
- Rafael Jimenez <rafael.jimenez at esperantotech.com>, contributor.
- Stefan Freudenberger <stefan at reservoir.com>, contributor.
---
.../Driver/print-supported-extensions-riscv.c | 1 +
llvm/docs/RISCVUsage.rst | 3 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 9 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 6 +
llvm/lib/Target/RISCV/RISCVInstrFormats.td | 3 +
.../lib/Target/RISCV/RISCVInstrFormatsXAIF.td | 265 +++++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td | 787 +++++++++++++++
llvm/lib/Target/RISCV/RISCVProcessors.td | 16 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 39 +
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 58 ++
llvm/test/CodeGen/RISCV/features-info.ll | 1 +
llvm/test/MC/RISCV/xaifet-amo-valid.s | 939 ++++++++++++++++++
llvm/test/MC/RISCV/xaifet-simd-valid.s | 673 +++++++++++++
16 files changed, 2828 insertions(+)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
create mode 100644 llvm/test/MC/RISCV/xaifet-amo-valid.s
create mode 100644 llvm/test/MC/RISCV/xaifet-simd-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 4be310244715e..ec3492c65da73 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -160,6 +160,7 @@
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
+// CHECK-NEXT: xaifet 1.0 'XAIFET' (AI Foundry ET Extension)
// CHECK-NEXT: xandesbfhcvt 5.0 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index df5a595e8ec93..c24d04700bb64 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -370,6 +370,9 @@ It is our intention to follow the naming conventions described in `riscv-non-isa
The current vendor extensions supported are:
+``XAIFET``
+ LLVM implements `the AIFET (AI Foundry's ET) vendor-defined instructions specified in <https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf>`__ originally defined by Esperanto Technologies (and now under the AI Foundry non-profit). Instructions are prefixed with `aif.` as described in the specification.
+
``XTHeadBa``
LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 9bb3724c96c11..e9d72aceb0e88 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1316,6 +1316,11 @@ static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
&RISCVMCRegisterClasses[RegClassID]);
}
+static MCRegister convertFPR64ToFPR256(MCRegister Reg) {
+ assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
+ return Reg - RISCV::F0_D + RISCV::F0_Q2;
+}
+
unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
unsigned Kind) {
RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp);
@@ -1329,6 +1334,10 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
+ if (IsRegFPR64 && Kind == MCK_FPR256) {
+ Op.Reg.Reg = convertFPR64ToFPR256(Reg);
+ return Match_Success;
+ }
if (IsRegFPR64 && Kind == MCK_FPR128) {
Op.Reg.Reg = convertFPR64ToFPR128(Reg);
return Match_Success;
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index fba9fa2f1c1de..cacb07fb65501 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -194,6 +194,28 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeFPR256RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32)
+ return MCDisassembler::Fail;
+
+ MCRegister Reg = RISCV::F0_Q2 + RegNo;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 8)
+ return MCDisassembler::Fail;
+
+ MCRegister Reg = RISCV::M0 + RegNo;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X1));
@@ -686,6 +708,8 @@ static constexpr FeatureBitset XAndesGroup = {
static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
+static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET};
+
static constexpr DecoderListEntry DecoderList32[]{
// Vendor Extensions
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
@@ -701,6 +725,7 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
+ {DecoderTableXAIF32, XAIFGroup, "AI Foundry extensions"},
// Standard Extensions
{DecoderTable32, {}, "standard 32-bit instructions"},
{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index a047324ef36fa..cda2f95bbef78 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -414,6 +414,7 @@ enum OperandType : unsigned {
OPERAND_SIMM12_LSB00000,
OPERAND_SIMM16,
OPERAND_SIMM16_NONZERO,
+ OPERAND_SIMM20,
OPERAND_SIMM20_LI,
OPERAND_SIMM26,
OPERAND_CLUI_IMM,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 66e1b18f37392..d8da44247b25f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1730,6 +1730,12 @@ def HasVendorXSMTVDot
AssemblerPredicate<(all_of FeatureVendorXSMTVDot),
"'XSMTVDot' (SpacemiT Vector Dot Product Extension)">;
+def FeatureVendorXAIFET
+ : RISCVExtension<1, 0, "AI Foundry ET Extension", [FeatureStdExtF]>;
+def HasXAIFET : Predicate<"Subtarget->hasXAIFET()">,
+ AssemblerPredicate<(all_of FeatureVendorXAIFET),
+ "'XAIFET' (AI Foundry ET Extension)">;
+
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index fee1d1596ff5c..82bbe8d1fc748 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -146,6 +146,7 @@ def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>;
def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>;
def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>;
def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>;
+def OPC_0011111 : RISCVOpcode<"", 0b0011111>;
def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>;
def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>;
def OPC_CUSTOM_1 : RISCVOpcode<"CUSTOM_1", 0b0101011>;
@@ -153,6 +154,7 @@ def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>;
def OPC_OP : RISCVOpcode<"OP", 0b0110011>;
def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>;
def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>;
+def OPC_0111111 : RISCVOpcode<"", 0b0111111>;
def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>;
def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>;
def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>;
@@ -160,6 +162,7 @@ def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>;
def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>;
def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>;
def OPC_CUSTOM_2 : RISCVOpcode<"CUSTOM_2", 0b1011011>;
+def OPC_1011111 : RISCVOpcode<"", 0b1011111>;
def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>;
def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td
new file mode 100644
index 0000000000000..e800f12a7249c
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td
@@ -0,0 +1,265 @@
+//===-- RISCVInstrFormatXAIF.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction formats for the AI Foundry ET extensions, formerly known as the
+// ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+// https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+//===----------------------------------------------------------------------===//
+
+// Opcodes used by the ET extensions (referencing RISCVOpcode records defined in
+// RISCVInstrFormats.td)
+defvar OPC_ET_MEM_PS = OPC_CUSTOM_0;
+defvar OPC_ET_IMM_PS = OPC_0011111;
+defvar OPC_ET_IMM10_PI = OPC_0111111;
+defvar OPC_ET_OP3_PS = OPC_CUSTOM_2;
+defvar OPC_ET_IMM_PI = OPC_1011111;
+defvar OPC_ET_CVT_PS = OPC_OP_VE;
+defvar OPC_ET_OP_PS = OPC_CUSTOM_3;
+
+// Example: AIF.FSWIZZ.PS
+class RVInstET1<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<8> imm;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = imm{7-3};
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = imm{2-0};
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FADDI.PS
+class RVInstET2<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<10> imm;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-27} = imm{9-5};
+ let Inst{26-25} = 0b10;
+ let Inst{24-20} = imm{4-0};
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FADD.PS
+class RVInstET3<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<3> rm;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = rm;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FMADD.PS
+class RVInstET4<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<5> rs3;
+ bits<3> rm;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = funct2;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = rm;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FMVZ.X.PS
+class RVInstET5<bits<7> funct7, bits<3> funct3,
+ RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<3> idx;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-23} = 0;
+ let Inst{22-20} = idx;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FSLLI.PS
+class RVInstET6<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> imm;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-25} = 0b0100111;
+ let Inst{24-20} = imm;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FROUND.P
+class RVInstET7<RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs1;
+ bits<3> rm;
+ bits<5> rd;
+
+ let Inst{31-20} = 0b010110000001;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = rm;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MOV.M.X
+class RVInstET8<RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<8> imm;
+ bits<5> rs1;
+ bits<3> rd;
+
+ let Inst{31-25} = 0b0101011;
+ let Inst{24-20} = imm{7-3};
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = imm{2-0};
+ let Inst{11-10} = 0b00;
+ let Inst{9-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MASKAND
+class RVInstET9<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<3> rs2;
+ bits<3> rs1;
+ bits<3> rd;
+
+ let Inst{31-25} = 0b0110011;
+ let Inst{24-23} = 0b00;
+ let Inst{22-20} = rs2;
+ let Inst{19-18} = 0b00;
+ let Inst{17-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-10} = 0b00;
+ let Inst{9-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MASKPOPC
+class RVInstET10<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<3> rs1;
+ bits<5> rd;
+
+ let Inst{31-27} = 0b01010;
+ let Inst{26-25} = funct2;
+ let Inst{24-18} = 0b0000000;
+ let Inst{17-15} = rs1;
+ let Inst{14-12} = 0b000;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MASKPOPC.RAST
+class RVInstET11<RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<4> imm;
+ bits<3> rs2;
+ bits<3> rs1;
+ bits<5> rd;
+
+ let Inst{31-25} = 0b0101111;
+ let Inst{24-23} = imm{3-2};
+ let Inst{22-20} = rs2;
+ let Inst{19-18} = imm{1-0};
+ let Inst{17-15} = rs1;
+ let Inst{14-12} = 0b000;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FSCW.PS
+class RVInstET12<bits<7> funct7, bits<3> funct3,
+ RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<5> rs3;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rs3;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.SBG
+class RVInstET13<bits<7> funct7, bits<3> funct3,
+ RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs1;
+ bits<5> rs2;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = 0b00000;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FSWL.PS
+class RVInstET14<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> fs3;
+ bits<5> rs1;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = 0b00000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = fs3;
+ let Inst{6-0} = opcode.Value;
+}
+
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 708414496f4b6..264e3da6afd33 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -625,6 +625,7 @@ def LeadingOnesWMask : ImmLeaf<XLenVT, [{
include "RISCVInstrFormats.td"
include "RISCVInstrFormatsC.td"
include "RISCVInstrFormatsV.td"
+include "RISCVInstrFormatsXAIF.td"
//===----------------------------------------------------------------------===//
// Instruction Class Templates
@@ -2382,6 +2383,7 @@ include "RISCVInstrInfoXMips.td"
include "RISCVInstrInfoXRivos.td"
include "RISCVInstrInfoXAndes.td"
include "RISCVInstrInfoXSpacemiT.td"
+include "RISCVInstrInfoXAIF.td"
//===----------------------------------------------------------------------===//
// Global ISel
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
new file mode 100644
index 0000000000000..596f1251e8aa2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
@@ -0,0 +1,787 @@
+//===-- RISCVInstrInfoXAIF.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction definitions for the AI Foundry ET extensions, formerly known as
+// the ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+// https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+// The following conventions are used in this file:
+//
+// 1. Specific instruction formats are named
+//
+// RVInstET<#>
+//
+// where <#> is a number from 1 to 14. Each number corresponds to a template
+// fitting a given instruction and other similar ones, as defined in
+// RISCVInstrFormatsXAIF.td
+//
+// 2. Each masked vector instruction <INST> is handled with an ETOps<Operands>
+// multiclass defining one instruction and two pseudo instructions:
+//
+// - <INST>: regular masked vector instructions as described in the manual,
+// implicitly using M0 register for masking out destination register
+// elements.
+//
+// - <INST>_EX: masked vector pseudo-instruction explictly accepting M0 as
+// its last operand, as opposed to <INST> where the register dependency
+// is just implicit. In addition to the explicit operands accepted by
+// <INST>, we must add m0 as the last operand.
+//
+// The purpose of this instruction variant is to explicitly mark the
+// dependency on the m0 register contents in MIR (Machine Instruction
+// Representation).
+//
+// - <INST>_PASSTHRU_EX: Similar to <INST_EX>, but also making explicit the
+// dependency on the previous destination register contents. In addition
+// to the explicit operands accepted by <INST_EX>, we must add the
+// destination register as the first operand.
+//
+// Destination and first source operands are constrained to be assigned
+// the same physical register during register allocation.
+//
+// This variant should be the choice during instruction selection for
+// cases when m0 is not guaranteed to be all ones.
+//
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XAIF", Predicates = [HasXAIFET] in {
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+ def AIF_FLQ2 : RVInstI<0b101, OPC_LOAD_FP,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "aif.flq2", "$rd, ${imm12}(${rs1})">;
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+ def AIF_FSQ2 : RVInstS<0b101, OPC_STORE_FP,
+ (outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1),
+ "aif.fsq2", "$rs2, ${imm12}(${rs1})">;
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def AIF_FLW_PS : RVInstI<0b010, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "aif.flw.ps", "$rd, ${imm12}(${rs1})">;
+ def AIF_FLW_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "aif.flw.ps", "$rd, ${imm12}(${rs1}), $m0">;
+ def AIF_FLW_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "aif.flw.ps", "$rd, ${imm12}(${rs1}), $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ def AIF_FSW_PS : RVInstS<0b110, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1),
+ "aif.fsw.ps", "$rs2, ${imm12}(${rs1})">;
+ def AIF_FSW_PS_EX : Pseudo<(outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1, MR0:$m0),
+ [], "aif.fsw.ps", "$rs2, ${imm12}(${rs1}), $m0">;
+ }
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def AIF_FBC_PS : RVInstI<0b000, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "aif.fbc.ps", "$rd, ${imm12}(${rs1})">;
+ def AIF_FBC_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "aif.fbc.ps", "$rd, ${imm12}(${rs1}), $m0">;
+ }
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ def AIF_FBCX_PS : RVInstI<0b011, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins GPR:$rs1),
+ "aif.fbcx.ps", "$rd, ${rs1}"> {
+ let imm12 = 0;
+ }
+ def AIF_FBCX_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, MR0:$m0), [],
+ "aif.fbcx.ps", "$rd, ${rs1}, $m0">;
+ def AIF_FBCX_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, GPR:$rs1, MR0:$m0), [],
+ "aif.fbcx.ps", "$rd, ${rs1}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ def AIF_FBCI_PS : RVInstU<OPC_ET_IMM_PS,
+ (outs FPR256:$rd),
+ (ins uimm20_lui:$imm20),
+ "aif.fbci.ps", "$rd, $imm20"> ;
+
+ def AIF_FBCI_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.ps", "$rd, $imm20, $m0">;
+ def AIF_FBCI_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.ps", "$rd, $imm20, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ multiclass ETOpsRdF1R2G<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ defm AIF_FGW_PS : ETOpsRdF1R2G<0b0110000, "aif.fgw.ps">;
+ defm AIF_FGH_PS : ETOpsRdF1R2G<0b0101000, "aif.fgh.ps">;
+ defm AIF_FGB_PS : ETOpsRdF1R2G<0b0100100, "aif.fgb.ps">;
+ }
+
+ multiclass ETOpsR3R1R2<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstET12<funct7, funct3, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rs3, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rs3, ${rs1}, ${rs2}, $m0">;
+ }
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ defm AIF_FSCW_PS : ETOpsR3R1R2<0b1110000, 0b001, "aif.fscw.ps">;
+ defm AIF_FSCH_PS : ETOpsR3R1R2<0b1101000, 0b001, "aif.fsch.ps">;
+ defm AIF_FSCB_PS : ETOpsR3R1R2<0b1100100, 0b001, "aif.fscb.ps">;
+ }
+
+ multiclass ETOpsRdR1R2Rm<bits<7> funct7, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstET3<funct7, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, frmarg:$rm),
+ opcodestr, "$rd, $rs1, $rs2$rm">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2$rm, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, FPR256:$rs2, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2$rm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FADD_PS : ETOpsRdR1R2Rm<0b0000000, OPC_ET_OP_PS, "aif.fadd.ps">;
+ defm AIF_FSUB_PS : ETOpsRdR1R2Rm<0b0000100, OPC_ET_OP_PS, "aif.fsub.ps">;
+ defm AIF_FMUL_PS : ETOpsRdR1R2Rm<0b0001000, OPC_ET_OP_PS, "aif.fmul.ps">;
+ defm AIF_FDIV_PS : ETOpsRdR1R2Rm<0b0001100, OPC_ET_OP_PS, "aif.fdiv.ps">;
+
+ multiclass ETOpsRdR1R2<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2),
+ opcodestr, "$rd, $rs1, $rs2">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, FPR256:$rs2, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FMIN_PS : ETOpsRdR1R2<0b0010100, 0b000, OPC_ET_OP_PS, "aif.fmin.ps">;
+ defm AIF_FMAX_PS : ETOpsRdR1R2<0b0010100, 0b001, OPC_ET_OP_PS, "aif.fmax.ps">;
+
+ multiclass ETOpsRdR1R2R3Rm<bits<2> funct2, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstET4<funct2, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, FPR256:$rs3, frmarg:$rm),
+ opcodestr, "$rd, $rs1, $rs2, $rs3$rm">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1,
+ FPR256:$rs2, FPR256:$rs3, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $rs3$rm, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1,
+ FPR256:$rs2, FPR256:$rs3, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $rs3$rm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FMADD_PS : ETOpsRdR1R2R3Rm<0b00, OPC_ET_OP3_PS, "aif.fmadd.ps">;
+ defm AIF_FMSUB_PS : ETOpsRdR1R2R3Rm<0b01, OPC_ET_OP3_PS, "aif.fmsub.ps">;
+ defm AIF_FNMSUB_PS : ETOpsRdR1R2R3Rm<0b10, OPC_ET_OP3_PS, "aif.fnmsub.ps">;
+ defm AIF_FNMADD_PS : ETOpsRdR1R2R3Rm<0b11, OPC_ET_OP3_PS, "aif.fnmadd.ps">;
+
+ def AIF_FCMOV_PS : RVInstET4<0b10, OPC_ET_IMM10_PI,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, FPR256:$rs3),
+ "aif.fcmov.ps", "$rd, $rs1, $rs2, $rs3"> {
+ let rm = 0b010;
+ }
+
+ def AIF_FCMOV_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2,
+ FPR256:$rs3, MR0:$m0), [],
+ "aif.fcmov.ps", "$rd, $rs1, $rs2, $rs3, $m0">;
+ def AIF_FCMOV_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, FPR256:$rs2,
+ FPR256:$rs3, MR0:$m0), [],
+ "aif.fcmov.ps", "$rd, $rs1, $rs2, $rs3, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ def AIF_FSWIZZ_PS : RVInstET1<0b1110011, OPC_ET_OP_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, uimm8:$imm),
+ "aif.fswizz.ps", "$rd, $rs1, $imm">;
+ def AIF_FSWIZZ_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, uimm8:$imm, MR0:$m0),
+ [], "aif.fswizz.ps", "$rd, $rs1, $imm, $m0">;
+ def AIF_FSWIZZ_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, uimm8:$imm, MR0:$m0),
+ [], "aif.fswizz.ps", "$rd, $rs1, $imm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ multiclass ETOpsRdR1Rm<bits<7> funct7, bits<5> funct1, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstET3<funct7, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm),
+ opcodestr, "$rd, $rs1$rm"> {
+ let rs2 = funct1;
+ }
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1$rm, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1$rm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FCVT_PW_PS : ETOpsRdR1Rm<0b1100000, 0, OPC_ET_OP_PS, "aif.fcvt.pw.ps">;
+ defm AIF_FCVT_PWU_PS : ETOpsRdR1Rm<0b1100000, 1, OPC_ET_OP_PS, "aif.fcvt.pwu.ps">;
+ defm AIF_FCVT_PS_PW : ETOpsRdR1Rm<0b1101000, 0, OPC_ET_OP_PS, "aif.fcvt.ps.pw">;
+ defm AIF_FCVT_PS_PWU : ETOpsRdR1Rm<0b1101000, 1, OPC_ET_OP_PS, "aif.fcvt.ps.pwu">;
+
+ class ETOpsRdR1Idx<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr> :
+ RVInstET5<funct7, funct3, opcode,
+ (outs GPR:$rd),
+ (ins FPR256:$rs1, uimm3:$idx),
+ opcodestr, "$rd, $rs1, $idx">;
+
+ def AIF_FMVZ_X_PS : ETOpsRdR1Idx<0b1110000, 0b000, OPC_ET_OP_PS, "aif.fmvz.x.ps">;
+ // no _EX variant
+ def AIF_FMVS_X_PS : ETOpsRdR1Idx<0b1110000, 0b010, OPC_ET_OP_PS, "aif.fmvs.x.ps">;
+ // no _EX variant
+
+ defm AIF_FSGNJN_PS : ETOpsRdR1R2<0b0010000, 0b001, OPC_ET_OP_PS, "aif.fsgnjn.ps">;
+ defm AIF_FSGNJ_PS : ETOpsRdR1R2<0b0010000, 0b000, OPC_ET_OP_PS, "aif.fsgnj.ps">;
+ defm AIF_FSGNJX_PS : ETOpsRdR1R2<0b0010000, 0b010, OPC_ET_OP_PS, "aif.fsgnjx.ps">;
+ defm AIF_FLE_PS : ETOpsRdR1R2<0b1010000, 0b000, OPC_ET_OP_PS, "aif.fle.ps">;
+ defm AIF_FLT_PS : ETOpsRdR1R2<0b1010000, 0b001, OPC_ET_OP_PS, "aif.flt.ps">;
+ defm AIF_FEQ_PS : ETOpsRdR1R2<0b1010000, 0b010, OPC_ET_OP_PS, "aif.feq.ps">;
+
+ multiclass ETOpsMdR1R2<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs MR:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2),
+ opcodestr, "$rd, $rs1, $rs2">;
+ def _EX : Pseudo<(outs MR:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $rs2, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs MR:$rd),
+ (ins MR:$in, FPR256:$rs1, FPR256:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $rs2, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FLEM_PS : ETOpsMdR1R2<0b1010000, 0b100, OPC_ET_OP_PS, "aif.flem.ps">;
+ defm AIF_FLTM_PS : ETOpsMdR1R2<0b1010000, 0b101, OPC_ET_OP_PS, "aif.fltm.ps">;
+ defm AIF_FEQM_PS : ETOpsMdR1R2<0b1010000, 0b110, OPC_ET_OP_PS, "aif.feqm.ps">;
+
+ multiclass ETOpsRdR1<bits<7> funct7, bits<5> funct5, bits<3> funct3,
+ RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = funct5;
+ }
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FCLASS_PS : ETOpsRdR1<0b1110000, 0b00000, 0b001, OPC_ET_OP_PS, "aif.fclass.ps">;
+
+ multiclass ETOpsCvt<bits<7> funct7, bits<5> funct5, string opcodestr> {
+ defm "" : ETOpsRdR1<funct7, funct5, 0b000,
+ OPC_ET_OP_PS, opcodestr>;
+ }
+
+ defm AIF_FCVT_PS_F10 : ETOpsCvt<0b1101000, 0b01000, "aif.fcvt.ps.f10">;
+ defm AIF_FCVT_PS_F11 : ETOpsCvt<0b1101000, 0b01001, "aif.fcvt.ps.f11">;
+ defm AIF_FCVT_PS_F16 : ETOpsCvt<0b1101000, 0b01010, "aif.fcvt.ps.f16">;
+ defm AIF_FCVT_PS_UN24 : ETOpsCvt<0b1101000, 0b10000, "aif.fcvt.ps.un24">;
+ defm AIF_FCVT_PS_UN16 : ETOpsCvt<0b1101000, 0b10001, "aif.fcvt.ps.un16">;
+ defm AIF_FCVT_PS_UN10 : ETOpsCvt<0b1101000, 0b10010, "aif.fcvt.ps.un10">;
+ defm AIF_FCVT_PS_UN8 : ETOpsCvt<0b1101000, 0b10011, "aif.fcvt.ps.un8">;
+ defm AIF_FCVT_PS_UN2 : ETOpsCvt<0b1101000, 0b10111, "aif.fcvt.ps.un2">;
+ defm AIF_FCVT_PS_SN16 : ETOpsCvt<0b1101000, 0b11001, "aif.fcvt.ps.sn16">;
+ defm AIF_FCVT_PS_SN8 : ETOpsCvt<0b1101000, 0b11011, "aif.fcvt.ps.sn8">;
+ defm AIF_FCVT_F11_PS : ETOpsCvt<0b1101100, 0b01000, "aif.fcvt.f11.ps">;
+ defm AIF_FCVT_F16_PS : ETOpsCvt<0b1101100, 0b01001, "aif.fcvt.f16.ps">;
+ defm AIF_FCVT_F10_PS : ETOpsCvt<0b1101100, 0b01011, "aif.fcvt.f10.ps">;
+ defm AIF_FCVT_UN24_PS : ETOpsCvt<0b1101100, 0b10000, "aif.fcvt.un24.ps">;
+ defm AIF_FCVT_UN16_PS : ETOpsCvt<0b1101100, 0b10001, "aif.fcvt.un16.ps">;
+ defm AIF_FCVT_UN10_PS : ETOpsCvt<0b1101100, 0b10010, "aif.fcvt.un10.ps">;
+ defm AIF_FCVT_UN8_PS : ETOpsCvt<0b1101100, 0b10011, "aif.fcvt.un8.ps">;
+ defm AIF_FCVT_UN2_PS : ETOpsCvt<0b1101100, 0b10111, "aif.fcvt.un2.ps">;
+ defm AIF_FCVT_SN16_PS : ETOpsCvt<0b1101100, 0b11001, "aif.fcvt.sn16.ps">;
+ defm AIF_FCVT_SN8_PS : ETOpsCvt<0b1101100, 0b11011, "aif.fcvt.sn8.ps">;
+
+ def AIF_FBCI_PI : RVInstU<OPC_ET_IMM_PI,
+ (outs FPR256:$rd),
+ (ins uimm20_lui:$imm20),
+ "aif.fbci.pi", "$rd, ${imm20}">;
+ def AIF_FBCI_PI_EX : Pseudo<(outs FPR256:$rd),
+ (ins uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.pi", "$rd, ${imm20}, $m0">;
+ def AIF_FBCI_PI_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.pi", "$rd, ${imm20}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ defm AIF_FADD_PI : ETOpsRdR1R2<0b0000011, 0b000, OPC_ET_OP_PS, "aif.fadd.pi">;
+ defm AIF_FSUB_PI : ETOpsRdR1R2<0b0000111, 0b000, OPC_ET_OP_PS, "aif.fsub.pi">;
+ defm AIF_FMUL_PI : ETOpsRdR1R2<0b0001011, 0b000, OPC_ET_OP_PS, "aif.fmul.pi">;
+ defm AIF_FMULH_PI : ETOpsRdR1R2<0b0001011, 0b001, OPC_ET_OP_PS, "aif.fmulh.pi">;
+ defm AIF_FMULHU_PI : ETOpsRdR1R2<0b0001011, 0b010, OPC_ET_OP_PS, "aif.fmulhu.pi">;
+ defm AIF_FDIV_PI : ETOpsRdR1R2<0b0001111, 0b000, OPC_ET_OP_PS, "aif.fdiv.pi">;
+ defm AIF_FDIVU_PI : ETOpsRdR1R2<0b0001111, 0b001, OPC_ET_OP_PS, "aif.fdivu.pi">;
+ defm AIF_FREM_PI : ETOpsRdR1R2<0b0001111, 0b010, OPC_ET_OP_PS, "aif.frem.pi">;
+ defm AIF_FREMU_PI : ETOpsRdR1R2<0b0001111, 0b011, OPC_ET_OP_PS, "aif.fremu.pi">;
+ defm AIF_FMIN_PI : ETOpsRdR1R2<0b0010111, 0b000, OPC_ET_OP_PS, "aif.fmin.pi">;
+ defm AIF_FMAX_PI : ETOpsRdR1R2<0b0010111, 0b001, OPC_ET_OP_PS, "aif.fmax.pi">;
+ defm AIF_FMINU_PI : ETOpsRdR1R2<0b0010111, 0b010, OPC_ET_OP_PS, "aif.fminu.pi">;
+ defm AIF_FMAXU_PI : ETOpsRdR1R2<0b0010111, 0b011, OPC_ET_OP_PS, "aif.fmaxu.pi">;
+
+ defm AIF_FLTM_PI : ETOpsMdR1R2<0b0011111, 0b000, OPC_ET_OP_PS, "aif.fltm.pi">;
+
+ defm AIF_FAND_PI : ETOpsRdR1R2<0b0000011, 0b111, OPC_ET_OP_PS, "aif.fand.pi">;
+ defm AIF_FOR_PI : ETOpsRdR1R2<0b0000011, 0b110, OPC_ET_OP_PS, "aif.for.pi">;
+ defm AIF_FNOT_PI : ETOpsRdR1<0b0000011, 0b00000, 0b010, OPC_ET_OP_PS, "aif.fnot.pi">;
+ defm AIF_FXOR_PI : ETOpsRdR1R2<0b0000011, 0b100, OPC_ET_OP_PS, "aif.fxor.pi">;
+ defm AIF_FSLL_PI : ETOpsRdR1R2<0b0000011, 0b001, OPC_ET_OP_PS, "aif.fsll.pi">;
+ defm AIF_FSRL_PI : ETOpsRdR1R2<0b0000011, 0b101, OPC_ET_OP_PS, "aif.fsrl.pi">;
+ defm AIF_FSRA_PI : ETOpsRdR1R2<0b0000111, 0b101, OPC_ET_OP_PS, "aif.fsra.pi">;
+ defm AIF_FLE_PI : ETOpsRdR1R2<0b1010011, 0b000, OPC_ET_OP_PS, "aif.fle.pi">;
+ defm AIF_FLT_PI : ETOpsRdR1R2<0b1010011, 0b001, OPC_ET_OP_PS, "aif.flt.pi">;
+ defm AIF_FEQ_PI : ETOpsRdR1R2<0b1010011, 0b010, OPC_ET_OP_PS, "aif.feq.pi">;
+ defm AIF_FLTU_PI : ETOpsRdR1R2<0b1010011, 0b011, OPC_ET_OP_PS, "aif.fltu.pi">;
+
+ multiclass ETOpsMdR1<bits<7> funct7, bits<3> funct3,
+ RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs MR:$rd),
+ (ins FPR256:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = 0;
+ }
+ def _EX : Pseudo<(outs MR:$rd),
+ (ins FPR256:$rs1, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs MR:$rd),
+ (ins MR:$in, FPR256:$rs1, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FSETM_PI : ETOpsMdR1<0b1010011, 0b100, OPC_ET_OP_PS, "aif.fsetm.pi">;
+
+ multiclass ETOpsRdR1I10<bits<3> funct3, RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstET2<funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, simm10:$imm),
+ opcodestr, "$rd, $rs1, ${imm}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, simm10:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, simm10:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FADDI_PI : ETOpsRdR1I10<0b000, OPC_ET_IMM10_PI, "aif.faddi.pi">;
+ defm AIF_FANDI_PI : ETOpsRdR1I10<0b001, OPC_ET_IMM10_PI, "aif.fandi.pi">;
+
+ multiclass ETOpsRdR1I5<bits<3> funct3, RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstET6<funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, uimm5:$imm),
+ opcodestr, "$rd, $rs1, ${imm}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, uimm5:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, uimm5:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm AIF_FSLLI_PI : ETOpsRdR1I5<0b001, OPC_ET_OP_PS, "aif.fslli.pi">;
+ defm AIF_FSRLI_PI : ETOpsRdR1I5<0b101, OPC_ET_OP_PS, "aif.fsrli.pi">;
+ defm AIF_FSRAI_PI : ETOpsRdR1I5<0b111, OPC_ET_OP_PS, "aif.fsrai.pi">;
+
+ defm AIF_FSIN_PS : ETOpsRdR1<0b0101100, 0b00110, 0b000, OPC_ET_OP_PS, "aif.fsin.ps">;
+ defm AIF_FEXP_PS : ETOpsRdR1<0b0101100, 0b00100, 0b000, OPC_ET_OP_PS, "aif.fexp.ps">;
+ defm AIF_FLOG_PS : ETOpsRdR1<0b0101100, 0b00011, 0b000, OPC_ET_OP_PS, "aif.flog.ps">;
+ defm AIF_FFRC_PS : ETOpsRdR1<0b0101100, 0b00010, 0b000, OPC_ET_OP_PS, "aif.ffrc.ps">;
+
+ def AIF_FROUND_PS : RVInstET7<OPC_ET_OP_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm),
+ "aif.fround.ps", "$rd, $rs1$rm">;
+ def AIF_FROUND_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm, MR0:$m0),
+ [], "aif.fround.ps", "$rd, $rs1$rm, $m0">;
+
+ defm AIF_FSQRT_PS : ETOpsRdR1<0b0101100, 0b00000, 0b000, OPC_ET_OP_PS, "aif.fsqrt.ps">;
+ defm AIF_FRCP_PS : ETOpsRdR1<0b0101100, 0b00111, 0b000, OPC_ET_OP_PS, "aif.frcp.ps">;
+ defm AIF_FRSQ_PS : ETOpsRdR1<0b0101100, 0b01000, 0b000, OPC_ET_OP_PS, "aif.frsq.ps">;
+
+ defm AIF_CUBEFACE_PS : ETOpsRdR1R2<0b1000100, 0b000, OPC_ET_OP_PS, "aif.cubeface.ps">;
+ defm AIF_CUBEFACEIDX_PS : ETOpsRdR1R2<0b1000100, 0b001, OPC_ET_OP_PS, "aif.cubefaceidx.ps">;
+ defm AIF_CUBESGNSC_PS : ETOpsRdR1R2<0b1000100, 0b010, OPC_ET_OP_PS, "aif.cubesgnsc.ps">;
+ defm AIF_CUBESGNTC_PS : ETOpsRdR1R2<0b1000100, 0b011, OPC_ET_OP_PS, "aif.cubesgntc.ps">;
+
+ def AIF_PACKB : ALUW_rr<0b1000000, 0b110, "aif.packb">;
+ def AIF_BITMIXB : ALUW_rr<0b1000000, 0b111, "aif.bitmixb">;
+
+ def AIF_MOV_M_X : RVInstET8<OPC_ET_OP_PS,
+ (outs MR:$rd),
+ (ins GPR:$rs1, uimm8:$imm),
+ "aif.mov.m.x", "$rd, $rs1, $imm">;
+ def AIF_MOVA_X_M : RVInstR<0b1101011, 0b000, OPC_ET_OP_PS,
+ (outs GPR:$rd),
+ (ins),
+ "aif.mova.x.m", "$rd"> {
+ let rs1 = 0;
+ let rs2 = 0;
+ }
+
+ def AIF_MOVA_M_X : RVInstR<0b1101011, 0b001, OPC_ET_OP_PS,
+ (outs),
+ (ins GPR:$rs1),
+ "aif.mova.m.x", "$rs1"> {
+ let rd = 0;
+ let rs2 = 0;
+ }
+
+ class ETOpsMdM1M2<bits<3> funct3, string codestr> :
+ RVInstET9<funct3, OPC_ET_OP_PS, (outs MR:$rd),
+ (ins MR:$rs1, MR:$rs2), codestr, "$rd, $rs1, $rs2">;
+
+ def AIF_MASKAND : ETOpsMdM1M2<0b111, "aif.maskand">;
+ def AIF_MASKOR : ETOpsMdM1M2<0b110, "aif.maskor">;
+ def AIF_MASKNOT : RVInstET9<0b010, OPC_ET_OP_PS, (outs MR:$rd),
+ (ins MR:$rs1), "aif.masknot", "$rd, $rs1"> {
+ let rs2 = 0;
+ }
+ def AIF_MASKXOR : ETOpsMdM1M2<0b100, "aif.maskxor">;
+
+ class ETOpsRdM1<bits<2> funct2, string opcodestr> :
+ RVInstET10<funct2, OPC_ET_OP_PS, (outs GPR:$rd), (ins MR:$rs1),
+ opcodestr, "$rd, $rs1">;
+
+ def AIF_MASKPOPC : ETOpsRdM1<0b01, "aif.maskpopc">;
+ def AIF_MASKPOPCZ : ETOpsRdM1<0b10, "aif.maskpopcz">;
+
+ def AIF_MASKPOPC_ET_RAST :
+ RVInstET11<OPC_ET_OP_PS, (outs MR:$rd),
+ (ins MR:$rs1, MR:$rs2, uimm4:$imm),
+ "aif.maskpopc.rast", "$rd, $rs1, $rs2, $imm">;
+
+ defm AIF_FPACKREPB_PI :
+ ETOpsRdR1<0b0010011, 0b00000, 0b000, OPC_ET_OP_PS, "aif.fpackrepb.pi">;
+ defm AIF_FPACKREPH_PI :
+ ETOpsRdR1<0b0010011, 0b00000, 0b001, OPC_ET_OP_PS, "aif.fpackreph.pi">;
+
+ multiclass ETOpsRdR1R2G32<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins GPR:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, m0">;
+ }
+
+ let mayLoad = 1 in {
+ defm AIF_FG32W_PS : ETOpsRdR1R2G32<0b0010000, "aif.fg32w.ps">;
+ defm AIF_FG32H_PS : ETOpsRdR1R2G32<0b0001000, "aif.fg32h.ps">;
+ defm AIF_FG32B_PS : ETOpsRdR1R2G32<0b0000100, "aif.fg32b.ps">;
+ }
+
+ multiclass ETOpsR3R1R2SC32<bits<7> funct7, string opcodestr> {
+ def "" : RVInstET12<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs3, GPR:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rs3, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs),
+ (ins FPR256:$rs3, GPR:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rs3, ${rs1}, ${rs2}, $m0">;
+ }
+
+ let mayStore = 1 in {
+ defm AIF_FSC32W_PS : ETOpsR3R1R2SC32<0b1010000, "aif.fsc32w.ps">;
+ defm AIF_FSC32H_PS : ETOpsR3R1R2SC32<0b1001000, "aif.fsc32h.ps">;
+ defm AIF_FSC32B_PS : ETOpsR3R1R2SC32<0b1000100, "aif.fsc32b.ps">;
+ }
+
+ // Specialse FCMOVM has no implicit input since all of output
+ // is defined.
+ def AIF_FCMOVM_PS : RVInstR<0b0000000, 0b000, OPC_ET_CVT_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2),
+ "aif.fcmovm.ps", "$rd, $rs1, $rs2">;
+ def AIF_FCMOVM_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, MR0:$m0), [],
+ "aif.fcmovm.ps", "$rd, $rs1, $rs2, $m0">;
+
+ defm AIF_FRCP_FIX_RAST : ETOpsRdR1R2<0b0011000, 0b000, OPC_ET_OP_PS, "aif.frcp_fix.rast">;
+ defm AIF_FCVT_RAST_PS : ETOpsRdR1<0b1100000, 0b00010, 0b000, OPC_ET_OP_PS, "aif.fcvt.rast.ps">;
+ defm AIF_FCVT_PS_RAST : ETOpsRdR1<0b1101000, 0b00010, 0b000, OPC_ET_OP_PS, "aif.fcvt.ps.rast">;
+ defm AIF_FSAT8_PI : ETOpsRdR1<0b0000011, 0b00000, 0b011, OPC_ET_OP_PS, "aif.fsat8.pi">;
+ defm AIF_FSATU8_PI : ETOpsRdR1<0b0000011, 0b00001, 0b011, OPC_ET_OP_PS, "aif.fsatu8.pi">;
+
+ multiclass ETOpsFdR1<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7, 0b111, OPC_ET_MEM_PS,
+ (outs FPR256:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, (${rs1})"> {
+ let rs2 = 0;
+ }
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, MR0:$m0), [],
+ opcodestr, "$rd, (${rs1}), $m0">;
+ }
+
+ let mayLoad = 1 in {
+ defm AIF_FLWL_PS : ETOpsFdR1<0b0001000, "aif.flwl.ps">;
+ defm AIF_FLWG_PS : ETOpsFdR1<0b0001001, "aif.flwg.ps">;
+ }
+
+ multiclass ETOpsFs3Rs1<bits<7> funct7, string opcodestr> {
+ def "" : RVInstET14<funct7, 0b111, OPC_ET_MEM_PS,
+ (outs), (ins FPR256:$fs3, GPR:$rs1),
+ opcodestr, "$fs3, (${rs1})">;
+ def _EX : Pseudo<(outs), (ins FPR256:$fs3, GPR:$rs1, MR0:$m0), [],
+ opcodestr, "$fs3, (${rs1}), $m0">;
+ }
+
+ let mayStore = 1 in {
+ defm AIF_FSWL_PS : ETOpsFs3Rs1<0b0101000, "aif.fswl.ps">;
+ defm AIF_FSWG_PS : ETOpsFs3Rs1<0b0101001, "aif.fswg.ps">;
+ }
+
+ multiclass ETOpsRdR1R2FG<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstR<funct7, funct3, OPC_ET_MEM_PS, (outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2), opcodestr,
+ "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [], opcodestr,
+ "$rd, ${rs1}, ${rs2}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [], opcodestr,
+ "$rd, ${rs1}, ${rs2}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ let mayLoad = 1 in {
+ defm AIF_FGBL_PS : ETOpsRdR1R2FG<0b1000000, 0b111, "aif.fgbl.ps">;
+ defm AIF_FGHL_PS : ETOpsRdR1R2FG<0b1000100, 0b111, "aif.fghl.ps">;
+ defm AIF_FGWL_PS : ETOpsRdR1R2FG<0b1001000, 0b111, "aif.fgwl.ps">;
+ }
+
+ multiclass ETOpsR3R1R2FS<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstET12<funct7, funct3, OPC_ET_MEM_PS, (outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2), opcodestr,
+ "${rs3}, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0),
+ [], opcodestr,
+ "${rs3}, ${rs1}, ${rs2}, $m0">;
+ }
+
+ let mayStore = 1 in {
+ defm AIF_FSCBL_PS : ETOpsR3R1R2FS<0b1100000, 0b111, "aif.fscbl.ps">;
+ defm AIF_FSCHL_PS : ETOpsR3R1R2FS<0b1100100, 0b111, "aif.fschl.ps">;
+ defm AIF_FSCWL_PS : ETOpsR3R1R2FS<0b1101000, 0b111, "aif.fscwl.ps">;
+ }
+
+ let mayLoad = 1 in {
+ defm AIF_FGBG_PS : ETOpsRdR1R2FG<0b1000001, 0b111, "aif.fgbg.ps">;
+ defm AIF_FGHG_PS : ETOpsRdR1R2FG<0b1000101, 0b111, "aif.fghg.ps">;
+ defm AIF_FGWG_PS : ETOpsRdR1R2FG<0b1001001, 0b111, "aif.fgwg.ps">;
+ }
+
+ let mayStore = 1 in {
+ defm AIF_FSCBG_PS : ETOpsR3R1R2FS<0b1100001, 0b111, "aif.fscbg.ps">;
+ defm AIF_FSCHG_PS : ETOpsR3R1R2FS<0b1100101, 0b111, "aif.fschg.ps">;
+ defm AIF_FSCWG_PS : ETOpsR3R1R2FS<0b1101001, 0b111, "aif.fscwg.ps">;
+ }
+
+ let mayLoad = 1, mayStore = 1 in {
+ defm AIF_FAMOADDL_PI : ETOpsRdR1R2FG<0b0000011, 0b100, "aif.famoaddl.pi">;
+ defm AIF_FAMOSWAPL_PI : ETOpsRdR1R2FG<0b0000111, 0b100, "aif.famoswapl.pi">;
+ defm AIF_FAMOANDL_PI : ETOpsRdR1R2FG<0b0001011, 0b100, "aif.famoandl.pi">;
+ defm AIF_FAMOORL_PI : ETOpsRdR1R2FG<0b0001111, 0b100, "aif.famoorl.pi">;
+ defm AIF_FAMOXORL_PI : ETOpsRdR1R2FG<0b0010011, 0b100, "aif.famoxorl.pi">;
+ defm AIF_FAMOMINL_PI : ETOpsRdR1R2FG<0b0010111, 0b100, "aif.famominl.pi">;
+ defm AIF_FAMOMAXL_PI : ETOpsRdR1R2FG<0b0011011, 0b100, "aif.famomaxl.pi">;
+ defm AIF_FAMOMINUL_PI : ETOpsRdR1R2FG<0b0011111, 0b100, "aif.famominul.pi">;
+ defm AIF_FAMOMAXUL_PI : ETOpsRdR1R2FG<0b0100011, 0b100, "aif.famomaxul.pi">;
+ defm AIF_FAMOMINL_PS : ETOpsRdR1R2FG<0b0011000, 0b100, "aif.famominl.ps">;
+ defm AIF_FAMOMAXL_PS : ETOpsRdR1R2FG<0b0010100, 0b100, "aif.famomaxl.ps">;
+
+ defm AIF_FAMOADDG_PI : ETOpsRdR1R2FG<0b1000011, 0b100, "aif.famoaddg.pi">;
+ defm AIF_FAMOSWAPG_PI : ETOpsRdR1R2FG<0b1000111, 0b100, "aif.famoswapg.pi">;
+ defm AIF_FAMOANDG_PI : ETOpsRdR1R2FG<0b1001011, 0b100, "aif.famoandg.pi">;
+ defm AIF_FAMOORG_PI : ETOpsRdR1R2FG<0b1001111, 0b100, "aif.famoorg.pi">;
+ defm AIF_FAMOXORG_PI : ETOpsRdR1R2FG<0b1010011, 0b100, "aif.famoxorg.pi">;
+ defm AIF_FAMOMING_PI : ETOpsRdR1R2FG<0b1010111, 0b100, "aif.famoming.pi">;
+ defm AIF_FAMOMAXG_PI : ETOpsRdR1R2FG<0b1011011, 0b100, "aif.famomaxg.pi">;
+ defm AIF_FAMOMINUG_PI : ETOpsRdR1R2FG<0b1011111, 0b100, "aif.famominug.pi">;
+ defm AIF_FAMOMAXUG_PI : ETOpsRdR1R2FG<0b1100011, 0b100, "aif.famomaxug.pi">;
+ defm AIF_FAMOMING_PS : ETOpsRdR1R2FG<0b1011000, 0b100, "aif.famoming.ps">;
+ defm AIF_FAMOMAXG_PS : ETOpsRdR1R2FG<0b1010100, 0b100, "aif.famomaxg.ps">;
+ }
+
+ class ETOpsR2R1<bits<7> funct7, bits<3> funct3, string opcodestr> :
+ RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd),
+ (ins GPR:$rs2, GPRMemZeroOffset:$rs1), opcodestr,
+ "${rd}, ${rs2}, ${rs1}">;
+
+ let mayLoad = 1, mayStore = 1 in {
+ def AIF_AMOSWAPL_W : ETOpsR2R1<0b0000100, 0b010, "aif.amoswapl.w">;
+ def AIF_AMOADDL_W : ETOpsR2R1<0b0000000, 0b010, "aif.amoaddl.w">;
+ def AIF_AMOXORL_W : ETOpsR2R1<0b0010000, 0b010, "aif.amoxorl.w">;
+ def AIF_AMOANDL_W : ETOpsR2R1<0b0110000, 0b010, "aif.amoandl.w">;
+ def AIF_AMOORL_W : ETOpsR2R1<0b0100000, 0b010, "aif.amoorl.w">;
+ def AIF_AMOMINL_W : ETOpsR2R1<0b1000000, 0b010, "aif.amominl.w">;
+ def AIF_AMOMAXL_W : ETOpsR2R1<0b1010000, 0b010, "aif.amomaxl.w">;
+ def AIF_AMOMINUL_W : ETOpsR2R1<0b1100000, 0b010, "aif.amominul.w">;
+ def AIF_AMOMAXUL_W : ETOpsR2R1<0b1110000, 0b010, "aif.amomaxul.w">;
+ def AIF_AMOCMPSWAPL_W : ETOpsR2R1<0b1111000, 0b010, "aif.amocmpswapl.w">;
+
+ def AIF_AMOSWAPG_W : ETOpsR2R1<0b0000101, 0b010, "aif.amoswapg.w">;
+ def AIF_AMOADDG_W : ETOpsR2R1<0b0000001, 0b010, "aif.amoaddg.w">;
+ def AIF_AMOXORG_W : ETOpsR2R1<0b0010001, 0b010, "aif.amoxorg.w">;
+ def AIF_AMOANDG_W : ETOpsR2R1<0b0110001, 0b010, "aif.amoandg.w">;
+ def AIF_AMOORG_W : ETOpsR2R1<0b0100001, 0b010, "aif.amoorg.w">;
+ def AIF_AMOMING_W : ETOpsR2R1<0b1000001, 0b010, "aif.amoming.w">;
+ def AIF_AMOMAXG_W : ETOpsR2R1<0b1010001, 0b010, "aif.amomaxg.w">;
+ def AIF_AMOMINUG_W : ETOpsR2R1<0b1100001, 0b010, "aif.amominug.w">;
+ def AIF_AMOMAXUG_W : ETOpsR2R1<0b1110001, 0b010, "aif.amomaxug.w">;
+ def AIF_AMOCMPSWAPG_W : ETOpsR2R1<0b1111001, 0b010, "aif.amocmpswapg.w">;
+
+ def AIF_AMOSWAPL_D : ETOpsR2R1<0b0000100, 0b011, "aif.amoswapl.d">;
+ def AIF_AMOADDL_D : ETOpsR2R1<0b0000000, 0b011, "aif.amoaddl.d">;
+ def AIF_AMOXORL_D : ETOpsR2R1<0b0010000, 0b011, "aif.amoxorl.d">;
+ def AIF_AMOANDL_D : ETOpsR2R1<0b0110000, 0b011, "aif.amoandl.d">;
+ def AIF_AMOORL_D : ETOpsR2R1<0b0100000, 0b011, "aif.amoorl.d">;
+ def AIF_AMOMINL_D : ETOpsR2R1<0b1000000, 0b011, "aif.amominl.d">;
+ def AIF_AMOMAXL_D : ETOpsR2R1<0b1010000, 0b011, "aif.amomaxl.d">;
+ def AIF_AMOMINUL_D : ETOpsR2R1<0b1100000, 0b011, "aif.amominul.d">;
+ def AIF_AMOMAXUL_D : ETOpsR2R1<0b1110000, 0b011, "aif.amomaxul.d">;
+ def AIF_AMOCMPSWAPL_D : ETOpsR2R1<0b1111000, 0b011, "aif.amocmpswapl.d">;
+
+ def AIF_AMOSWAPG_D : ETOpsR2R1<0b0000101, 0b011, "aif.amoswapg.d">;
+ def AIF_AMOADDG_D : ETOpsR2R1<0b0000001, 0b011, "aif.amoaddg.d">;
+ def AIF_AMOXORG_D : ETOpsR2R1<0b0010001, 0b011, "aif.amoxorg.d">;
+ def AIF_AMOANDG_D : ETOpsR2R1<0b0110001, 0b011, "aif.amoandg.d">;
+ def AIF_AMOORG_D : ETOpsR2R1<0b0100001, 0b011, "aif.amoorg.d">;
+ def AIF_AMOMING_D : ETOpsR2R1<0b1000001, 0b011, "aif.amoming.d">;
+ def AIF_AMOMAXG_D : ETOpsR2R1<0b1010001, 0b011, "aif.amomaxg.d">;
+ def AIF_AMOMINUG_D : ETOpsR2R1<0b1100001, 0b011, "aif.amominug.d">;
+ def AIF_AMOMAXUG_D : ETOpsR2R1<0b1110001, 0b011, "aif.amomaxug.d">;
+ def AIF_AMOCMPSWAPG_D : ETOpsR2R1<0b1111001, 0b011, "aif.amocmpswapg.d">;
+ } // let mayLoad = 1, mayStore =1 in
+
+ class ETOpsR1R2S<bits<7> funct7, bits<3> funct3, string opcodestr> :
+ RVInstR<funct7, funct3, OPC_OP_32, (outs),
+ (ins GPR:$rs2, GPRMemZeroOffset:$rs1), opcodestr,
+ "${rs2}, ${rs1}"> {
+ let rd = 0;
+ }
+
+ let mayLoad = 1 in {
+ def AIF_SBL : ETOpsR1R2S<0b0001000, 0b011, "aif.sbl">;
+ def AIF_SHL : ETOpsR1R2S<0b0001100, 0b011, "aif.shl">;
+ def AIF_SBG : ETOpsR1R2S<0b0001001, 0b011, "aif.sbg">;
+ def AIF_SHG : ETOpsR1R2S<0b0001101, 0b011, "aif.shg">;
+ }
+
+ // These pseudo-instructions are used for stack references
+ // where various places assume the offset immediate follows
+ // the address operand.
+ let mayStore = 1 in
+ def AIF_StackFSQ2 : Pseudo<(outs),
+ (ins FPR256:$rs2, GPR:$rs1, simm12_lo:$imm), [],
+ "aif.fsq2", "$rs2, ${imm}(${rs1})">;
+ let mayLoad = 1 in
+ def AIF_StackFLQ2 : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, simm12_lo:$imm), [],
+ "aif.flq2", "$rd, ${imm}(${rs1})">;
+
+ // These pseudo-instructions are used for spill and reload
+ // of mask registers
+ let mayStore = 1 in
+ def AIF_StackMS : Pseudo<(outs),
+ (ins MR:$rs2, GPR:$rs1, simm12_lo:$imm), [],
+ "aif.ms", "$rs2, ${imm}(${rs1})">;
+ let mayLoad = 1 in
+ def AIF_StackML : Pseudo<(outs MR:$rd),
+ (ins GPR:$rs1, simm12_lo:$imm), [],
+ "aif.ml", "$rd, ${imm}(${rs1})">;
+
+ } // let hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+} // let Predicates = [HasXAIFET], DecoderNamespace = "XAIF"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5becfd2ad502b..64328a7be21f2 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -881,3 +881,19 @@ def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv",
FeatureStdExtV,
FeatureVendorXAndesPerf],
Andes45TuneFeatures>;
+
+def ESPERANTO_SOC1 : RISCVProcessorModel<"et-soc1",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtF,
+ FeatureStdExtC,
+ FeatureVendorXAIFET]>;
+
+def AINEKKO_ERBIUM : RISCVProcessorModel<"an-erbium",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtF,
+ FeatureStdExtC,
+ FeatureVendorXAIFET]>;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index e3657badfa9a4..0112cc2b4426b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -901,3 +901,42 @@ let RegInfos = XLenRI in {
def TRM2 : RISCVRegisterClass<[untyped], 32, (add (decimate TR, 2))>;
def TRM4 : RISCVRegisterClass<[untyped], 32, (add (decimate TR, 4))>;
}
+
+//===----------------------------------------------------------------------===//
+// XAIFET registers
+//===----------------------------------------------------------------------===//
+
+// Each scalar floating point register is extended to a 256 bits wide vector.
+// The original scalar floating point register occupies the 32 LSB of the
+// vector.
+
+let SubRegIndices = [sub_32] in
+ class RISCVReg256<RISCVReg32 subreg> :
+ RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
+ subreg.AltNames>;
+
+let RegAltNameIndices = [ABIRegAltName] in
+ foreach Index = 0-31 in
+ def F#Index#_Q2 : RISCVReg256<!cast<RISCVReg32>("F"#Index#"_F")>,
+ DwarfRegNum<[!add(Index, 3088)]>;
+
+// The order of registers represents the preferred allocation sequence,
+// meaning caller-save regs are listed before callee-save.
+def FPR256 : RISCVRegisterClass<[v8i32, v8f32], 256,
+ (add
+ (sequence "F%u_Q2", 0, 7),
+ (sequence "F%u_Q2", 10, 17),
+ (sequence "F%u_Q2", 28, 31),
+ (sequence "F%u_Q2", 8, 9),
+ (sequence "F%u_Q2", 18, 27))>;
+
+// Mask registers m0 to m7
+foreach Index = 0-7 in
+ def M#Index : RISCVReg<Index, "m"#Index, ["m"#Index]>,
+ DwarfRegNum<[!add(Index, 4020)]>;
+
+// Allowing i8 in addition to v8i1 simplifies the handling of builtins
+def MR : RISCVRegisterClass<[i8, v8i1], 8,
+ (add (sequence "M%u", 1, 7), M0)>;
+
+def MR0 : RISCVRegisterClass<[i8, v8i1], 8, (add M0)>;
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 7f038ee728284..66e3484ff0955 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -566,3 +566,61 @@ foreach i = 0 - 3 in {
def : SysReg<"qc.mwpendaddr" # i, !add(0x7D4, i)>;
}
} // FeatureVendorXqciint, isRV32Only
+
+// XAIFET
+let FeaturesRequired = [{ {RISCV::FeatureVendorXAIFET} }] in {
+ def : SysReg<"aif.cache_invalidate", 0x7d0>;
+ def : SysReg<"aif.dcache_debug", 0xfc0>;
+ def : SysReg<"aif.evict_sw", 0x7f9>;
+ def : SysReg<"aif.evict_va", 0x89f>;
+ def : SysReg<"aif.excl_mode", 0x7d3>;
+ def : SysReg<"aif.fcc", 0x821>;
+ def : SysReg<"aif.fccnb", 0xcc0>;
+ def : SysReg<"aif.flb", 0x820>;
+ def : SysReg<"aif.flush_sw", 0x7fb>;
+ def : SysReg<"aif.flush_va", 0x8bf>;
+ def : SysReg<"aif.gsc_progress", 0x840>;
+ def : SysReg<"aif.hartid", 0xcd0>;
+ def : SysReg<"aif.lock_sw", 0x7fd>;
+ def : SysReg<"aif.lock_va", 0x8df>;
+ def : SysReg<"aif.matp", 0x7c0>;
+ def : SysReg<"aif.mbusaddr", 0x7d5>;
+ def : SysReg<"aif.mcache_control", 0x7e0>;
+ def : SysReg<"aif.menable_shadows", 0x7d2>;
+ def : SysReg<"aif.minstmask", 0x7cd>;
+ def : SysReg<"aif.minstmatch", 0x7ce>;
+ def : SysReg<"aif.portctrl0", 0x9cc>;
+ def : SysReg<"aif.portctrl1", 0x9cd>;
+ def : SysReg<"aif.portctrl2", 0x9ce>;
+ def : SysReg<"aif.portctrl3", 0x9cf>;
+ def : SysReg<"aif.porthead0", 0xcc8>;
+ def : SysReg<"aif.porthead1", 0xcc9>;
+ def : SysReg<"aif.porthead2", 0xcca>;
+ def : SysReg<"aif.porthead3", 0xccb>;
+ def : SysReg<"aif.portheadnb0", 0xccc>;
+ def : SysReg<"aif.portheadnb1", 0xccd>;
+ def : SysReg<"aif.portheadnb2", 0xcce>;
+ def : SysReg<"aif.portheadnb3", 0xccf>;
+ def : SysReg<"aif.prefetch_va", 0x81f>;
+ def : SysReg<"aif.stall", 0x822>;
+ def : SysReg<"aif.tensor_conv_ctrl", 0x803>;
+ def : SysReg<"aif.tensor_conv_size", 0x802>;
+ def : SysReg<"aif.tensor_coop", 0x804>;
+ def : SysReg<"aif.tensor_error", 0x808>;
+ def : SysReg<"aif.tensor_fma", 0x801>;
+ def : SysReg<"aif.tensor_load", 0x83f>;
+ def : SysReg<"aif.tensor_load_l2", 0x85f>;
+ def : SysReg<"aif.tensor_mask", 0x805>;
+ def : SysReg<"aif.tensor_quant", 0x806>;
+ def : SysReg<"aif.tensor_reduce", 0x800>;
+ def : SysReg<"aif.tensor_store", 0x87f>;
+ def : SysReg<"aif.tensor_wait", 0x830>;
+ def : SysReg<"aif.tex_send", 0x807>;
+ def : SysReg<"aif.ucache_control", 0x810>;
+ def : SysReg<"aif.unlock_sw", 0x7ff>;
+ def : SysReg<"aif.unlock_va", 0x8ff>;
+ def : SysReg<"aif.validation0", 0x8d0>;
+ def : SysReg<"aif.validation1", 0x8d1>;
+ def : SysReg<"aif.validation2", 0x8d2>;
+ def : SysReg<"aif.validation3", 0x8d3>;
+} // FeatureVendorXAIFET
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index e4e06d579a607..f514c18ae93ba 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -174,6 +174,7 @@
; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.
; CHECK-NEXT: vl-dependent-latency - Latency of vector instructions is dependent on the dynamic value of vl.
; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
+; CHECK-NEXT: xaifet - 'XAIFET' (AI Foundry ET Extension).
; CHECK-NEXT: xandesbfhcvt - 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension).
; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension).
; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).
diff --git a/llvm/test/MC/RISCV/xaifet-amo-valid.s b/llvm/test/MC/RISCV/xaifet-amo-valid.s
new file mode 100644
index 0000000000000..cbb1374ba71d0
--- /dev/null
+++ b/llvm/test/MC/RISCV/xaifet-amo-valid.s
@@ -0,0 +1,939 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# XAIFET - AI Foundry ET AMO instructions
+// CHECK-DISASM: <stdin>: file format elf64-littleriscv
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xaifet %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xaifet %s \
+# RUN: | llvm-objdump -d --mattr=+xaifet - | FileCheck %s --check-prefix=CHECK-DISASM
+
+#====----------------------------------------------------------------------===//
+# Scalar INT AMO local|global
+#====----------------------------------------------------------------------===//
+
+aif.amoaddg.d a4, s9, (t1)
+// CHECK-ENCODING: aif.amoaddg.d a4, s9, (t1) # encoding: [0x3b,0x37,0x93,0x03]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0393373b aif.amoaddg.d a4, s9, (t1)
+
+aif.amoaddg.w t1, s5, (t0)
+// CHECK-ENCODING: aif.amoaddg.w t1, s5, (t0) # encoding: [0x3b,0xa3,0x52,0x03]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0352a33b aif.amoaddg.w t1, s5, (t0)
+
+aif.amoaddl.d a4, s4, (a6)
+// CHECK-ENCODING: aif.amoaddl.d a4, s4, (a6) # encoding: [0x3b,0x37,0x48,0x01]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0148373b aif.amoaddl.d a4, s4, (a6)
+
+aif.amoaddl.w tp, t2, (gp)
+// CHECK-ENCODING: aif.amoaddl.w tp, t2, (gp) # encoding: [0x3b,0xa2,0x71,0x00]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0071a23b aif.amoaddl.w tp, t2, (gp)
+
+aif.amoandg.d s2, a5, (a2)
+// CHECK-ENCODING: aif.amoandg.d s2, a5, (a2) # encoding: [0x3b,0x39,0xf6,0x62]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 62f6393b aif.amoandg.d s2, a5, (a2)
+
+aif.amoandg.w t0, s8, (s2)
+// CHECK-ENCODING: aif.amoandg.w t0, s8, (s2) # encoding: [0xbb,0x22,0x89,0x63]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 638922bb aif.amoandg.w t0, s8, (s2)
+
+aif.amoandl.d sp, ra, (a4)
+// CHECK-ENCODING: aif.amoandl.d sp, ra, (a4) # encoding: [0x3b,0x31,0x17,0x60]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6017313b aif.amoandl.d sp, ra, (a4)
+
+aif.amoandl.w t5, s0, (gp)
+// CHECK-ENCODING: aif.amoandl.w t5, s0, (gp) # encoding: [0x3b,0xaf,0x81,0x60]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6081af3b aif.amoandl.w t5, s0, (gp)
+
+aif.amocmpswapg.d fp, gp, (a3)
+// CHECK-ENCODING: aif.amocmpswapg.d s0, gp, (a3) # encoding: [0x3b,0xb4,0x36,0xf2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f236b43b aif.amocmpswapg.d s0, gp, (a3)
+
+aif.amocmpswapg.w a5, tp, (s8)
+// CHECK-ENCODING: aif.amocmpswapg.w a5, tp, (s8) # encoding: [0xbb,0x27,0x4c,0xf2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f24c27bb aif.amocmpswapg.w a5, tp, (s8)
+
+aif.amocmpswapl.d t5, s6, (s1)
+// CHECK-ENCODING: aif.amocmpswapl.d t5, s6, (s1) # encoding: [0x3b,0xbf,0x64,0xf1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f164bf3b aif.amocmpswapl.d t5, s6, (s1)
+
+aif.amocmpswapl.w a7, s0, (sp)
+// CHECK-ENCODING: aif.amocmpswapl.w a7, s0, (sp) # encoding: [0xbb,0x28,0x81,0xf0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f08128bb aif.amocmpswapl.w a7, s0, (sp)
+
+aif.amomaxg.d tp, s10, (a2)
+// CHECK-ENCODING: aif.amomaxg.d tp, s10, (a2) # encoding: [0x3b,0x32,0xa6,0xa3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a3a6323b aif.amomaxg.d tp, s10, (a2)
+
+aif.amomaxg.w a0, s6, (a1)
+// CHECK-ENCODING: aif.amomaxg.w a0, s6, (a1) # encoding: [0x3b,0xa5,0x65,0xa3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a365a53b aif.amomaxg.w a0, s6, (a1)
+
+aif.amomaxl.d a6, s7, (s4)
+// CHECK-ENCODING: aif.amomaxl.d a6, s7, (s4) # encoding: [0x3b,0x38,0x7a,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a17a383b aif.amomaxl.d a6, s7, (s4)
+
+aif.amomaxl.w s4, s3, (a7)
+// CHECK-ENCODING: aif.amomaxl.w s4, s3, (a7) # encoding: [0x3b,0xaa,0x38,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a138aa3b aif.amomaxl.w s4, s3, (a7)
+
+aif.amomaxug.d t0, s4, (t2)
+// CHECK-ENCODING: aif.amomaxug.d t0, s4, (t2) # encoding: [0xbb,0xb2,0x43,0xe3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e343b2bb aif.amomaxug.d t0, s4, (t2)
+
+aif.amomaxug.w s5, t5, (t2)
+// CHECK-ENCODING: aif.amomaxug.w s5, t5, (t2) # encoding: [0xbb,0xaa,0xe3,0xe3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e3e3aabb aif.amomaxug.w s5, t5, (t2)
+
+aif.amomaxul.d t2, t2, (tp)
+// CHECK-ENCODING: aif.amomaxul.d t2, t2, (tp) # encoding: [0xbb,0x33,0x72,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e07233bb aif.amomaxul.d t2, t2, (tp)
+
+aif.amomaxul.w t5, a2, (t4)
+// CHECK-ENCODING: aif.amomaxul.w t5, a2, (t4) # encoding: [0x3b,0xaf,0xce,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e0ceaf3b aif.amomaxul.w t5, a2, (t4)
+
+aif.amoming.d fp, t0, (s1)
+// CHECK-ENCODING: aif.amoming.d s0, t0, (s1) # encoding: [0x3b,0xb4,0x54,0x82]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8254b43b aif.amoming.d s0, t0, (s1)
+
+aif.amoming.w a1, s4, (t2)
+// CHECK-ENCODING: aif.amoming.w a1, s4, (t2) # encoding: [0xbb,0xa5,0x43,0x83]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8343a5bb aif.amoming.w a1, s4, (t2)
+
+aif.amominl.d t0, a5, (t3)
+// CHECK-ENCODING: aif.amominl.d t0, a5, (t3) # encoding: [0xbb,0x32,0xfe,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 80fe32bb aif.amominl.d t0, a5, (t3)
+
+aif.amominl.w t3, s5, (gp)
+// CHECK-ENCODING: aif.amominl.w t3, s5, (gp) # encoding: [0x3b,0xae,0x51,0x81]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8151ae3b aif.amominl.w t3, s5, (gp)
+
+aif.amominug.d s9, t1, (s3)
+// CHECK-ENCODING: aif.amominug.d s9, t1, (s3) # encoding: [0xbb,0xbc,0x69,0xc2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c269bcbb aif.amominug.d s9, t1, (s3)
+
+aif.amominug.w a4, fp, (gp)
+// CHECK-ENCODING: aif.amominug.w a4, s0, (gp) # encoding: [0x3b,0xa7,0x81,0xc2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c281a73b aif.amominug.w a4, s0, (gp)
+
+aif.amominul.d ra, a6, (ra)
+// CHECK-ENCODING: aif.amominul.d ra, a6, (ra) # encoding: [0xbb,0xb0,0x00,0xc1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c100b0bb aif.amominul.d ra, a6, (ra)
+
+aif.amominul.w a1, a3, (s8)
+// CHECK-ENCODING: aif.amominul.w a1, a3, (s8) # encoding: [0xbb,0x25,0xdc,0xc0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c0dc25bb aif.amominul.w a1, a3, (s8)
+
+aif.amoorg.d a5, a7, (a4)
+// CHECK-ENCODING: aif.amoorg.d a5, a7, (a4) # encoding: [0xbb,0x37,0x17,0x43]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 431737bb aif.amoorg.d a5, a7, (a4)
+
+aif.amoorg.w s10, a5, (s9)
+// CHECK-ENCODING: aif.amoorg.w s10, a5, (s9) # encoding: [0x3b,0xad,0xfc,0x42]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 42fcad3b aif.amoorg.w s10, a5, (s9)
+
+aif.amoorl.d ra, t3, (zero)
+// CHECK-ENCODING: aif.amoorl.d ra, t3, (zero) # encoding: [0xbb,0x30,0xc0,0x41]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 41c030bb aif.amoorl.d ra, t3, (zero)
+
+aif.amoorl.w t5, a5, (a7)
+// CHECK-ENCODING: aif.amoorl.w t5, a5, (a7) # encoding: [0x3b,0xaf,0xf8,0x40]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 40f8af3b aif.amoorl.w t5, a5, (a7)
+
+aif.amoswapg.d s7, sp, (sp)
+// CHECK-ENCODING: aif.amoswapg.d s7, sp, (sp) # encoding: [0xbb,0x3b,0x21,0x0a]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0a213bbb aif.amoswapg.d s7, sp, (sp)
+
+aif.amoswapg.w a7, t3, (s9)
+// CHECK-ENCODING: aif.amoswapg.w a7, t3, (s9) # encoding: [0xbb,0xa8,0xcc,0x0b]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0bcca8bb aif.amoswapg.w a7, t3, (s9)
+
+aif.amoswapl.d sp, gp, (t5)
+// CHECK-ENCODING: aif.amoswapl.d sp, gp, (t5) # encoding: [0x3b,0x31,0x3f,0x08]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 083f313b aif.amoswapl.d sp, gp, (t5)
+
+aif.amoswapl.w s1, a7, (s9)
+// CHECK-ENCODING: aif.amoswapl.w s1, a7, (s9) # encoding: [0xbb,0xa4,0x1c,0x09]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 091ca4bb aif.amoswapl.w s1, a7, (s9)
+
+aif.amoxorg.d t4, s1, (s1)
+// CHECK-ENCODING: aif.amoxorg.d t4, s1, (s1) # encoding: [0xbb,0xbe,0x94,0x22]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2294bebb aif.amoxorg.d t4, s1, (s1)
+
+aif.amoxorg.w gp, a4, (sp)
+// CHECK-ENCODING: aif.amoxorg.w gp, a4, (sp) # encoding: [0xbb,0x21,0xe1,0x22]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 22e121bb aif.amoxorg.w gp, a4, (sp)
+
+aif.amoxorl.d sp, a0, (a0)
+// CHECK-ENCODING: aif.amoxorl.d sp, a0, (a0) # encoding: [0x3b,0x31,0xa5,0x20]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 20a5313b aif.amoxorl.d sp, a0, (a0)
+
+aif.amoxorl.w s1, a7, (fp)
+// CHECK-ENCODING: aif.amoxorl.w s1, a7, (s0) # encoding: [0xbb,0x24,0x14,0x21]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 211424bb aif.amoxorl.w s1, a7, (s0)
+
+aif.amoaddg.d a4, s9, 0(t1)
+// CHECK-ENCODING: aif.amoaddg.d a4, s9, (t1) # encoding: [0x3b,0x37,0x93,0x03]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0393373b aif.amoaddg.d a4, s9, (t1)
+
+aif.amoaddg.w t1, s5, 0(t0)
+// CHECK-ENCODING: aif.amoaddg.w t1, s5, (t0) # encoding: [0x3b,0xa3,0x52,0x03]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0352a33b aif.amoaddg.w t1, s5, (t0)
+
+aif.amoaddl.d a4, s4, 0(a6)
+// CHECK-ENCODING: aif.amoaddl.d a4, s4, (a6) # encoding: [0x3b,0x37,0x48,0x01]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0148373b aif.amoaddl.d a4, s4, (a6)
+
+aif.amoaddl.w tp, t2, 0(gp)
+// CHECK-ENCODING: aif.amoaddl.w tp, t2, (gp) # encoding: [0x3b,0xa2,0x71,0x00]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0071a23b aif.amoaddl.w tp, t2, (gp)
+
+aif.amoandg.d s2, a5, 0(a2)
+// CHECK-ENCODING: aif.amoandg.d s2, a5, (a2) # encoding: [0x3b,0x39,0xf6,0x62]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 62f6393b aif.amoandg.d s2, a5, (a2)
+
+aif.amoandg.w t0, s8, 0(s2)
+// CHECK-ENCODING: aif.amoandg.w t0, s8, (s2) # encoding: [0xbb,0x22,0x89,0x63]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 638922bb aif.amoandg.w t0, s8, (s2)
+
+aif.amoandl.d sp, ra, 0(a4)
+// CHECK-ENCODING: aif.amoandl.d sp, ra, (a4) # encoding: [0x3b,0x31,0x17,0x60]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6017313b aif.amoandl.d sp, ra, (a4)
+
+aif.amoandl.w t5, s0, 0(gp)
+// CHECK-ENCODING: aif.amoandl.w t5, s0, (gp) # encoding: [0x3b,0xaf,0x81,0x60]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6081af3b aif.amoandl.w t5, s0, (gp)
+
+aif.amocmpswapg.d fp, gp, 0(a3)
+// CHECK-ENCODING: aif.amocmpswapg.d s0, gp, (a3) # encoding: [0x3b,0xb4,0x36,0xf2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f236b43b aif.amocmpswapg.d s0, gp, (a3)
+
+aif.amocmpswapg.w a5, tp, 0(s8)
+// CHECK-ENCODING: aif.amocmpswapg.w a5, tp, (s8) # encoding: [0xbb,0x27,0x4c,0xf2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f24c27bb aif.amocmpswapg.w a5, tp, (s8)
+
+aif.amocmpswapl.d t5, s6, 0(s1)
+// CHECK-ENCODING: aif.amocmpswapl.d t5, s6, (s1) # encoding: [0x3b,0xbf,0x64,0xf1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f164bf3b aif.amocmpswapl.d t5, s6, (s1)
+
+aif.amocmpswapl.w a7, s0, 0(sp)
+// CHECK-ENCODING: aif.amocmpswapl.w a7, s0, (sp) # encoding: [0xbb,0x28,0x81,0xf0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f08128bb aif.amocmpswapl.w a7, s0, (sp)
+
+aif.amomaxg.d tp, s10, 0(a2)
+// CHECK-ENCODING: aif.amomaxg.d tp, s10, (a2) # encoding: [0x3b,0x32,0xa6,0xa3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a3a6323b aif.amomaxg.d tp, s10, (a2)
+
+aif.amomaxg.w a0, s6, 0(a1)
+// CHECK-ENCODING: aif.amomaxg.w a0, s6, (a1) # encoding: [0x3b,0xa5,0x65,0xa3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a365a53b aif.amomaxg.w a0, s6, (a1)
+
+aif.amomaxl.d a6, s7, 0(s4)
+// CHECK-ENCODING: aif.amomaxl.d a6, s7, (s4) # encoding: [0x3b,0x38,0x7a,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a17a383b aif.amomaxl.d a6, s7, (s4)
+
+aif.amomaxl.w s4, s3, 0(a7)
+// CHECK-ENCODING: aif.amomaxl.w s4, s3, (a7) # encoding: [0x3b,0xaa,0x38,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a138aa3b aif.amomaxl.w s4, s3, (a7)
+
+aif.amomaxug.d t0, s4, 0(t2)
+// CHECK-ENCODING: aif.amomaxug.d t0, s4, (t2) # encoding: [0xbb,0xb2,0x43,0xe3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e343b2bb aif.amomaxug.d t0, s4, (t2)
+
+aif.amomaxug.w s5, t5, 0(t2)
+// CHECK-ENCODING: aif.amomaxug.w s5, t5, (t2) # encoding: [0xbb,0xaa,0xe3,0xe3]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e3e3aabb aif.amomaxug.w s5, t5, (t2)
+
+aif.amomaxul.d t2, t2, 0(tp)
+// CHECK-ENCODING: aif.amomaxul.d t2, t2, (tp) # encoding: [0xbb,0x33,0x72,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e07233bb aif.amomaxul.d t2, t2, (tp)
+
+aif.amomaxul.w t5, a2, 0(t4)
+// CHECK-ENCODING: aif.amomaxul.w t5, a2, (t4) # encoding: [0x3b,0xaf,0xce,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e0ceaf3b aif.amomaxul.w t5, a2, (t4)
+
+aif.amoming.d fp, t0, 0(s1)
+// CHECK-ENCODING: aif.amoming.d s0, t0, (s1) # encoding: [0x3b,0xb4,0x54,0x82]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8254b43b aif.amoming.d s0, t0, (s1)
+
+aif.amoming.w a1, s4, 0(t2)
+// CHECK-ENCODING: aif.amoming.w a1, s4, (t2) # encoding: [0xbb,0xa5,0x43,0x83]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8343a5bb aif.amoming.w a1, s4, (t2)
+
+aif.amominl.d t0, a5, 0(t3)
+// CHECK-ENCODING: aif.amominl.d t0, a5, (t3) # encoding: [0xbb,0x32,0xfe,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 80fe32bb aif.amominl.d t0, a5, (t3)
+
+aif.amominl.w t3, s5, 0(gp)
+// CHECK-ENCODING: aif.amominl.w t3, s5, (gp) # encoding: [0x3b,0xae,0x51,0x81]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8151ae3b aif.amominl.w t3, s5, (gp)
+
+aif.amominug.d s9, t1, 0(s3)
+// CHECK-ENCODING: aif.amominug.d s9, t1, (s3) # encoding: [0xbb,0xbc,0x69,0xc2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c269bcbb aif.amominug.d s9, t1, (s3)
+
+aif.amominug.w a4, fp, 0(gp)
+// CHECK-ENCODING: aif.amominug.w a4, s0, (gp) # encoding: [0x3b,0xa7,0x81,0xc2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c281a73b aif.amominug.w a4, s0, (gp)
+
+aif.amominul.d ra, a6, 0(ra)
+// CHECK-ENCODING: aif.amominul.d ra, a6, (ra) # encoding: [0xbb,0xb0,0x00,0xc1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c100b0bb aif.amominul.d ra, a6, (ra)
+
+aif.amominul.w a1, a3, 0(s8)
+// CHECK-ENCODING: aif.amominul.w a1, a3, (s8) # encoding: [0xbb,0x25,0xdc,0xc0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c0dc25bb aif.amominul.w a1, a3, (s8)
+
+aif.amoorg.d a5, a7, 0(a4)
+// CHECK-ENCODING: aif.amoorg.d a5, a7, (a4) # encoding: [0xbb,0x37,0x17,0x43]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 431737bb aif.amoorg.d a5, a7, (a4)
+
+aif.amoorg.w s10, a5, 0(s9)
+// CHECK-ENCODING: aif.amoorg.w s10, a5, (s9) # encoding: [0x3b,0xad,0xfc,0x42]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 42fcad3b aif.amoorg.w s10, a5, (s9)
+
+aif.amoorl.d ra, t3, 0(zero)
+// CHECK-ENCODING: aif.amoorl.d ra, t3, (zero) # encoding: [0xbb,0x30,0xc0,0x41]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 41c030bb aif.amoorl.d ra, t3, (zero)
+
+aif.amoorl.w t5, a5, 0(a7)
+// CHECK-ENCODING: aif.amoorl.w t5, a5, (a7) # encoding: [0x3b,0xaf,0xf8,0x40]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 40f8af3b aif.amoorl.w t5, a5, (a7)
+
+aif.amoswapg.d s7, sp, 0(sp)
+// CHECK-ENCODING: aif.amoswapg.d s7, sp, (sp) # encoding: [0xbb,0x3b,0x21,0x0a]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0a213bbb aif.amoswapg.d s7, sp, (sp)
+
+aif.amoswapg.w a7, t3, 0(s9)
+// CHECK-ENCODING: aif.amoswapg.w a7, t3, (s9) # encoding: [0xbb,0xa8,0xcc,0x0b]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0bcca8bb aif.amoswapg.w a7, t3, (s9)
+
+aif.amoswapl.d sp, gp, 0(t5)
+// CHECK-ENCODING: aif.amoswapl.d sp, gp, (t5) # encoding: [0x3b,0x31,0x3f,0x08]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 083f313b aif.amoswapl.d sp, gp, (t5)
+
+aif.amoswapl.w s1, a7, 0(s9)
+// CHECK-ENCODING: aif.amoswapl.w s1, a7, (s9) # encoding: [0xbb,0xa4,0x1c,0x09]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 091ca4bb aif.amoswapl.w s1, a7, (s9)
+
+aif.amoxorg.d t4, s1, 0(s1)
+// CHECK-ENCODING: aif.amoxorg.d t4, s1, (s1) # encoding: [0xbb,0xbe,0x94,0x22]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2294bebb aif.amoxorg.d t4, s1, (s1)
+
+aif.amoxorg.w gp, a4, 0(sp)
+// CHECK-ENCODING: aif.amoxorg.w gp, a4, (sp) # encoding: [0xbb,0x21,0xe1,0x22]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 22e121bb aif.amoxorg.w gp, a4, (sp)
+
+aif.amoxorl.d sp, a0, 0(a0)
+// CHECK-ENCODING: aif.amoxorl.d sp, a0, (a0) # encoding: [0x3b,0x31,0xa5,0x20]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 20a5313b aif.amoxorl.d sp, a0, (a0)
+
+aif.amoxorl.w s1, a7, 0(fp)
+// CHECK-ENCODING: aif.amoxorl.w s1, a7, (s0) # encoding: [0xbb,0x24,0x14,0x21]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 211424bb aif.amoxorl.w s1, a7, (s0)
+
+#====----------------------------------------------------------------------===//
+# SIMD INT AMO local|global
+#====----------------------------------------------------------------------===//
+
+aif.famoaddg.pi fa5, ft5, (a5)
+// CHECK-ENCODING: aif.famoaddg.pi fa5, ft5, (a5) # encoding: [0x8b,0xc7,0xf2,0x86]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 86f2c78b aif.famoaddg.pi fa5, ft5, (a5)
+
+aif.famoaddl.pi fs3, ft1, (gp)
+// CHECK-ENCODING: aif.famoaddl.pi fs3, ft1, (gp) # encoding: [0x8b,0xc9,0x30,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0630c98b aif.famoaddl.pi fs3, ft1, (gp)
+
+aif.famoandg.pi fs7, ft5, (s3)
+// CHECK-ENCODING: aif.famoandg.pi fs7, ft5, (s3) # encoding: [0x8b,0xcb,0x32,0x97]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 9732cb8b aif.famoandg.pi fs7, ft5, (s3)
+
+aif.famoandl.pi fs6, fs5, (a0)
+// CHECK-ENCODING: aif.famoandl.pi fs6, fs5, (a0) # encoding: [0x0b,0xcb,0xaa,0x16]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 16aacb0b aif.famoandl.pi fs6, fs5, (a0)
+
+aif.famomaxg.pi ft0, ft10, (s6)
+// CHECK-ENCODING: aif.famomaxg.pi ft0, ft10, (s6) # encoding: [0x0b,0x40,0x6f,0xb7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: b76f400b aif.famomaxg.pi ft0, ft10, (s6)
+
+aif.famomaxg.ps fs1, fs9, (s7)
+// CHECK-ENCODING: aif.famomaxg.ps fs1, fs9, (s7) # encoding: [0x8b,0xc4,0x7c,0xa9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a97cc48b aif.famomaxg.ps fs1, fs9, (s7)
+
+aif.famomaxl.pi ft11, ft6, (t5)
+// CHECK-ENCODING: aif.famomaxl.pi ft11, ft6, (t5) # encoding: [0x8b,0x4f,0xe3,0x37]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 37e34f8b aif.famomaxl.pi ft11, ft6, (t5)
+
+aif.famomaxl.ps fs6, fs9, (zero)
+// CHECK-ENCODING: aif.famomaxl.ps fs6, fs9, (zero) # encoding: [0x0b,0xcb,0x0c,0x28]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 280ccb0b aif.famomaxl.ps fs6, fs9, (zero)
+
+aif.famomaxug.pi ft9, fs1, (s5)
+// CHECK-ENCODING: aif.famomaxug.pi ft9, fs1, (s5) # encoding: [0x8b,0xce,0x54,0xc7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c754ce8b aif.famomaxug.pi ft9, fs1, (s5)
+
+aif.famomaxul.pi ft11, fs3, (s4)
+// CHECK-ENCODING: aif.famomaxul.pi ft11, fs3, (s4) # encoding: [0x8b,0xcf,0x49,0x47]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 4749cf8b aif.famomaxul.pi ft11, fs3, (s4)
+
+aif.famoming.pi fa5, ft6, (a7)
+// CHECK-ENCODING: aif.famoming.pi fa5, ft6, (a7) # encoding: [0x8b,0x47,0x13,0xaf]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: af13478b aif.famoming.pi fa5, ft6, (a7)
+
+aif.famoming.ps ft2, ft8, (fp)
+// CHECK-ENCODING: aif.famoming.ps ft2, ft8, (s0) # encoding: [0x0b,0x41,0x8e,0xb0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: b08e410b aif.famoming.ps ft2, ft8, (s0)
+
+aif.famominl.pi ft6, fs2, (a0)
+// CHECK-ENCODING: aif.famominl.pi ft6, fs2, (a0) # encoding: [0x0b,0x43,0xa9,0x2e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2ea9430b aif.famominl.pi ft6, fs2, (a0)
+
+aif.famominl.ps ft5, ft4, (s3)
+// CHECK-ENCODING: aif.famominl.ps ft5, ft4, (s3) # encoding: [0x8b,0x42,0x32,0x31]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 3132428b aif.famominl.ps ft5, ft4, (s3)
+
+aif.famominug.pi ft7, fs10, (s1)
+// CHECK-ENCODING: aif.famominug.pi ft7, fs10, (s1) # encoding: [0x8b,0x43,0x9d,0xbe]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: be9d438b aif.famominug.pi ft7, fs10, (s1)
+
+aif.famominul.pi fa6, fs10, (tp)
+// CHECK-ENCODING: aif.famominul.pi fa6, fs10, (tp) # encoding: [0x0b,0x48,0x4d,0x3e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 3e4d480b aif.famominul.pi fa6, fs10, (tp)
+
+aif.famoorg.pi ft9, fs8, (gp)
+// CHECK-ENCODING: aif.famoorg.pi ft9, fs8, (gp) # encoding: [0x8b,0x4e,0x3c,0x9e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 9e3c4e8b aif.famoorg.pi ft9, fs8, (gp)
+
+aif.famoorl.pi fa0, ft8, (s5)
+// CHECK-ENCODING: aif.famoorl.pi fa0, ft8, (s5) # encoding: [0x0b,0x45,0x5e,0x1f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1f5e450b aif.famoorl.pi fa0, ft8, (s5)
+
+aif.famoswapg.pi fs5, fs9, (s10)
+// CHECK-ENCODING: aif.famoswapg.pi fs5, fs9, (s10) # encoding: [0x8b,0xca,0xac,0x8f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8facca8b aif.famoswapg.pi fs5, fs9, (s10)
+
+aif.famoswapl.pi fs0, fa4, (s10)
+// CHECK-ENCODING: aif.famoswapl.pi fs0, fa4, (s10) # encoding: [0x0b,0x44,0xa7,0x0f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0fa7440b aif.famoswapl.pi fs0, fa4, (s10)
+
+aif.famoxorg.pi fs7, ft9, (t5)
+// CHECK-ENCODING: aif.famoxorg.pi fs7, ft9, (t5) # encoding: [0x8b,0xcb,0xee,0xa7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a7eecb8b aif.famoxorg.pi fs7, ft9, (t5)
+
+aif.famoxorl.pi fa7, fs7, (a4)
+// CHECK-ENCODING: aif.famoxorl.pi fa7, fs7, (a4) # encoding: [0x8b,0xc8,0xeb,0x26]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 26ebc88b aif.famoxorl.pi fa7, fs7, (a4)
+
+#====----------------------------------------------------------------------===//
+# SIMD global
+#====----------------------------------------------------------------------===//
+
+aif.fgbg.ps fs7, fs6, (s0)
+// CHECK-ENCODING: aif.fgbg.ps fs7, fs6, (s0) # encoding: [0x8b,0x7b,0x8b,0x82]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 828b7b8b aif.fgbg.ps fs7, fs6, (s0)
+
+aif.fghg.ps fa4, fs8, (s6)
+// CHECK-ENCODING: aif.fghg.ps fa4, fs8, (s6) # encoding: [0x0b,0x77,0x6c,0x8b]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8b6c770b aif.fghg.ps fa4, fs8, (s6)
+
+aif.fgwg.ps fa6, fs6, (tp)
+// CHECK-ENCODING: aif.fgwg.ps fa6, fs6, (tp) # encoding: [0x0b,0x78,0x4b,0x92]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 924b780b aif.fgwg.ps fa6, fs6, (tp)
+
+aif.flwg.ps fs10, (a4)
+// CHECK-ENCODING: aif.flwg.ps fs10, (a4) # encoding: [0x0b,0x7d,0x07,0x12]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 12077d0b aif.flwg.ps fs10, (a4)
+
+aif.fscbg.ps fa6, fs5, (t0)
+// CHECK-ENCODING: aif.fscbg.ps fa6, fs5, (t0) # encoding: [0x0b,0xf8,0x5a,0xc2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c25af80b aif.fscbg.ps fa6, fs5, (t0)
+
+aif.fschg.ps fa3, fs9, (s8)
+// CHECK-ENCODING: aif.fschg.ps fa3, fs9, (s8) # encoding: [0x8b,0xf6,0x8c,0xcb]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: cb8cf68b aif.fschg.ps fa3, fs9, (s8)
+
+aif.fscwg.ps ft4, fs9, (s0)
+// CHECK-ENCODING: aif.fscwg.ps ft4, fs9, (s0) # encoding: [0x0b,0xf2,0x8c,0xd2]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d28cf20b aif.fscwg.ps ft4, fs9, (s0)
+
+aif.fswg.ps fa5, (t5)
+// CHECK-ENCODING: aif.fswg.ps fa5, (t5) # encoding: [0x8b,0x77,0x0f,0x52]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 520f778b aif.fswg.ps fa5, (t5)
+
+#====----------------------------------------------------------------------===//
+# SIMD local
+#====----------------------------------------------------------------------===//
+
+aif.fgbl.ps fs3, ft11, (ra)
+// CHECK-ENCODING: aif.fgbl.ps fs3, ft11, (ra) # encoding: [0x8b,0xf9,0x1f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 801ff98b aif.fgbl.ps fs3, ft11, (ra)
+
+aif.fghl.ps ft1, fs2, (s5)
+// CHECK-ENCODING: aif.fghl.ps ft1, fs2, (s5) # encoding: [0x8b,0x70,0x59,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8959708b aif.fghl.ps ft1, fs2, (s5)
+
+aif.fgwl.ps ft6, fs2, (gp)
+// CHECK-ENCODING: aif.fgwl.ps ft6, fs2, (gp) # encoding: [0x0b,0x73,0x39,0x90]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 9039730b aif.fgwl.ps ft6, fs2, (gp)
+
+aif.flwl.ps fs1, (t2)
+// CHECK-ENCODING: aif.flwl.ps fs1, (t2) # encoding: [0x8b,0xf4,0x03,0x10]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1003f48b aif.flwl.ps fs1, (t2)
+
+aif.fscbl.ps ft5, ft7, (s5)
+// CHECK-ENCODING: aif.fscbl.ps ft5, ft7, (s5) # encoding: [0x8b,0xf2,0x53,0xc1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c153f28b aif.fscbl.ps ft5, ft7, (s5)
+
+aif.fschl.ps fs8, ft1, (t1)
+// CHECK-ENCODING: aif.fschl.ps fs8, ft1, (t1) # encoding: [0x0b,0xfc,0x60,0xc8]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c860fc0b aif.fschl.ps fs8, ft1, (t1)
+
+aif.fscwl.ps fs0, ft11, (ra)
+// CHECK-ENCODING: aif.fscwl.ps fs0, ft11, (ra) # encoding: [0x0b,0xf4,0x1f,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d01ff40b aif.fscwl.ps fs0, ft11, (ra)
+
+aif.fswl.ps ft7, (t2)
+// CHECK-ENCODING: aif.fswl.ps ft7, (t2) # encoding: [0x8b,0xf3,0x03,0x50]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 5003f38b aif.fswl.ps ft7, (t2)
+
+#====----------------------------------------------------------------------===//
+# Scalar global
+#====----------------------------------------------------------------------===//
+
+aif.sbg a6, (t4)
+// CHECK-ENCODING: aif.sbg a6, (t4) # encoding: [0x3b,0xb0,0x0e,0x13]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 130eb03b aif.sbg a6, (t4)
+
+aif.shg sp, (s6)
+// CHECK-ENCODING: aif.shg sp, (s6) # encoding: [0x3b,0x30,0x2b,0x1a]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1a2b303b aif.shg sp, (s6)
+
+aif.sbg a6, 0(t4)
+// CHECK-ENCODING: aif.sbg a6, (t4) # encoding: [0x3b,0xb0,0x0e,0x13]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 130eb03b aif.sbg a6, (t4)
+
+aif.shg sp, 0(s6)
+// CHECK-ENCODING: aif.shg sp, (s6) # encoding: [0x3b,0x30,0x2b,0x1a]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1a2b303b aif.shg sp, (s6)
+
+#====----------------------------------------------------------------------===//
+# Scalar local
+#====----------------------------------------------------------------------===//
+
+aif.sbl a3, (fp)
+// CHECK-ENCODING: aif.sbl a3, (s0) # encoding: [0x3b,0x30,0xd4,0x10]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 10d4303b aif.sbl a3, (s0)
+
+aif.shl fp, (s10)
+// CHECK-ENCODING: aif.shl s0, (s10) # encoding: [0x3b,0x30,0x8d,0x18]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 188d303b aif.shl s0, (s10)
+
+aif.sbl a3, 0(fp)
+// CHECK-ENCODING: aif.sbl a3, (s0) # encoding: [0x3b,0x30,0xd4,0x10]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 10d4303b aif.sbl a3, (s0)
+
+aif.shl fp, 0(s10)
+// CHECK-ENCODING: aif.shl s0, (s10) # encoding: [0x3b,0x30,0x8d,0x18]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 188d303b aif.shl s0, (s10)
+
+#====----------------------------------------------------------------------===//
+# CSRs
+#====----------------------------------------------------------------------===//
+
+csrwi aif.matp, 0x1f
+// CHECK-ENCODING: csrwi aif.matp, 31 # encoding: [0x73,0xd0,0x0f,0x7c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.matp' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7c0fd073 csrwi aif.matp, 0x1f
+
+csrwi aif.minstmask, 0x1f
+// CHECK-ENCODING: csrwi aif.minstmask, 31 # encoding: [0x73,0xd0,0xdf,0x7c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.minstmask' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7cdfd073 csrwi aif.minstmask, 0x1f
+
+csrwi aif.minstmatch, 0x1f
+// CHECK-ENCODING: csrwi aif.minstmatch, 31 # encoding: [0x73,0xd0,0xef,0x7c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.minstmatch' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7cefd073 csrwi aif.minstmatch, 0x1f
+
+csrwi aif.cache_invalidate, 0x1f
+// CHECK-ENCODING: csrwi aif.cache_invalidate, 31 # encoding: [0x73,0xd0,0x0f,0x7d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.cache_invalidate' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7d0fd073 csrwi aif.cache_invalidate, 0x1f
+
+csrwi aif.menable_shadows, 0x1f
+// CHECK-ENCODING: csrwi aif.menable_shadows, 31 # encoding: [0x73,0xd0,0x2f,0x7d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.menable_shadows' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7d2fd073 csrwi aif.menable_shadows, 0x1f
+
+csrwi aif.excl_mode, 0x1f
+// CHECK-ENCODING: csrwi aif.excl_mode, 31 # encoding: [0x73,0xd0,0x3f,0x7d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.excl_mode' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7d3fd073 csrwi aif.excl_mode, 0x1f
+
+csrwi aif.mbusaddr, 0x1f
+// CHECK-ENCODING: csrwi aif.mbusaddr, 31 # encoding: [0x73,0xd0,0x5f,0x7d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.mbusaddr' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7d5fd073 csrwi aif.mbusaddr, 0x1f
+
+csrwi aif.mcache_control, 0x1f
+// CHECK-ENCODING: csrwi aif.mcache_control, 31 # encoding: [0x73,0xd0,0x0f,0x7e]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.mcache_control' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7e0fd073 csrwi aif.mcache_control, 0x1f
+
+csrwi aif.evict_sw, 0x1f
+// CHECK-ENCODING: csrwi aif.evict_sw, 31 # encoding: [0x73,0xd0,0x9f,0x7f]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.evict_sw' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7f9fd073 csrwi aif.evict_sw, 0x1f
+
+csrwi aif.flush_sw, 0x1f
+// CHECK-ENCODING: csrwi aif.flush_sw, 31 # encoding: [0x73,0xd0,0xbf,0x7f]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.flush_sw' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7fbfd073 csrwi aif.flush_sw, 0x1f
+
+csrwi aif.lock_sw, 0x1f
+// CHECK-ENCODING: csrwi aif.lock_sw, 31 # encoding: [0x73,0xd0,0xdf,0x7f]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.lock_sw' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7fdfd073 csrwi aif.lock_sw, 0x1f
+
+csrwi aif.unlock_sw, 0x1f
+// CHECK-ENCODING: csrwi aif.unlock_sw, 31 # encoding: [0x73,0xd0,0xff,0x7f]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.unlock_sw' requires 'xaifet' to be enabled
+// CHECK-DISASM: 7fffd073 csrwi aif.unlock_sw, 0x1f
+
+csrwi aif.tensor_reduce, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_reduce, 31 # encoding: [0x73,0xd0,0x0f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_reduce' requires 'xaifet' to be enabled
+// CHECK-DISASM: 800fd073 csrwi aif.tensor_reduce, 0x1f
+
+csrwi aif.tensor_fma, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_fma, 31 # encoding: [0x73,0xd0,0x1f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_fma' requires 'xaifet' to be enabled
+// CHECK-DISASM: 801fd073 csrwi aif.tensor_fma, 0x1f
+
+csrwi aif.tensor_conv_size, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_conv_size, 31 # encoding: [0x73,0xd0,0x2f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_conv_size' requires 'xaifet' to be enabled
+// CHECK-DISASM: 802fd073 csrwi aif.tensor_conv_size, 0x1f
+
+csrwi aif.tensor_conv_ctrl, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_conv_ctrl, 31 # encoding: [0x73,0xd0,0x3f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_conv_ctrl' requires 'xaifet' to be enabled
+// CHECK-DISASM: 803fd073 csrwi aif.tensor_conv_ctrl, 0x1f
+
+csrwi aif.tensor_coop, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_coop, 31 # encoding: [0x73,0xd0,0x4f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_coop' requires 'xaifet' to be enabled
+// CHECK-DISASM: 804fd073 csrwi aif.tensor_coop, 0x1f
+
+csrwi aif.tensor_mask, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_mask, 31 # encoding: [0x73,0xd0,0x5f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_mask' requires 'xaifet' to be enabled
+// CHECK-DISASM: 805fd073 csrwi aif.tensor_mask, 0x1f
+
+csrwi aif.tensor_quant, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_quant, 31 # encoding: [0x73,0xd0,0x6f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_quant' requires 'xaifet' to be enabled
+// CHECK-DISASM: 806fd073 csrwi aif.tensor_quant, 0x1f
+
+csrwi aif.tex_send, 0x1f
+// CHECK-ENCODING: csrwi aif.tex_send, 31 # encoding: [0x73,0xd0,0x7f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tex_send' requires 'xaifet' to be enabled
+// CHECK-DISASM: 807fd073 csrwi aif.tex_send, 0x1f
+
+csrwi aif.tensor_error, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_error, 31 # encoding: [0x73,0xd0,0x8f,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_error' requires 'xaifet' to be enabled
+// CHECK-DISASM: 808fd073 csrwi aif.tensor_error, 0x1f
+
+csrwi aif.ucache_control, 0x1f
+// CHECK-ENCODING: csrwi aif.ucache_control, 31 # encoding: [0x73,0xd0,0x0f,0x81]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.ucache_control' requires 'xaifet' to be enabled
+// CHECK-DISASM: 810fd073 csrwi aif.ucache_control, 0x1f
+
+csrwi aif.prefetch_va, 0x1f
+// CHECK-ENCODING: csrwi aif.prefetch_va, 31 # encoding: [0x73,0xd0,0xff,0x81]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.prefetch_va' requires 'xaifet' to be enabled
+// CHECK-DISASM: 81ffd073 csrwi aif.prefetch_va, 0x1f
+
+csrwi aif.flb, 0x1f
+// CHECK-ENCODING: csrwi aif.flb, 31 # encoding: [0x73,0xd0,0x0f,0x82]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.flb' requires 'xaifet' to be enabled
+// CHECK-DISASM: 820fd073 csrwi aif.flb, 0x1f
+
+csrwi aif.fcc, 0x1f
+// CHECK-ENCODING: csrwi aif.fcc, 31 # encoding: [0x73,0xd0,0x1f,0x82]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.fcc' requires 'xaifet' to be enabled
+// CHECK-DISASM: 821fd073 csrwi aif.fcc, 0x1f
+
+csrwi aif.stall, 0x1f
+// CHECK-ENCODING: csrwi aif.stall, 31 # encoding: [0x73,0xd0,0x2f,0x82]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.stall' requires 'xaifet' to be enabled
+// CHECK-DISASM: 822fd073 csrwi aif.stall, 0x1f
+
+csrwi aif.tensor_wait, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_wait, 31 # encoding: [0x73,0xd0,0x0f,0x83]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_wait' requires 'xaifet' to be enabled
+// CHECK-DISASM: 830fd073 csrwi aif.tensor_wait, 0x1f
+
+csrwi aif.tensor_load, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_load, 31 # encoding: [0x73,0xd0,0xff,0x83]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_load' requires 'xaifet' to be enabled
+// CHECK-DISASM: 83ffd073 csrwi aif.tensor_load, 0x1f
+
+csrwi aif.gsc_progress, 0x1f
+// CHECK-ENCODING: csrwi aif.gsc_progress, 31 # encoding: [0x73,0xd0,0x0f,0x84]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.gsc_progress' requires 'xaifet' to be enabled
+// CHECK-DISASM: 840fd073 csrwi aif.gsc_progress, 0x1f
+
+csrwi aif.tensor_load_l2, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_load_l2, 31 # encoding: [0x73,0xd0,0xff,0x85]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_load_l2' requires 'xaifet' to be enabled
+// CHECK-DISASM: 85ffd073 csrwi aif.tensor_load_l2, 0x1f
+
+csrwi aif.tensor_store, 0x1f
+// CHECK-ENCODING: csrwi aif.tensor_store, 31 # encoding: [0x73,0xd0,0xff,0x87]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.tensor_store' requires 'xaifet' to be enabled
+// CHECK-DISASM: 87ffd073 csrwi aif.tensor_store, 0x1f
+
+csrwi aif.evict_va, 0x1f
+// CHECK-ENCODING: csrwi aif.evict_va, 31 # encoding: [0x73,0xd0,0xff,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.evict_va' requires 'xaifet' to be enabled
+// CHECK-DISASM: 89ffd073 csrwi aif.evict_va, 0x1f
+
+csrwi aif.flush_va, 0x1f
+// CHECK-ENCODING: csrwi aif.flush_va, 31 # encoding: [0x73,0xd0,0xff,0x8b]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.flush_va' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8bffd073 csrwi aif.flush_va, 0x1f
+
+csrwi aif.validation0, 0x1f
+// CHECK-ENCODING: csrwi aif.validation0, 31 # encoding: [0x73,0xd0,0x0f,0x8d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.validation0' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8d0fd073 csrwi aif.validation0, 0x1f
+
+csrwi aif.validation1, 0x1f
+// CHECK-ENCODING: csrwi aif.validation1, 31 # encoding: [0x73,0xd0,0x1f,0x8d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.validation1' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8d1fd073 csrwi aif.validation1, 0x1f
+
+csrwi aif.validation2, 0x1f
+// CHECK-ENCODING: csrwi aif.validation2, 31 # encoding: [0x73,0xd0,0x2f,0x8d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.validation2' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8d2fd073 csrwi aif.validation2, 0x1f
+
+csrwi aif.validation3, 0x1f
+// CHECK-ENCODING: csrwi aif.validation3, 31 # encoding: [0x73,0xd0,0x3f,0x8d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.validation3' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8d3fd073 csrwi aif.validation3, 0x1f
+
+csrwi aif.lock_va, 0x1f
+// CHECK-ENCODING: csrwi aif.lock_va, 31 # encoding: [0x73,0xd0,0xff,0x8d]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.lock_va' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8dffd073 csrwi aif.lock_va, 0x1f
+
+csrwi aif.unlock_va, 0x1f
+// CHECK-ENCODING: csrwi aif.unlock_va, 31 # encoding: [0x73,0xd0,0xff,0x8f]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.unlock_va' requires 'xaifet' to be enabled
+// CHECK-DISASM: 8fffd073 csrwi aif.unlock_va, 0x1f
+
+csrwi aif.portctrl0, 0x1f
+// CHECK-ENCODING: csrwi aif.portctrl0, 31 # encoding: [0x73,0xd0,0xcf,0x9c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portctrl0' requires 'xaifet' to be enabled
+// CHECK-DISASM: 9ccfd073 csrwi aif.portctrl0, 0x1f
+
+csrwi aif.portctrl1, 0x1f
+// CHECK-ENCODING: csrwi aif.portctrl1, 31 # encoding: [0x73,0xd0,0xdf,0x9c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portctrl1' requires 'xaifet' to be enabled
+// CHECK-DISASM: 9cdfd073 csrwi aif.portctrl1, 0x1f
+
+csrwi aif.portctrl2, 0x1f
+// CHECK-ENCODING: csrwi aif.portctrl2, 31 # encoding: [0x73,0xd0,0xef,0x9c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portctrl2' requires 'xaifet' to be enabled
+// CHECK-DISASM: 9cefd073 csrwi aif.portctrl2, 0x1f
+
+csrwi aif.portctrl3, 0x1f
+// CHECK-ENCODING: csrwi aif.portctrl3, 31 # encoding: [0x73,0xd0,0xff,0x9c]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portctrl3' requires 'xaifet' to be enabled
+// CHECK-DISASM: 9cffd073 csrwi aif.portctrl3, 0x1f
+
+csrwi aif.fccnb, 0x1f
+// CHECK-ENCODING: csrwi aif.fccnb, 31 # encoding: [0x73,0xd0,0x0f,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.fccnb' requires 'xaifet' to be enabled
+// CHECK-DISASM: cc0fd073 csrwi aif.fccnb, 0x1f
+
+csrwi aif.porthead0, 0x1f
+// CHECK-ENCODING: csrwi aif.porthead0, 31 # encoding: [0x73,0xd0,0x8f,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.porthead0' requires 'xaifet' to be enabled
+// CHECK-DISASM: cc8fd073 csrwi aif.porthead0, 0x1f
+
+csrwi aif.porthead1, 0x1f
+// CHECK-ENCODING: csrwi aif.porthead1, 31 # encoding: [0x73,0xd0,0x9f,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.porthead1' requires 'xaifet' to be enabled
+// CHECK-DISASM: cc9fd073 csrwi aif.porthead1, 0x1f
+
+csrwi aif.porthead2, 0x1f
+// CHECK-ENCODING: csrwi aif.porthead2, 31 # encoding: [0x73,0xd0,0xaf,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.porthead2' requires 'xaifet' to be enabled
+// CHECK-DISASM: ccafd073 csrwi aif.porthead2, 0x1f
+
+csrwi aif.porthead3, 0x1f
+// CHECK-ENCODING: csrwi aif.porthead3, 31 # encoding: [0x73,0xd0,0xbf,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.porthead3' requires 'xaifet' to be enabled
+// CHECK-DISASM: ccbfd073 csrwi aif.porthead3, 0x1f
+
+csrwi aif.portheadnb0, 0x1f
+// CHECK-ENCODING: csrwi aif.portheadnb0, 31 # encoding: [0x73,0xd0,0xcf,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portheadnb0' requires 'xaifet' to be enabled
+// CHECK-DISASM: cccfd073 csrwi aif.portheadnb0, 0x1f
+
+csrwi aif.portheadnb1, 0x1f
+// CHECK-ENCODING: csrwi aif.portheadnb1, 31 # encoding: [0x73,0xd0,0xdf,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portheadnb1' requires 'xaifet' to be enabled
+// CHECK-DISASM: ccdfd073 csrwi aif.portheadnb1, 0x1f
+
+csrwi aif.portheadnb2, 0x1f
+// CHECK-ENCODING: csrwi aif.portheadnb2, 31 # encoding: [0x73,0xd0,0xef,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portheadnb2' requires 'xaifet' to be enabled
+// CHECK-DISASM: ccefd073 csrwi aif.portheadnb2, 0x1f
+
+csrwi aif.portheadnb3, 0x1f
+// CHECK-ENCODING: csrwi aif.portheadnb3, 31 # encoding: [0x73,0xd0,0xff,0xcc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.portheadnb3' requires 'xaifet' to be enabled
+// CHECK-DISASM: ccffd073 csrwi aif.portheadnb3, 0x1f
+
+csrwi aif.hartid, 0x1f
+// CHECK-ENCODING: csrwi aif.hartid, 31 # encoding: [0x73,0xd0,0x0f,0xcd]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.hartid' requires 'xaifet' to be enabled
+// CHECK-DISASM: cd0fd073 csrwi aif.hartid, 0x1f
+
+csrwi aif.dcache_debug, 0x1f
+// CHECK-ENCODING: csrwi aif.dcache_debug, 31 # encoding: [0x73,0xd0,0x0f,0xfc]
+// CHECK-ERROR: :[[@LINE-2]]:7: error: system register 'aif.dcache_debug' requires 'xaifet' to be enabled
+// CHECK-DISASM: fc0fd073 csrwi aif.dcache_debug, 0x1f
diff --git a/llvm/test/MC/RISCV/xaifet-simd-valid.s b/llvm/test/MC/RISCV/xaifet-simd-valid.s
new file mode 100644
index 0000000000000..541db1272bbfe
--- /dev/null
+++ b/llvm/test/MC/RISCV/xaifet-simd-valid.s
@@ -0,0 +1,673 @@
+# XAIFET - AI Foundry ET SIMD instructions
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xaifet %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xaifet %s \
+# RUN: | llvm-objdump -d --mattr=+xaifet - | FileCheck %s --check-prefix=CHECK-DISASM
+
+aif.bitmixb s7, gp, gp
+// CHECK-ENCODING: aif.bitmixb s7, gp, gp # encoding: [0xbb,0xfb,0x31,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8031fbbb aif.bitmixb s7, gp, gp
+
+aif.cubefaceidx.ps fa0, fs9, ft9
+// CHECK-ENCODING: aif.cubefaceidx.ps fa0, fs9, ft9 # encoding: [0x7b,0x95,0xdc,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 89dc957b aif.cubefaceidx.ps fa0, fs9, ft9
+
+aif.cubeface.ps ft9, fa3, ft10
+// CHECK-ENCODING: aif.cubeface.ps ft9, fa3, ft10 # encoding: [0xfb,0x8e,0xe6,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 89e68efb aif.cubeface.ps ft9, fa3, ft10
+
+aif.cubesgnsc.ps ft9, ft8, fs9
+// CHECK-ENCODING: aif.cubesgnsc.ps ft9, ft8, fs9 # encoding: [0xfb,0x2e,0x9e,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 899e2efb aif.cubesgnsc.ps ft9, ft8, fs9
+
+aif.cubesgntc.ps fs2, ft6, fa6
+// CHECK-ENCODING: aif.cubesgntc.ps fs2, ft6, fa6 # encoding: [0x7b,0x39,0x03,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8903397b aif.cubesgntc.ps fs2, ft6, fa6
+
+#====----------------------------------------------------------------------===//
+# SIMD FP|INT instructions
+#====----------------------------------------------------------------------===//
+
+aif.faddi.pi fa4, ft1, -96
+// CHECK-ENCODING: aif.faddi.pi fa4, ft1, -96 # encoding: [0x3f,0x87,0x00,0xec]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: ec00873f aif.faddi.pi fa4, ft1, -0x60
+
+aif.fadd.pi fs10, fa5, fs8
+// CHECK-ENCODING: aif.fadd.pi fs10, fa5, fs8 # encoding: [0x7b,0x8d,0x87,0x07]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 07878d7b aif.fadd.pi fs10, fa5, fs8
+
+aif.fadd.ps fs0, ft0, fs4, rtz
+// CHECK-ENCODING: aif.fadd.ps fs0, ft0, fs4, rtz # encoding: [0x7b,0x14,0x40,0x01]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0140147b aif.fadd.ps fs0, ft0, fs4, rtz
+
+aif.fandi.pi fa7, fs1, 16
+// CHECK-ENCODING: aif.fandi.pi fa7, fs1, 16 # encoding: [0xbf,0x98,0x04,0x05]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 050498bf aif.fandi.pi fa7, fs1, 0x10
+
+aif.fand.pi ft2, fs8, fa1
+// CHECK-ENCODING: aif.fand.pi ft2, fs8, fa1 # encoding: [0x7b,0x71,0xbc,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 06bc717b aif.fand.pi ft2, fs8, fa1
+
+aif.fbci.pi fs9, 1015523
+// CHECK-ENCODING: aif.fbci.pi fs9, 1015523 # encoding: [0xdf,0x3c,0xee,0xf7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: f7ee3cdf aif.fbci.pi fs9, 0xf7ee3
+
+aif.fbci.ps fs9, 946477
+// CHECK-ENCODING: aif.fbci.ps fs9, 946477 # encoding: [0x9f,0xdc,0x12,0xe7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e712dc9f aif.fbci.ps fs9, 0xe712d
+
+aif.fbcx.ps fa3, s3
+// CHECK-ENCODING: aif.fbcx.ps fa3, s3 # encoding: [0x8b,0xb6,0x09,0x00]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0009b68b aif.fbcx.ps fa3, s3
+
+aif.fbc.ps fs0, 1529(s9)
+// CHECK-ENCODING: aif.fbc.ps fs0, 1529(s9) # encoding: [0x0b,0x84,0x9c,0x5f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 5f9c840b aif.fbc.ps fs0, 0x5f9(s9)
+
+aif.fclass.ps fs0, fs8
+// CHECK-ENCODING: aif.fclass.ps fs0, fs8 # encoding: [0x7b,0x14,0x0c,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e00c147b aif.fclass.ps fs0, fs8
+
+aif.fcmovm.ps ft5, fa7, fs6
+// CHECK-ENCODING: aif.fcmovm.ps ft5, fa7, fs6 # encoding: [0xf7,0x82,0x68,0x01]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 016882f7 aif.fcmovm.ps ft5, fa7, fs6
+
+aif.fcmov.ps fs11, ft1, ft8, fa1
+// CHECK-ENCODING: aif.fcmov.ps fs11, ft1, ft8, fa1 # encoding: [0xbf,0xad,0xc0,0x5d]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 5dc0adbf aif.fcmov.ps fs11, ft1, ft8, fa1
+
+aif.fcvt.f10.ps fa2, ft1
+// CHECK-ENCODING: aif.fcvt.f10.ps fa2, ft1 # encoding: [0x7b,0x86,0xb0,0xd8]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d8b0867b aif.fcvt.f10.ps fa2, ft1
+
+aif.fcvt.f11.ps fa0, ft4
+// CHECK-ENCODING: aif.fcvt.f11.ps fa0, ft4 # encoding: [0x7b,0x05,0x82,0xd8]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d882057b aif.fcvt.f11.ps fa0, ft4
+
+aif.fcvt.f16.ps ft1, fa2
+// CHECK-ENCODING: aif.fcvt.f16.ps ft1, fa2 # encoding: [0xfb,0x00,0x96,0xd8]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d89600fb aif.fcvt.f16.ps ft1, fa2
+
+aif.fcvt.ps.f10 ft5, fa0
+// CHECK-ENCODING: aif.fcvt.ps.f10 ft5, fa0 # encoding: [0xfb,0x02,0x85,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d08502fb aif.fcvt.ps.f10 ft5, fa0
+
+aif.fcvt.ps.f11 fa0, fa6
+// CHECK-ENCODING: aif.fcvt.ps.f11 fa0, fa6 # encoding: [0x7b,0x05,0x98,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d098057b aif.fcvt.ps.f11 fa0, fa6
+
+aif.fcvt.ps.f16 fa4, fs0
+// CHECK-ENCODING: aif.fcvt.ps.f16 fa4, fs0 # encoding: [0x7b,0x07,0xa4,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d0a4077b aif.fcvt.ps.f16 fa4, fs0
+
+aif.fcvt.ps.pw fs0, ft1, rtz
+// CHECK-ENCODING: aif.fcvt.ps.pw fs0, ft1, rtz # encoding: [0x7b,0x94,0x00,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d000947b aif.fcvt.ps.pw fs0, ft1, rtz
+
+aif.fcvt.ps.pwu ft8, ft0, rtz
+// CHECK-ENCODING: aif.fcvt.ps.pwu ft8, ft0, rtz # encoding: [0x7b,0x1e,0x10,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d0101e7b aif.fcvt.ps.pwu ft8, ft0, rtz
+
+aif.fcvt.ps.rast ft7, fa0
+// CHECK-ENCODING: aif.fcvt.ps.rast ft7, fa0 # encoding: [0xfb,0x03,0x25,0xd0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d02503fb aif.fcvt.ps.rast ft7, fa0
+
+aif.fcvt.ps.sn16 ft11, fa2
+// CHECK-ENCODING: aif.fcvt.ps.sn16 ft11, fa2 # encoding: [0xfb,0x0f,0x96,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d1960ffb aif.fcvt.ps.sn16 ft11, fa2
+
+aif.fcvt.ps.sn8 fs1, ft2
+// CHECK-ENCODING: aif.fcvt.ps.sn8 fs1, ft2 # encoding: [0xfb,0x04,0xb1,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d1b104fb aif.fcvt.ps.sn8 fs1, ft2
+
+aif.fcvt.ps.un10 fs0, fs11
+// CHECK-ENCODING: aif.fcvt.ps.un10 fs0, fs11 # encoding: [0x7b,0x84,0x2d,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d12d847b aif.fcvt.ps.un10 fs0, fs11
+
+aif.fcvt.ps.un16 fa7, ft5
+// CHECK-ENCODING: aif.fcvt.ps.un16 fa7, ft5 # encoding: [0xfb,0x88,0x12,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d11288fb aif.fcvt.ps.un16 fa7, ft5
+
+aif.fcvt.ps.un2 fs0, fa7
+// CHECK-ENCODING: aif.fcvt.ps.un2 fs0, fa7 # encoding: [0x7b,0x84,0x78,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d178847b aif.fcvt.ps.un2 fs0, fa7
+
+aif.fcvt.ps.un24 ft6, ft1
+// CHECK-ENCODING: aif.fcvt.ps.un24 ft6, ft1 # encoding: [0x7b,0x83,0x00,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d100837b aif.fcvt.ps.un24 ft6, ft1
+
+aif.fcvt.ps.un8 fa3, fa4
+// CHECK-ENCODING: aif.fcvt.ps.un8 fa3, fa4 # encoding: [0xfb,0x06,0x37,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d13706fb aif.fcvt.ps.un8 fa3, fa4
+
+aif.fcvt.pwu.ps ft10, ft1, rup
+// CHECK-ENCODING: aif.fcvt.pwu.ps ft10, ft1, rup # encoding: [0x7b,0xbf,0x10,0xc0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c010bf7b aif.fcvt.pwu.ps ft10, ft1, rup
+
+aif.fcvt.pw.ps fs6, ft5, rup
+// CHECK-ENCODING: aif.fcvt.pw.ps fs6, ft5, rup # encoding: [0x7b,0xbb,0x02,0xc0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c002bb7b aif.fcvt.pw.ps fs6, ft5, rup
+
+aif.fcvt.rast.ps ft11, fs7
+// CHECK-ENCODING: aif.fcvt.rast.ps ft11, fs7 # encoding: [0xfb,0x8f,0x2b,0xc0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c02b8ffb aif.fcvt.rast.ps ft11, fs7
+
+aif.fcvt.sn16.ps ft1, fs7
+// CHECK-ENCODING: aif.fcvt.sn16.ps ft1, fs7 # encoding: [0xfb,0x80,0x9b,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d99b80fb aif.fcvt.sn16.ps ft1, fs7
+
+aif.fcvt.sn8.ps fs3, ft5
+// CHECK-ENCODING: aif.fcvt.sn8.ps fs3, ft5 # encoding: [0xfb,0x89,0xb2,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d9b289fb aif.fcvt.sn8.ps fs3, ft5
+
+aif.fcvt.un10.ps ft5, fa6
+// CHECK-ENCODING: aif.fcvt.un10.ps ft5, fa6 # encoding: [0xfb,0x02,0x28,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d92802fb aif.fcvt.un10.ps ft5, fa6
+
+aif.fcvt.un16.ps fs9, ft6
+// CHECK-ENCODING: aif.fcvt.un16.ps fs9, ft6 # encoding: [0xfb,0x0c,0x13,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d9130cfb aif.fcvt.un16.ps fs9, ft6
+
+aif.fcvt.un24.ps fs8, ft8
+// CHECK-ENCODING: aif.fcvt.un24.ps fs8, ft8 # encoding: [0x7b,0x0c,0x0e,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d90e0c7b aif.fcvt.un24.ps fs8, ft8
+
+aif.fcvt.un2.ps fa0, fa3
+// CHECK-ENCODING: aif.fcvt.un2.ps fa0, fa3 # encoding: [0x7b,0x85,0x76,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d976857b aif.fcvt.un2.ps fa0, fa3
+
+aif.fcvt.un8.ps fa0, ft2
+// CHECK-ENCODING: aif.fcvt.un8.ps fa0, ft2 # encoding: [0x7b,0x05,0x31,0xd9]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d931057b aif.fcvt.un8.ps fa0, ft2
+
+aif.fdivu.pi fa1, fa5, fa2
+// CHECK-ENCODING: aif.fdivu.pi fa1, fa5, fa2 # encoding: [0xfb,0x95,0xc7,0x1e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1ec795fb aif.fdivu.pi fa1, fa5, fa2
+
+aif.fdiv.pi ft3, fa0, fs4
+// CHECK-ENCODING: aif.fdiv.pi ft3, fa0, fs4 # encoding: [0xfb,0x01,0x45,0x1f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1f4501fb aif.fdiv.pi ft3, fa0, fs4
+
+aif.fdiv.ps fs10, ft5, fs11, rdn
+// CHECK-ENCODING: aif.fdiv.ps fs10, ft5, fs11, rdn # encoding: [0x7b,0xad,0xb2,0x19]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 19b2ad7b aif.fdiv.ps fs10, ft5, fs11, rdn
+
+aif.feqm.ps m4, ft5, ft8
+// CHECK-ENCODING: aif.feqm.ps m4, ft5, ft8 # encoding: [0x7b,0xe2,0xc2,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a1c2e27b aif.feqm.ps m4, ft5, ft8
+
+aif.feq.pi ft10, fa1, fs0
+// CHECK-ENCODING: aif.feq.pi ft10, fa1, fs0 # encoding: [0x7b,0xaf,0x85,0xa6]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a685af7b aif.feq.pi ft10, fa1, fs0
+
+aif.feq.ps fa5, ft4, fs2
+// CHECK-ENCODING: aif.feq.ps fa5, ft4, fs2 # encoding: [0xfb,0x27,0x22,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a12227fb aif.feq.ps fa5, ft4, fs2
+
+aif.fexp.ps fs10, ft3
+// CHECK-ENCODING: aif.fexp.ps fs10, ft3 # encoding: [0x7b,0x8d,0x41,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 58418d7b aif.fexp.ps fs10, ft3
+
+aif.flog.ps fa0, fs10
+// CHECK-ENCODING: aif.flog.ps fa0, fs10 # encoding: [0x7b,0x05,0x3d,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 583d057b aif.flog.ps fa0, fs10
+
+aif.ffrc.ps fs9, ft8
+// CHECK-ENCODING: aif.ffrc.ps fs9, ft8 # encoding: [0xfb,0x0c,0x2e,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 582e0cfb aif.ffrc.ps fs9, ft8
+
+aif.fg32b.ps fa2, a0, (s0)
+// CHECK-ENCODING: aif.fg32b.ps fa2, a0, (s0) # encoding: [0x0b,0x16,0x85,0x08]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0885160b aif.fg32b.ps fa2, a0, (s0)
+
+aif.fg32h.ps ft10, s6, (s9)
+// CHECK-ENCODING: aif.fg32h.ps ft10, s6, (s9) # encoding: [0x0b,0x1f,0x9b,0x11]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 119b1f0b aif.fg32h.ps ft10, s6, (s9)
+
+aif.fg32w.ps fs5, ra, (a0)
+// CHECK-ENCODING: aif.fg32w.ps fs5, ra, (a0) # encoding: [0x8b,0x9a,0xa0,0x20]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 20a09a8b aif.fg32w.ps fs5, ra, (a0)
+
+aif.fgb.ps fs11, ft7, (s4)
+// CHECK-ENCODING: aif.fgb.ps fs11, ft7, (s4) # encoding: [0x8b,0x9d,0x43,0x49]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 49439d8b aif.fgb.ps fs11, ft7, (s4)
+
+aif.fgh.ps ft3, ft7, (t5)
+// CHECK-ENCODING: aif.fgh.ps ft3, ft7, (t5) # encoding: [0x8b,0x91,0xe3,0x51]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 51e3918b aif.fgh.ps ft3, ft7, (t5)
+
+aif.fgw.ps fs10, fa7, (s3)
+// CHECK-ENCODING: aif.fgw.ps fs10, fa7, (s3) # encoding: [0x0b,0x9d,0x38,0x61]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 61389d0b aif.fgw.ps fs10, fa7, (s3)
+
+aif.flem.ps m6, ft4, ft3
+// CHECK-ENCODING: aif.flem.ps m6, ft4, ft3 # encoding: [0x7b,0x43,0x32,0xa0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a032437b aif.flem.ps m6, ft4, ft3
+
+aif.fle.pi ft2, fs3, fa7
+// CHECK-ENCODING: aif.fle.pi ft2, fs3, fa7 # encoding: [0x7b,0x81,0x19,0xa7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a719817b aif.fle.pi ft2, fs3, fa7
+
+aif.fle.ps ft9, fs11, fa1
+// CHECK-ENCODING: aif.fle.ps ft9, fs11, fa1 # encoding: [0xfb,0x8e,0xbd,0xa0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a0bd8efb aif.fle.ps ft9, fs11, fa1
+
+aif.flq2 fa5, -2020(sp)
+// CHECK-ENCODING: aif.flq2 fa5, -2020(sp) # encoding: [0x87,0x57,0xc1,0x81]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 81c15787 aif.flq2 fa5, -0x7e4(sp)
+
+aif.fltm.pi m0, ft3, fs1
+// CHECK-ENCODING: aif.fltm.pi m0, ft3, fs1 # encoding: [0x7b,0x80,0x91,0x3e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 3e91807b aif.fltm.pi m0, ft3, fs1
+
+aif.fltm.ps m6, ft2, fa3
+// CHECK-ENCODING: aif.fltm.ps m6, ft2, fa3 # encoding: [0x7b,0x53,0xd1,0xa0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a0d1537b aif.fltm.ps m6, ft2, fa3
+
+aif.fltu.pi ft5, fa1, fs10
+// CHECK-ENCODING: aif.fltu.pi ft5, fa1, fs10 # encoding: [0xfb,0xb2,0xa5,0xa7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a7a5b2fb aif.fltu.pi ft5, fa1, fs10
+
+aif.flt.pi ft11, fa4, fs8
+// CHECK-ENCODING: aif.flt.pi ft11, fa4, fs8 # encoding: [0xfb,0x1f,0x87,0xa7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a7871ffb aif.flt.pi ft11, fa4, fs8
+
+aif.flt.ps fs11, fs3, fs5
+// CHECK-ENCODING: aif.flt.ps fs11, fs3, fs5 # encoding: [0xfb,0x9d,0x59,0xa1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a1599dfb aif.flt.ps fs11, fs3, fs5
+
+aif.flw.ps ft9, 1224(s5)
+// CHECK-ENCODING: aif.flw.ps ft9, 1224(s5) # encoding: [0x8b,0xae,0x8a,0x4c]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 4c8aae8b aif.flw.ps ft9, 0x4c8(s5)
+
+aif.fmadd.ps fs0, fs2, ft8, ft8, rmm
+// CHECK-ENCODING: aif.fmadd.ps fs0, fs2, ft8, ft8, rmm # encoding: [0x5b,0x44,0xc9,0xe1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e1c9445b aif.fmadd.ps fs0, fs2, ft8, ft8, rmm
+
+aif.fmaxu.pi ft10, fs3, fs11
+// CHECK-ENCODING: aif.fmaxu.pi ft10, fs3, fs11 # encoding: [0x7b,0xbf,0xb9,0x2f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2fb9bf7b aif.fmaxu.pi ft10, fs3, fs11
+
+aif.fmax.pi ft3, fs1, fs6
+// CHECK-ENCODING: aif.fmax.pi ft3, fs1, fs6 # encoding: [0xfb,0x91,0x64,0x2f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2f6491fb aif.fmax.pi ft3, fs1, fs6
+
+aif.fmax.ps fa0, fs2, ft3
+// CHECK-ENCODING: aif.fmax.ps fa0, fs2, ft3 # encoding: [0x7b,0x15,0x39,0x28]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2839157b aif.fmax.ps fa0, fs2, ft3
+
+aif.fminu.pi ft5, ft2, ft2
+// CHECK-ENCODING: aif.fminu.pi ft5, ft2, ft2 # encoding: [0xfb,0x22,0x21,0x2e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2e2122fb aif.fminu.pi ft5, ft2, ft2
+
+aif.fmin.pi fs10, fs10, fs3
+// CHECK-ENCODING: aif.fmin.pi fs10, fs10, fs3 # encoding: [0x7b,0x0d,0x3d,0x2f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 2f3d0d7b aif.fmin.pi fs10, fs10, fs3
+
+aif.fmin.ps fa1, ft5, ft5
+// CHECK-ENCODING: aif.fmin.ps fa1, ft5, ft5 # encoding: [0xfb,0x85,0x52,0x28]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 285285fb aif.fmin.ps fa1, ft5, ft5
+
+aif.fmsub.ps fs0, fs7, fs6, ft3, rmm
+// CHECK-ENCODING: aif.fmsub.ps fs0, fs7, fs6, ft3, rmm # encoding: [0x5b,0xc4,0x6b,0x1b]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1b6bc45b aif.fmsub.ps fs0, fs7, fs6, ft3, rmm
+
+aif.fmulhu.pi ft6, fs7, fs4
+// CHECK-ENCODING: aif.fmulhu.pi ft6, fs7, fs4 # encoding: [0x7b,0xa3,0x4b,0x17]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 174ba37b aif.fmulhu.pi ft6, fs7, fs4
+
+aif.fmulh.pi fa3, fa3, fs1
+// CHECK-ENCODING: aif.fmulh.pi fa3, fa3, fs1 # encoding: [0xfb,0x96,0x96,0x16]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 169696fb aif.fmulh.pi fa3, fa3, fs1
+
+aif.fmul.pi ft4, ft7, ft4
+// CHECK-ENCODING: aif.fmul.pi ft4, ft7, ft4 # encoding: [0x7b,0x82,0x43,0x16]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1643827b aif.fmul.pi ft4, ft7, ft4
+
+aif.fmul.ps fa5, fa2, fs10, rtz
+// CHECK-ENCODING: aif.fmul.ps fa5, fa2, fs10, rtz # encoding: [0xfb,0x17,0xa6,0x11]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 11a617fb aif.fmul.ps fa5, fa2, fs10, rtz
+
+aif.fmvs.x.ps fp, fs0, 6
+// CHECK-ENCODING: aif.fmvs.x.ps s0, fs0, 6 # encoding: [0x7b,0x24,0x64,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e064247b aif.fmvs.x.ps s0, fs0, 0x6
+
+aif.fmvz.x.ps a5, ft6, 6
+// CHECK-ENCODING: aif.fmvz.x.ps a5, ft6, 6 # encoding: [0xfb,0x07,0x63,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e06307fb aif.fmvz.x.ps a5, ft6, 0x6
+
+aif.fnmadd.ps ft10, ft8, fs5, fs3, rdn
+// CHECK-ENCODING: aif.fnmadd.ps ft10, ft8, fs5, fs3, rdn # encoding: [0x5b,0x2f,0x5e,0x9f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 9f5e2f5b aif.fnmadd.ps ft10, ft8, fs5, fs3, rdn
+
+aif.fnmsub.ps ft0, ft11, fs7, fa5, rtz
+// CHECK-ENCODING: aif.fnmsub.ps ft0, ft11, fs7, fa5, rtz # encoding: [0x5b,0x90,0x7f,0x7d]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 7d7f905b aif.fnmsub.ps ft0, ft11, fs7, fa5, rtz
+
+aif.fnot.pi fs10, fs6
+// CHECK-ENCODING: aif.fnot.pi fs10, fs6 # encoding: [0x7b,0x2d,0x0b,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 060b2d7b aif.fnot.pi fs10, fs6
+
+aif.for.pi ft10, fa0, fa4
+// CHECK-ENCODING: aif.for.pi ft10, fa0, fa4 # encoding: [0x7b,0x6f,0xe5,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 06e56f7b aif.for.pi ft10, fa0, fa4
+
+aif.fpackrepb.pi ft8, fs11
+// CHECK-ENCODING: aif.fpackrepb.pi ft8, fs11 # encoding: [0x7b,0x8e,0x0d,0x26]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 260d8e7b aif.fpackrepb.pi ft8, fs11
+
+aif.fpackreph.pi ft2, ft10
+// CHECK-ENCODING: aif.fpackreph.pi ft2, ft10 # encoding: [0x7b,0x11,0x0f,0x26]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 260f117b aif.fpackreph.pi ft2, ft10
+
+aif.frcp_fix.rast ft3, fs0, fa1
+// CHECK-ENCODING: aif.frcp_fix.rast ft3, fs0, fa1 # encoding: [0xfb,0x01,0xb4,0x30]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 30b401fb aif.frcp_fix.rast ft3, fs0, fa1
+
+aif.frcp.ps ft11, fs2
+// CHECK-ENCODING: aif.frcp.ps ft11, fs2 # encoding: [0xfb,0x0f,0x79,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 58790ffb aif.frcp.ps ft11, fs2
+
+aif.fremu.pi ft4, ft4, ft1
+// CHECK-ENCODING: aif.fremu.pi ft4, ft4, ft1 # encoding: [0x7b,0x32,0x12,0x1e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1e12327b aif.fremu.pi ft4, ft4, ft1
+
+aif.frem.pi fa2, fs10, ft1
+// CHECK-ENCODING: aif.frem.pi fa2, fs10, ft1 # encoding: [0x7b,0x26,0x1d,0x1e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 1e1d267b aif.frem.pi fa2, fs10, ft1
+
+aif.fround.ps fa3, fs7, rtz
+// CHECK-ENCODING: aif.fround.ps fa3, fs7, rtz # encoding: [0xfb,0x96,0x1b,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 581b96fb aif.fround.ps fa3, fs7, rtz
+
+aif.frsq.ps fs1, fs1
+// CHECK-ENCODING: aif.frsq.ps fs1, fs1 # encoding: [0xfb,0x84,0x84,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 588484fb aif.frsq.ps fs1, fs1
+
+aif.fsat8.pi ft1, fs7
+// CHECK-ENCODING: aif.fsat8.pi ft1, fs7 # encoding: [0xfb,0xb0,0x0b,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 060bb0fb aif.fsat8.pi ft1, fs7
+
+aif.fsatu8.pi fa1, fa2
+// CHECK-ENCODING: aif.fsatu8.pi fa1, fa2 # encoding: [0xfb,0x35,0x16,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 061635fb aif.fsatu8.pi fa1, fa2
+
+aif.fsc32b.ps ft7, gp, (s3)
+// CHECK-ENCODING: aif.fsc32b.ps ft7, gp, (s3) # encoding: [0x8b,0x93,0x31,0x89]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 8931938b aif.fsc32b.ps ft7, gp, (s3)
+
+aif.fsc32h.ps fa3, s6, (tp)
+// CHECK-ENCODING: aif.fsc32h.ps fa3, s6, (tp) # encoding: [0x8b,0x16,0x4b,0x90]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 904b168b aif.fsc32h.ps fa3, s6, (tp)
+
+aif.fsc32w.ps ft0, t5, (a0)
+// CHECK-ENCODING: aif.fsc32w.ps ft0, t5, (a0) # encoding: [0x0b,0x10,0xaf,0xa0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a0af100b aif.fsc32w.ps ft0, t5, (a0)
+
+aif.fscb.ps ft9, ft1, (zero)
+// CHECK-ENCODING: aif.fscb.ps ft9, ft1, (zero) # encoding: [0x8b,0x9e,0x00,0xc8]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: c8009e8b aif.fscb.ps ft9, ft1, (zero)
+
+aif.fsch.ps fs2, fa0, (t5)
+// CHECK-ENCODING: aif.fsch.ps fs2, fa0, (t5) # encoding: [0x0b,0x19,0xe5,0xd1]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d1e5190b aif.fsch.ps fs2, fa0, (t5)
+
+aif.fscw.ps ft1, ft0, (a0)
+// CHECK-ENCODING: aif.fscw.ps ft1, ft0, (a0) # encoding: [0x8b,0x10,0xa0,0xe0]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e0a0108b aif.fscw.ps ft1, ft0, (a0)
+
+aif.fsetm.pi m0, fa5
+// CHECK-ENCODING: aif.fsetm.pi m0, fa5 # encoding: [0x7b,0xc0,0x07,0xa6]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: a607c07b aif.fsetm.pi m0, fa5
+
+aif.fsgnjn.ps ft6, fs10, ft2
+// CHECK-ENCODING: aif.fsgnjn.ps ft6, fs10, ft2 # encoding: [0x7b,0x13,0x2d,0x20]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 202d137b aif.fsgnjn.ps ft6, fs10, ft2
+
+aif.fsgnjx.ps ft9, fs2, fs0
+// CHECK-ENCODING: aif.fsgnjx.ps ft9, fs2, fs0 # encoding: [0xfb,0x2e,0x89,0x20]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 20892efb aif.fsgnjx.ps ft9, fs2, fs0
+
+aif.fsgnj.ps fs3, fa7, ft0
+// CHECK-ENCODING: aif.fsgnj.ps fs3, fa7, ft0 # encoding: [0xfb,0x89,0x08,0x20]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 200889fb aif.fsgnj.ps fs3, fa7, ft0
+
+aif.fsin.ps ft2, ft4
+// CHECK-ENCODING: aif.fsin.ps ft2, ft4 # encoding: [0x7b,0x01,0x62,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 5862017b aif.fsin.ps ft2, ft4
+
+aif.fslli.pi ft1, fs10, 25
+// CHECK-ENCODING: aif.fslli.pi ft1, fs10, 25 # encoding: [0xfb,0x10,0x9d,0x4f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 4f9d10fb aif.fslli.pi ft1, fs10, 0x19
+
+aif.fsll.pi ft3, ft9, fa7
+// CHECK-ENCODING: aif.fsll.pi ft3, ft9, fa7 # encoding: [0xfb,0x91,0x1e,0x07]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 071e91fb aif.fsll.pi ft3, ft9, fa7
+
+aif.fsq2 fa4, -1100(s5)
+// CHECK-ENCODING: aif.fsq2 fa4, -1100(s5) # encoding: [0x27,0xda,0xea,0xba]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: baeada27 aif.fsq2 fa4, -0x44c(s5)
+
+aif.fsqrt.ps ft2, fs11
+// CHECK-ENCODING: aif.fsqrt.ps ft2, fs11 # encoding: [0x7b,0x81,0x0d,0x58]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 580d817b aif.fsqrt.ps ft2, fs11
+
+aif.fsrai.pi ft1, fs5, 5
+// CHECK-ENCODING: aif.fsrai.pi ft1, fs5, 5 # encoding: [0xfb,0xf0,0x5a,0x4e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 4e5af0fb aif.fsrai.pi ft1, fs5, 0x5
+
+aif.fsra.pi fs1, ft11, ft2
+// CHECK-ENCODING: aif.fsra.pi fs1, ft11, ft2 # encoding: [0xfb,0xd4,0x2f,0x0e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0e2fd4fb aif.fsra.pi fs1, ft11, ft2
+
+aif.fsrli.pi fs0, fa4, 5
+// CHECK-ENCODING: aif.fsrli.pi fs0, fa4, 5 # encoding: [0x7b,0x54,0x57,0x4e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 4e57547b aif.fsrli.pi fs0, fa4, 0x5
+
+aif.fsrl.pi fa2, fs0, fa4
+// CHECK-ENCODING: aif.fsrl.pi fa2, fs0, fa4 # encoding: [0x7b,0x56,0xe4,0x06]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 06e4567b aif.fsrl.pi fa2, fs0, fa4
+
+aif.fsub.pi ft0, ft10, ft9
+// CHECK-ENCODING: aif.fsub.pi ft0, ft10, ft9 # encoding: [0x7b,0x00,0xdf,0x0f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0fdf007b aif.fsub.pi ft0, ft10, ft9
+
+aif.fsub.ps ft2, ft2, fs8, dyn
+// CHECK-ENCODING: aif.fsub.ps ft2, ft2, fs8 # encoding: [0x7b,0x71,0x81,0x09]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 0981717b aif.fsub.ps ft2, ft2, fs8
+
+aif.fswizz.ps ft3, fa4, 188
+// CHECK-ENCODING: aif.fswizz.ps ft3, fa4, 188 # encoding: [0xfb,0x41,0x77,0xe7]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: e77741fb aif.fswizz.ps ft3, fa4, 0xbc
+
+aif.fsw.ps fs4, 1772(a1)
+// CHECK-ENCODING: aif.fsw.ps fs4, 1772(a1) # encoding: [0x0b,0xe6,0x45,0x6f]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6f45e60b aif.fsw.ps fs4, 0x6ec(a1)
+
+aif.fxor.pi ft10, fa6, fs6
+// CHECK-ENCODING: aif.fxor.pi ft10, fa6, fs6 # encoding: [0x7b,0x4f,0x68,0x07]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 07684f7b aif.fxor.pi ft10, fa6, fs6
+
+#====----------------------------------------------------------------------===//
+# Masking instructions
+#====----------------------------------------------------------------------===//
+
+aif.maskand m3, m5, m0
+// CHECK-ENCODING: aif.maskand m3, m5, m0 # encoding: [0xfb,0xf1,0x02,0x66]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6602f1fb aif.maskand m3, m5, m0
+
+aif.masknot m6, m6
+// CHECK-ENCODING: aif.masknot m6, m6 # encoding: [0x7b,0x23,0x03,0x66]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6603237b aif.masknot m6, m6
+
+aif.maskor m0, m7, m5
+// CHECK-ENCODING: aif.maskor m0, m7, m5 # encoding: [0x7b,0xe0,0x53,0x66]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6653e07b aif.maskor m0, m7, m5
+
+aif.maskpopc s9, m7
+// CHECK-ENCODING: aif.maskpopc s9, m7 # encoding: [0xfb,0x8c,0x03,0x52]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 52038cfb aif.maskpopc s9, m7
+
+aif.maskpopcz s10, m4
+// CHECK-ENCODING: aif.maskpopcz s10, m4 # encoding: [0x7b,0x0d,0x02,0x54]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 54020d7b aif.maskpopcz s10, m4
+
+aif.maskpopc.rast m1, m3, m2, 2
+// CHECK-ENCODING: aif.maskpopc.rast m1, m3, m2, 2 # encoding: [0xfb,0x80,0x29,0x5e]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 5e2980fb aif.maskpopc.rast m1, m3, m2, 0x2
+
+aif.maskxor m6, m6, m2
+// CHECK-ENCODING: aif.maskxor m6, m6, m2 # encoding: [0x7b,0x43,0x23,0x66]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 6623437b aif.maskxor m6, m6, m2
+
+aif.mova.m.x t1
+// CHECK-ENCODING: aif.mova.m.x t1 # encoding: [0x7b,0x10,0x03,0xd6]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d603107b aif.mova.m.x t1
+
+aif.mova.x.m s1
+// CHECK-ENCODING: aif.mova.x.m s1 # encoding: [0xfb,0x04,0x00,0xd6]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: d60004fb aif.mova.x.m s1
+
+aif.mov.m.x m3, t0, 201
+// CHECK-ENCODING: aif.mov.m.x m3, t0, 201 # encoding: [0xfb,0x91,0x92,0x57]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 579291fb aif.mov.m.x m3, t0, 0xc9
+
+aif.packb a1, a2, a4
+// CHECK-ENCODING: aif.packb a1, a2, a4 # encoding: [0xbb,0x65,0xe6,0x80]
+// CHECK-ERROR: :[[@LINE-2]]:1: error: instruction requires the following: 'XAIFET' (AI Foundry ET Extension)
+// CHECK-DISASM: 80e665bb aif.packb a1, a2, a4
More information about the cfe-commits
mailing list