[clang] [CIR][X86]Implement handling for shiftleft/shiftright builtins in CIR (PR #175049)
Priyanshu Kumar via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 8 11:02:59 PST 2026
https://github.com/Priyanshu3820 updated https://github.com/llvm/llvm-project/pull/175049
>From 7f91722ebc48cbe146e6e19194188c37a3a79f24 Mon Sep 17 00:00:00 2001
From: Priyanshu Kumar <10b.priyanshu at gmail.com>
Date: Thu, 8 Jan 2026 18:43:51 +0000
Subject: [PATCH 1/2] Implement handling for msvc specific shift builtins in
CIR
---
clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 22 +++++--
.../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 60 +++++++++++++++++++
2 files changed, 78 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 29a89e46bafba..6beb8106b267c 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -1906,10 +1906,24 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
}
case X86::BI__shiftleft128:
case X86::BI__shiftright128: {
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented X86 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
+ // Determine if left or right shift
+ bool isRight = (builtinID == X86::BI__shiftright128);
+
+ // Flip low/high ops and zero-extend amount to matching type.
+ // shiftleft128(Low, High, Amt) -> fshl(High, Low, Amt)
+ // shiftright128(Low, High, Amt) -> fshr(High, Low, Amt)
+ std::swap(ops[0], ops[1]);
+
+ // Zero-extend shift amount to i64 if needed
+ auto amtTy = mlir::dyn_cast<cir::IntType>(ops[2].getType());
+ auto i64Ty = builder.getUInt64Ty();
+
+ if (amtTy != i64Ty) {
+ ops[2] = builder.createIntCast(ops[2], i64Ty);
+ }
+
+ return emitX86FunnelShift(builder, getLoc(expr->getExprLoc()), ops[0],
+ ops[1], ops[2], isRight);
}
case X86::BI_ReadWriteBarrier:
case X86::BI_ReadBarrier:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
new file mode 100644
index 0000000000000..28fad3a68e968
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
@@ -0,0 +1,60 @@
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \
+// RUN: -Oz -fclangir -emit-cir %s -o %t.cir
+// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR
+
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \
+// RUN: -Oz -fclangir -emit-llvm %s -o %t.ll
+// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM
+
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \
+// RUN: -Oz -emit-llvm %s -o %t.ll
+// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG
+
+unsigned __int64 __shiftleft128(unsigned __int64 low, unsigned __int64 high,
+ unsigned char shift);
+unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high,
+ unsigned char shift);
+
+unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h,
+ unsigned char d) {
+ // CIR-LABEL: cir.func{{.*}}@test_shiftleft128
+ // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}})
+ // CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i
+ // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
+ // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
+// CIR: cir.return
+
+// LLVM-LABEL: define dso_local i64 @test_shiftleft128(i64 %0, i64 %1, i8 %2)
+// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %2 to i64
+// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %1, i64 %0, i64 [[TMP1]])
+// LLVM-NEXT: ret i64 [[TMP2]]
+
+// OGCG-LABEL: define dso_local noundef i64 @test_shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d)
+// OGCG-NEXT: entry:
+// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64
+// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 [[TMP0]])
+// OGCG-NEXT: ret i64 [[TMP1]]
+return __shiftleft128(l, h, d);
+}
+
+unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h,
+ unsigned char d) {
+ // CIR-LABEL: cir.func{{.*}}@test_shiftright128
+ // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}})
+// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i
+// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
+// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshr" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
+// CIR: cir.return
+
+// LLVM-LABEL: define dso_local i64 @test_shiftright128(i64 %0, i64 %1, i8 %2)
+// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %2 to i64
+// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %1, i64 %0, i64 [[TMP1]])
+// LLVM-NEXT: ret i64 [[TMP2]]
+
+// OGCG-LABEL: define dso_local noundef i64 @test_shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d)
+// OGCG-NEXT: entry:
+// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64
+// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 [[TMP0]])
+// OGCG-NEXT: ret i64 [[TMP1]]
+return __shiftright128(l, h, d);
+}
>From ca47d3a8ab294c44dd665986d96a5f3461d939fd Mon Sep 17 00:00:00 2001
From: Priyanshu Kumar <10b.priyanshu at gmail.com>
Date: Thu, 8 Jan 2026 19:02:15 +0000
Subject: [PATCH 2/2] Fix formatting and match existing function pattern
---
clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 2 +-
.../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 26 +++++++++----------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 6beb8106b267c..b222355e23f42 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -1915,7 +1915,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
std::swap(ops[0], ops[1]);
// Zero-extend shift amount to i64 if needed
- auto amtTy = mlir::dyn_cast<cir::IntType>(ops[2].getType());
+ auto amtTy = mlir::cast<cir::IntType>(ops[2].getType());
auto i64Ty = builder.getUInt64Ty();
if (amtTy != i64Ty) {
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
index 28fad3a68e968..5265537e5be7c 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
@@ -15,13 +15,11 @@ unsigned __int64 __shiftleft128(unsigned __int64 low, unsigned __int64 high,
unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high,
unsigned char shift);
-unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h,
- unsigned char d) {
- // CIR-LABEL: cir.func{{.*}}@test_shiftleft128
- // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}})
- // CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i
- // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
- // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
+// CIR-LABEL: cir.func{{.*}}@test_shiftleft128
+// CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}})
+// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i
+// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
+// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
// CIR: cir.return
// LLVM-LABEL: define dso_local i64 @test_shiftleft128(i64 %0, i64 %1, i8 %2)
@@ -34,13 +32,13 @@ unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h,
// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64
// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 [[TMP0]])
// OGCG-NEXT: ret i64 [[TMP1]]
-return __shiftleft128(l, h, d);
+unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h,
+ unsigned char d) {
+ return __shiftleft128(l, h, d);
}
-unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h,
- unsigned char d) {
- // CIR-LABEL: cir.func{{.*}}@test_shiftright128
- // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}})
+// CIR-LABEL: cir.func{{.*}}@test_shiftright128
+// CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}})
// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i
// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i
// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshr" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i
@@ -56,5 +54,7 @@ unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h,
// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64
// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 [[TMP0]])
// OGCG-NEXT: ret i64 [[TMP1]]
-return __shiftright128(l, h, d);
+unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h,
+ unsigned char d) {
+ return __shiftright128(l, h, d);
}
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