[clang] [CIR][AArch64] Add lowering for unpredicated svdup builtins (PR #174433)

[Andrzej Warzyński via cfe-commits]

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@@ -65,7 +110,26 @@ CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID,
 
   assert(!cir::MissingFeatures::aarch64SVEIntrinsics());
 
+  auto *builtinIntrInfo = findARMVectorIntrinsicInMap(
+      aarch64SVEIntrinsicMap, builtinID, aarch64SVEIntrinsicsProvenSorted);
+
+  // The operands of the builtin call
+  llvm::SmallVector<mlir::Value> ops;
+
+  for (const auto *argExpr : expr->arguments())
+    ops.push_back(emitScalarExpr(argExpr));
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banach-space wrote:

Agreed, let me fix that.

I've hit one issue though. [`converType`](https://github.com/llvm/llvm-project/blob/188507e54218c91832714fc50b24bd2fc2fd9383/clang/lib/CIR/CodeGen/CIRGenTypes.cpp?plain=1#L280-L596) does not handle these SVE types:
https://github.com/llvm/llvm-project/blob/188507e54218c91832714fc50b24bd2fc2fd9383/clang/include/clang/Basic/AArch64ACLETypes.def?plain=1#L175-L239

I don't need those types for _this_ PR, so would rather avoid adding them here. However, without a proper conversion I am unable to implement a logic similar to this:
https://github.com/llvm/llvm-project/blob/188507e54218c91832714fc50b24bd2fc2fd9383/clang/lib/CodeGen/TargetBuiltins/ARM.cpp?plain=1#L4574-L4576 

I will leave a FIXME in the newly added `getAArch64SVEProcessedOperands` for now.

https://github.com/llvm/llvm-project/pull/174433