[clang] [X86][CIR]Implement handling for F16 halfs to float conversion builtins (PR #173572)

[Andy Kaylor via cfe-commits]

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@@ -446,6 +446,61 @@ static mlir::Value emitX86Muldq(CIRGenBuilderTy &builder, mlir::Location loc,
   return builder.createMul(loc, lhs, rhs);
 }
 
+// Convert f16 half values to floats.
+static mlir::Value emitX86CvtF16ToFloatExpr(CIRGenBuilderTy &builder,
+                                            mlir::Location loc,
+                                            llvm::ArrayRef<mlir::Value> ops,
+                                            mlir::Type dstTy,
+                                            unsigned builtinID) {
+  assert((ops.size() == 1 || ops.size() == 3 || ops.size() == 4) &&
+         "Unknown cvtph2ps intrinsic");
+
+  // If the SAE intrinsic doesn't use default rounding then we can't upgrade.
+  if (ops.size() == 4) {
+    auto constOp = ops[3].getDefiningOp<cir::ConstantOp>();
+    assert(constOp && "Expected constant operand");
+    if (constOp.getIntValue().getZExtValue() != 4) {
+      StringRef intrinsicName;
+      switch (builtinID) {
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andykaylor wrote:

Only the `x86.avx512.mask.vcvtph2ps.512` form of this intrinsic takes a rounding mode parameter, so you don't need to switch on the builtin ID here. Note that in classic codegen `EmitX86CvtF16ToFloatExpr` always generates a call to `Intrinsic::x86_avx512_mask_vcvtph2ps_512` here. We should do the same.

https://github.com/llvm/llvm-project/pull/173572