[clang] [llvm] [AMDGPU] Introduce asyncmark/wait intrinsics (PR #173259)

[Krzysztof Drewniak via cfe-commits]

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@@ -368,12 +368,15 @@ enum CPol {
   GLC = 1,
   SLC = 2,
   DLC = 4,
+  SWZ_pregfx12 = 8,
   SCC = 16,
+  ASYNC_pregfx12 = 32,
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krzysz00 wrote:

I figure this should be an MMO flag at the isel level. At the IR level, smuggling this state into the high bits of CPol is a backwards-compatible way to have state that, unlike metadata, can't be dropped.

I'd be willing to clear the existing volatile out of CPol if we went and upgraded all the intrinsics to take an `immarg i1 %volatile` instead

https://github.com/llvm/llvm-project/pull/173259