[clang] [llvm] [RISCV] Add Spacemit X100 processor definition (PR #173988)

[Mark Zhuang via cfe-commits]

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@@ -159,6 +159,7 @@ Changes to the RISC-V Backend
 * DWARF fission is now compatible with linker relaxations, allowing `-gsplit-dwarf` and `-mrelax`
   to be used together when building for the RISC-V platform.
 * The Xqci Qualcomm uC Vendor Extension is no longger marked as experimental.
+* `-mcpu=spacemit-x100` is now supported.
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zqb-all wrote:

Thanks, addressed. 
BTW，the "xxx is support now" is copy from line 175，x86 backend.

https://github.com/llvm/llvm-project/pull/173988