[clang] [PATCH] [PATCH] [CIR][X86] Add support for cmp builtins (PR #174318)
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cfe-commits at lists.llvm.org
Sun Jan 4 00:50:32 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clangir
@llvm/pr-subscribers-clang
Author: Zhihui Yang (YGGkk)
<details>
<summary>Changes</summary>
Part of https://github.com/llvm/llvm-project/issues/167765
Add support for cmp builtins
Add a new castop kind vector_to_int to cast the vector type to int type
---
Patch is 52.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/174318.diff
6 Files Affected:
- (modified) clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h (+4)
- (modified) clang/include/clang/CIR/Dialect/IR/CIROps.td (+8)
- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+82-5)
- (modified) clang/lib/CIR/Dialect/IR/CIRDialect.cpp (+8)
- (modified) clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp (+32-1)
- (added) clang/test/CIR/CodeGenBuiltins/X86/cmp-builtins.c (+719)
``````````diff
diff --git a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
index 8edb796884b5c..fe3bc846ddbc9 100644
--- a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+++ b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
@@ -479,6 +479,10 @@ class CIRBaseBuilderTy : public mlir::OpBuilder {
return createAddrSpaceCast(src.getLoc(), src, newTy);
}
+ mlir::Value createVectorToIntCast(mlir::Location loc, mlir::Value src, mlir::Type newTy) {
+ return createCast(loc, cir::CastKind::vector_to_int, src, newTy);
+ }
+
//===--------------------------------------------------------------------===//
// Binary Operators
//===--------------------------------------------------------------------===//
diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td b/clang/include/clang/CIR/Dialect/IR/CIROps.td
index 74e0860762ec6..c2be3359e3af2 100644
--- a/clang/include/clang/CIR/Dialect/IR/CIROps.td
+++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td
@@ -177,6 +177,7 @@ def CIR_CastKind : CIR_I32EnumAttr<"CastKind", "cast kind", [
// Enums below are specific to CIR and don't have a correspondence to classic
// codegen:
+ I32EnumAttrCase<"vector_to_int", 999>,
I32EnumAttrCase<"bool_to_float", 1000>,
]>;
@@ -217,6 +218,13 @@ def CIR_CastOp : CIR_Op<"cast", [
CIR also supports some additional conversions that are not part of the classic
Clang codegen:
+ - `vector_to_int`
+
+ Example:
+ ```mlir
+ %4 = cir.cast vector_to_int %3 :!cir.vector<16 x !s8i> -> !u16i
+ ```
+
- `bool_to_float`
Example:
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 75bf25b20f1af..70a206fb4b0e7 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -417,6 +417,81 @@ static mlir::Value emitX86vpcom(CIRGenBuilderTy &builder, mlir::Location loc,
return builder.createVecCompare(loc, pred, op0, op1);
}
+static mlir::Value emitX86MaskedCompare(CIRGenBuilderTy &builder, mlir::Location loc,
+ llvm::SmallVector<mlir::Value> ops, bool isSigned = true)
+{
+
+ uint64_t imm = CIRGenFunction::getZExtIntValueFromConstOp(ops[2]) & 0x7;
+ cir::VectorType ty = cast<cir::VectorType>(ops[0].getType());
+ cir::IntType elementTy = cast<cir::IntType>(ty.getElementType());
+ unsigned numElts = ty.getSize();
+ mlir::Value cmp;
+ if (imm == 3)
+ {
+ cmp = builder.getNullValue(cir::VectorType::get(builder.getSIntNTy(1), numElts), loc);
+ }
+ else if (imm == 7)
+ {
+ llvm::APInt allOnes = llvm::APInt::getAllOnes(elementTy.getWidth());
+ cmp = cir::VecSplatOp::create(
+ builder, loc, ty, builder.getConstAPInt(loc, elementTy, allOnes));
+ }
+ else
+ {
+ cir::CmpOpKind pred;
+ switch(imm) {
+ default:
+ llvm_unreachable("Unknown condition code");
+ case 0:
+ pred = cir::CmpOpKind::eq;
+ break;
+ case 1:
+ pred = cir::CmpOpKind::lt;
+ break;
+ case 2:
+ pred = cir::CmpOpKind::le;
+ break;
+ case 4:
+ pred = cir::CmpOpKind::ne;
+ break;
+ case 5:
+ pred = cir::CmpOpKind::ge;
+ break;
+ case 6:
+ pred = cir::CmpOpKind::gt;
+ break;
+ }
+ cir::VectorType integralVecTy = cir::VectorType::get(builder.getUIntNTy(1), numElts);
+ cmp = cir::VecCmpOp::create(builder, loc, integralVecTy, pred, ops[0], ops[1]);
+ }
+ mlir::Value maskIn = nullptr;
+ if (ops.size() == 4)
+ maskIn = ops[3];
+
+ if (maskIn)
+ {
+ auto castOp = mlir::dyn_cast_or_null<cir::CastOp>(maskIn.getDefiningOp());
+ if (!castOp)
+ {
+ auto maskVec = getMaskVecValue(builder, loc, maskIn, numElts);
+ cmp = builder.createAnd(loc, cmp, maskVec);
+ }
+ }
+ if (numElts < 8)
+ {
+ mlir::Type i32Ty = builder.getSInt32Ty();
+ SmallVector<mlir::Attribute, 8> indices;
+ for (unsigned i = 0; i != numElts; ++i)
+ indices.push_back(cir::IntAttr::get(i32Ty, i));
+ for (unsigned i = numElts; i != 8; ++i)
+ indices.push_back(cir::IntAttr::get(i32Ty, i % numElts + numElts));
+ cmp = builder.createVecShuffle(loc, cmp, builder.getNullValue(cmp.getType(), loc), indices);
+ }
+ auto result = builder.createVectorToIntCast(
+ loc, cmp, builder.getUIntNTy(std::max(numElts, 8U)));
+ return result;
+ }
+
mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -1338,6 +1413,10 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
case X86::BI__builtin_ia32_selectsbf_128:
case X86::BI__builtin_ia32_selectss_128:
case X86::BI__builtin_ia32_selectsd_128:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return {};
case X86::BI__builtin_ia32_cmpb128_mask:
case X86::BI__builtin_ia32_cmpb256_mask:
case X86::BI__builtin_ia32_cmpb512_mask:
@@ -1361,11 +1440,9 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
case X86::BI__builtin_ia32_ucmpd512_mask:
case X86::BI__builtin_ia32_ucmpq128_mask:
case X86::BI__builtin_ia32_ucmpq256_mask:
- case X86::BI__builtin_ia32_ucmpq512_mask:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented X86 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return {};
+ case X86::BI__builtin_ia32_ucmpq512_mask: {
+ return emitX86MaskedCompare(builder, getLoc(expr->getExprLoc()), ops);
+ }
case X86::BI__builtin_ia32_vpcomb:
case X86::BI__builtin_ia32_vpcomw:
case X86::BI__builtin_ia32_vpcomd:
diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
index d888fdcf081e7..f6c54ee210d91 100644
--- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
@@ -656,6 +656,14 @@ LogicalResult cir::CastOp::verify() {
<< "requires floating point !cir.complex type for result";
return success();
}
+ case cir::CastKind::vector_to_int: {
+ auto vectorTy = mlir::dyn_cast<cir::VectorType>(srcType);
+ if (!vectorTy)
+ return emitOpError() << "requires !cir.vector type for source";
+ if (!mlir::isa<cir::IntType>(resType))
+ return emitOpError() << "requires !cir.int type for result";
+ return success();
+ }
default:
llvm_unreachable("Unknown CastOp kind?");
}
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index eeb886445ede4..6d550228af27d 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -1334,6 +1334,29 @@ mlir::LogicalResult CIRToLLVMCastOpLowering::matchAndRewrite(
assert(!MissingFeatures::cxxABI());
assert(!MissingFeatures::methodType());
break;
+ case cir::CastKind::vector_to_int: {
+ mlir::Type srcType = castOp.getSrc().getType();
+ mlir::Type dstType = castOp.getType();
+ mlir::Value llvmSrcVal = adaptor.getSrc();
+ cir::IntType srcIntType =
+ mlir::cast<cir::IntType>(elementTypeIfVector(srcType));
+ cir::IntType dstIntType =
+ mlir::cast<cir::IntType>(elementTypeIfVector(dstType));
+ uint64_t numElements =
+ mlir::cast<cir::VectorType>(srcType).getSize();
+
+ auto width = numElements * srcIntType.getWidth();
+ auto convertIntTypeOp = rewriter.create<mlir::LLVM::BitcastOp>(castOp.getLoc(), rewriter.getIntegerType(width),
+ llvmSrcVal);
+ // truncate to the destination integer type
+ auto dstWidth = dstIntType.getWidth();
+ auto srcWidth = mlir::cast<mlir::IntegerType>(convertIntTypeOp.getResult().getType()).getWidth();
+ auto truncOp = rewriter.create<mlir::LLVM::TruncOp>(
+ convertIntTypeOp.getLoc(), rewriter.getIntegerType(dstWidth),
+ convertIntTypeOp.getResult());
+ rewriter.replaceOp(castOp, truncOp);
+ break;
+ }
default: {
return castOp.emitError("Unhandled cast kind: ")
<< castOp.getKindAttrName();
@@ -2650,7 +2673,6 @@ mlir::LogicalResult CIRToLLVMCmpOpLowering::matchAndRewrite(
return mlir::success();
}
}
-
return cmpOp.emitError() << "unsupported type for CmpOp: " << type;
}
@@ -3590,6 +3612,15 @@ mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite(
// LLVM IR vector comparison returns a vector of i1. This one-bit vector
// must be sign-extended to the correct result type.
+ auto vecElementType = elementTypeIfVector(op.getType());
+ if (auto intType = mlir::dyn_cast<cir::IntType>(vecElementType))
+ {
+ if (intType.getWidth() == 1)
+ {
+ rewriter.replaceOp(op, bitResult);
+ return mlir::success();
+ }
+ }
rewriter.replaceOpWithNewOp<mlir::LLVM::SExtOp>(
op, typeConverter->convertType(op.getType()), bitResult);
return mlir::success();
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/cmp-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/cmp-builtins.c
new file mode 100644
index 0000000000000..f37be51c43216
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/cmp-builtins.c
@@ -0,0 +1,719 @@
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -target-feature +avx512bw -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+
+#include <immintrin.h>
+
+__mmask16 test_mm_cmp_epi8_mask(__m128i __a, __m128i __b) {
+ // CIR-LABEL: test_mm_cmp_epi8_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<16 x !s8i>, !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<16 x !cir.int<u, 1>> -> !u16i
+ // LLVM-LABEL: test_mm_cmp_epi8_mask
+ // LLVM: icmp eq <16 x i8> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm_cmp_epi8_mask
+ // OGCG: icmp eq <16 x i8> %{{.*}}, %{{.*}}
+ return (__mmask16)_mm_cmp_epi8_mask(__a, __b, 0);
+}
+
+__mmask16 test_mm_cmp_epi8_mask_imm3(__m128i __a, __m128i __b) {
+ // CIR-LABEL: test_mm_cmp_epi8_mask
+ // CIR: cir.const #cir.zero : !cir.vector<16 x !cir.int<s, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<16 x !cir.int<s, 1>> -> !u16i
+ // LLVM-LABEL: test_mm_cmp_epi8_mask
+ // LLVM: store i16 0, ptr %{{.*}}, align 2
+ // LLVM: load i16, ptr %{{.*}}, align 2
+ // LLVM: ret i16 %{{.*}}
+ // OGCG-LABEL: test_mm_cmp_epi8_mask
+ // OGCG: ret i16 0
+ return (__mmask16)_mm_cmp_epi8_mask(__a, __b, 3);
+}
+
+__mmask16 test_mm_cmp_epi8_mask_imm7(__m128i __a, __m128i __b) {
+ // CIR-LABEL: test_mm_cmp_epi8_mask
+ // CIR: cir.vec.splat {{%.*}} : !s8i, !cir.vector<16 x !s8i>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<16 x !s8i> -> !u16i
+ // LLVM-LABEL: test_mm_cmp_epi8_mask
+ // LLVM: store i16 -1, ptr %{{.*}}, align 2
+ // LLVM: load i16, ptr %{{.*}}, align 2
+ // LLVM: ret i16 %{{.*}}
+ // OGCG-LABEL: test_mm_cmp_epi8_mask
+ // OGCG: ret i16 -1
+ return (__mmask16)_mm_cmp_epi8_mask(__a, __b, 7);
+}
+
+__mmask16 test_mm_mask_cmp_epi8_mask(__mmask16 __m, __m128i __a, __m128i __b) {
+ // CIR-LABEL: test_mm_mask_cmp_epi8_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<16 x !s8i>, !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.cast bitcast {{%.*}} : !u16i -> !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.binop(and, {{%.*}}, {{%.*}}) : !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<16 x !cir.int<u, 1>> -> !u16i
+ // LLVM-LABEL: test_mm_mask_cmp_epi8_mask
+ // LLVM: icmp eq <16 x i8> %{{.*}}, %{{.*}}
+ // LLVM: and <16 x i1> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm_mask_cmp_epi8_mask
+ // OGCG: icmp eq <16 x i8> %{{.*}}, %{{.*}}
+ // OGCG: and <16 x i1> %{{.*}}, %{{.*}}
+ return (__mmask16)_mm_mask_cmp_epi8_mask(__m, __a, __b, 0);
+}
+
+__mmask32 test_mm256_cmp_epi8_mask(__m256i __a, __m256i __b) {
+ // CIR-LABEL: test_mm256_cmp_epi8_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<32 x !s8i>, !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<32 x !cir.int<u, 1>> -> !u32i
+ // LLVM-LABEL: test_mm256_cmp_epi8_mask
+ // LLVM: icmp eq <32 x i8> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm256_cmp_epi8_mask
+ // OGCG: icmp eq <32 x i8> %{{.*}}, %{{.*}}
+ return (__mmask32)_mm256_cmp_epi8_mask(__a, __b, 0);
+}
+
+__mmask32 test_mm256_mask_cmp_epi8_mask(__mmask32 __m, __m256i __a, __m256i __b) {
+ // CIR-LABEL: test_mm256_mask_cmp_epi8_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<32 x !s8i>, !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.cast bitcast {{%.*}} : !u32i -> !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.binop(and, {{%.*}}, {{%.*}}) : !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<32 x !cir.int<u, 1>> -> !u32i
+ // LLVM-LABEL: test_mm256_mask_cmp_epi8_mask
+ // LLVM: icmp eq <32 x i8> %{{.*}}, %{{.*}}
+ // LLVM: and <32 x i1> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm256_mask_cmp_epi8_mask
+ // OGCG: icmp eq <32 x i8> %{{.*}}, %{{.*}}
+ // OGCG: and <32 x i1> %{{.*}}, %{{.*}}
+ return (__mmask32)_mm256_mask_cmp_epi8_mask(__m, __a, __b, 0);
+}
+
+__mmask64 test_mm512_cmp_epi8_mask(__m512i __a, __m512i __b) {
+ // CIR-LABEL: test_mm512_cmp_epi8_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<64 x !s8i>, !cir.vector<64 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<64 x !cir.int<u, 1>> -> !u64i
+ // LLVM-LABEL: test_mm512_cmp_epi8_mask
+ // LLVM: icmp eq <64 x i8> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm512_cmp_epi8_mask
+ // OGCG: icmp eq <64 x i8> %{{.*}}, %{{.*}}
+ return (__mmask64)_mm512_cmp_epi8_mask(__a, __b, 0);
+}
+
+__mmask64 test_mm512_mask_cmp_epi8_mask(__mmask64 __m, __m512i __a, __m512i __b) {
+ // CIR-LABEL: test_mm512_mask_cmp_epi8_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<64 x !s8i>, !cir.vector<64 x !cir.int<u, 1>>
+ // CIR: cir.cast bitcast {{%.*}} : !u64i -> !cir.vector<64 x !cir.int<u, 1>>
+ // CIR: cir.binop(and, {{%.*}}, {{%.*}}) : !cir.vector<64 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<64 x !cir.int<u, 1>> -> !u64i
+ // LLVM-LABEL: test_mm512_mask_cmp_epi8_mask
+ // LLVM: icmp eq <64 x i8> %{{.*}}, %{{.*}}
+ // LLVM: and <64 x i1> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm512_mask_cmp_epi8_mask
+ // OGCG: icmp eq <64 x i8> %{{.*}}, %{{.*}}
+ // OGCG: and <64 x i1> %{{.*}}, %{{.*}}
+ return (__mmask64)_mm512_mask_cmp_epi8_mask(__m, __a, __b, 0);
+}
+
+__mmask8 test_mm_cmp_epi16_mask(__m128i __a, __m128i __b) {
+ // CIR-LABEL: test_mm_cmp_epi16_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<8 x !s16i>, !cir.vector<8 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<8 x !cir.int<u, 1>> -> !u8i
+ // LLVM-LABEL: test_mm_cmp_epi16_mask
+ // LLVM: icmp eq <8 x i16> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm_cmp_epi16_mask
+ // OGCG: icmp eq <8 x i16> %{{.*}}, %{{.*}}
+ return (__mmask8)_mm_cmp_epi16_mask(__a, __b, 0);
+}
+
+__mmask8 test_mm_mask_cmp_epi16_mask(__mmask8 __m, __m128i __a, __m128i __b) {
+ // CIR-LABEL: test_mm_mask_cmp_epi16_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<8 x !s16i>, !cir.vector<8 x !cir.int<u, 1>>
+ // CIR: cir.cast bitcast {{%.*}} : !u8i -> !cir.vector<8 x !cir.int<u, 1>>
+ // CIR: cir.binop(and, {{%.*}}, {{%.*}}) : !cir.vector<8 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<8 x !cir.int<u, 1>> -> !u8i
+ // LLVM-LABEL: test_mm_mask_cmp_epi16_mask
+ // LLVM: icmp eq <8 x i16> %{{.*}}, %{{.*}}
+ // LLVM: and <8 x i1> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm_mask_cmp_epi16_mask
+ // OGCG: icmp eq <8 x i16> %{{.*}}, %{{.*}}
+ // OGCG: and <8 x i1> %{{.*}}, %{{.*}}
+ return (__mmask8)_mm_mask_cmp_epi16_mask(__m, __a, __b, 0);
+}
+
+__mmask16 test_mm256_cmp_epi16_mask(__m256i __a, __m256i __b) {
+ // CIR-LABEL: test_mm256_cmp_epi16_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<16 x !s16i>, !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<16 x !cir.int<u, 1>> -> !u16i
+ // LLVM-LABEL: test_mm256_cmp_epi16_mask
+ // LLVM: icmp eq <16 x i16> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm256_cmp_epi16_mask
+ // OGCG: icmp eq <16 x i16> %{{.*}}, %{{.*}}
+ return (__mmask16)_mm256_cmp_epi16_mask(__a, __b, 0);
+}
+
+__mmask16 test_mm256_mask_cmp_epi16_mask(__mmask16 __m, __m256i __a, __m256i __b) {
+ // CIR-LABEL: test_mm256_mask_cmp_epi16_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<16 x !s16i>, !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.cast bitcast {{%.*}} : !u16i -> !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.binop(and, {{%.*}}, {{%.*}}) : !cir.vector<16 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<16 x !cir.int<u, 1>> -> !u16i
+ // LLVM-LABEL: test_mm256_mask_cmp_epi16_mask
+ // LLVM: icmp eq <16 x i16> %{{.*}}, %{{.*}}
+ // LLVM: and <16 x i1> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm256_mask_cmp_epi16_mask
+ // OGCG: icmp eq <16 x i16> %{{.*}}, %{{.*}}
+ // OGCG: and <16 x i1> %{{.*}}, %{{.*}}
+ return (__mmask16)_mm256_mask_cmp_epi16_mask(__m, __a, __b, 0);
+}
+
+__mmask32 test_mm512_cmp_epi16_mask(__m512i __a, __m512i __b) {
+ // CIR-LABEL: test_mm512_cmp_epi16_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<32 x !s16i>, !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<32 x !cir.int<u, 1>> -> !u32i
+ // LLVM-LABEL: test_mm512_cmp_epi16_mask
+ // LLVM: icmp eq <32 x i16> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm512_cmp_epi16_mask
+ // OGCG: icmp eq <32 x i16> %{{.*}}, %{{.*}}
+ return (__mmask32)_mm512_cmp_epi16_mask(__a, __b, 0);
+}
+
+__mmask32 test_mm512_mask_cmp_epi16_mask(__mmask32 __m, __m512i __a, __m512i __b) {
+ // CIR-LABEL: test_mm512_mask_cmp_epi16_mask
+ // CIR: cir.vec.cmp(eq, {{%.*}}, {{%.*}}) : !cir.vector<32 x !s16i>, !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.cast bitcast {{%.*}} : !u32i -> !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.binop(and, {{%.*}}, {{%.*}}) : !cir.vector<32 x !cir.int<u, 1>>
+ // CIR: cir.cast vector_to_int {{%.*}} : !cir.vector<32 x !cir.int<u, 1>> -> !u32i
+ // LLVM-LABEL: test_mm512_mask_cmp_epi16_mask
+ // LLVM: icmp eq <32 x i16> %{{.*}}, %{{.*}}
+ // LLVM: and <32 x i1> %{{.*}}, %{{.*}}
+ // OGCG-LABEL: test_mm512_mask_cmp_epi16_mask
+ // OGCG: icmp eq <32 x i16> %{{.*}}, %{{.*}}
+ // OGCG: and <32 x i1> %{{.*}}, %{{.*}}
+ return (__mmask32)_mm512_mask_cmp_epi16_mask(__m, __a...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/174318
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