[clang] [llvm] [clang][WebAssembly] Fix Wasm Vararg pointer width (PR #173580)
via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 1 00:55:16 PST 2026
https://github.com/daxpedda updated https://github.com/llvm/llvm-project/pull/173580
>From eb7c600cc69ad67259282f106e49ab28d11f47f1 Mon Sep 17 00:00:00 2001
From: daxpedda <daxpedda at gmail.com>
Date: Thu, 25 Dec 2025 22:44:33 +0100
Subject: [PATCH 1/2] [clang][WebAssembly] Fix Wasm Vararg pointer width
---
clang/lib/CodeGen/Targets/WebAssembly.cpp | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/Targets/WebAssembly.cpp b/clang/lib/CodeGen/Targets/WebAssembly.cpp
index ebe996a4edd8d..ce97884fa57c4 100644
--- a/clang/lib/CodeGen/Targets/WebAssembly.cpp
+++ b/clang/lib/CodeGen/Targets/WebAssembly.cpp
@@ -160,10 +160,11 @@ RValue WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
bool IsIndirect = isAggregateTypeForABI(Ty) &&
!isEmptyRecord(getContext(), Ty, true) &&
!isSingleElementStruct(Ty, getContext());
- return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
- getContext().getTypeInfoInChars(Ty),
- CharUnits::fromQuantity(4),
- /*AllowHigherAlign=*/true, Slot);
+ return emitVoidPtrVAArg(
+ CGF, VAListAddr, Ty, IsIndirect, getContext().getTypeInfoInChars(Ty),
+ CharUnits::fromQuantity(
+ getContext().getTargetInfo().getTriple().isArch64Bit() ? 8 : 4),
+ /*AllowHigherAlign=*/true, Slot);
}
std::unique_ptr<TargetCodeGenInfo>
>From a71f47cab409747d775a72fb4133ecdc4605014d Mon Sep 17 00:00:00 2001
From: daxpedda <daxpedda at gmail.com>
Date: Thu, 1 Jan 2026 09:54:56 +0100
Subject: [PATCH 2/2] Fix vararg slot size
---
.../test/CodeGen/WebAssembly/wasm64-varargs.c | 125 ++++++++++++++++++
.../WebAssembly/WebAssemblyISelLowering.cpp | 2 +-
2 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGen/WebAssembly/wasm64-varargs.c
diff --git a/clang/test/CodeGen/WebAssembly/wasm64-varargs.c b/clang/test/CodeGen/WebAssembly/wasm64-varargs.c
new file mode 100644
index 0000000000000..387c3dc256be5
--- /dev/null
+++ b/clang/test/CodeGen/WebAssembly/wasm64-varargs.c
@@ -0,0 +1,125 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
+// RUN: %clang_cc1 -triple wasm64-unknown-unknown -o - -emit-llvm %s | FileCheck %s
+
+#include <stdarg.h>
+
+// CHECK-LABEL: define {{[^@]+}}@test_i32
+// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[V:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 8
+// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
+// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 8
+// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i64 8
+// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 8
+// CHECK-NEXT: store i32 [[TMP0]], ptr [[V]], align 4
+// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[V]], align 4
+// CHECK-NEXT: ret i32 [[TMP1]]
+//
+int test_i32(char *fmt, ...) {
+ va_list va;
+
+ va_start(va, fmt);
+ int v = va_arg(va, int);
+ va_end(va);
+
+ return v;
+}
+
+
+// CHECK-LABEL: define {{[^@]+}}@test_i64
+// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[V:%.*]] = alloca i64, align 8
+// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 8
+// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
+// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i64 8
+// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARGP_CUR]], align 8
+// CHECK-NEXT: store i64 [[TMP1]], ptr [[V]], align 8
+// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[V]], align 8
+// CHECK-NEXT: ret i64 [[TMP2]]
+//
+long long test_i64(char *fmt, ...) {
+ va_list va;
+
+ va_start(va, fmt);
+ long long v = va_arg(va, long long);
+ va_end(va);
+
+ return v;
+}
+
+
+struct S {
+ int x;
+ int y;
+ int z;
+};
+
+// CHECK-LABEL: define {{[^@]+}}@test_struct
+// CHECK-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 8
+// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
+// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 8
+// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i64 8
+// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGP_CUR]], align 8
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_RESULT]], ptr align 4 [[TMP0]], i64 12, i1 false)
+// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
+// CHECK-NEXT: ret void
+//
+struct S test_struct(char *fmt, ...) {
+ va_list va;
+
+ va_start(va, fmt);
+ struct S v = va_arg(va, struct S);
+ va_end(va);
+
+ return v;
+}
+
+
+struct Z {};
+
+// CHECK-LABEL: define {{[^@]+}}@test_empty_struct
+// CHECK-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[U:%.*]] = alloca [[STRUCT_Z:%.*]], align 1
+// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 8
+// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
+// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 8
+// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i64 0
+// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 8
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[U]], ptr align 8 [[ARGP_CUR]], i64 0, i1 false)
+// CHECK-NEXT: [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 8
+// CHECK-NEXT: [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i64 8
+// CHECK-NEXT: store ptr [[ARGP_NEXT2]], ptr [[VA]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 8
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_RESULT]], ptr align 4 [[TMP0]], i64 12, i1 false)
+// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
+// CHECK-NEXT: ret void
+//
+struct S test_empty_struct(char *fmt, ...) {
+ va_list va;
+
+ va_start(va, fmt);
+ struct Z u = va_arg(va, struct Z);
+ struct S v = va_arg(va, struct S);
+ va_end(va);
+
+ return v;
+}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index d8ae9cd6c39fa..525b490624aca 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1412,7 +1412,7 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
assert(VT != MVT::iPTR && "Legalized args should be concrete");
Type *Ty = VT.getTypeForEVT(*DAG.getContext());
Align Alignment =
- std::max(Out.Flags.getNonZeroOrigAlign(), Layout.getABITypeAlign(Ty));
+ std::max(Align(Subtarget->getTargetTriple().isArch64Bit() ? 8 : 4), Layout.getABITypeAlign(Ty));
unsigned Offset =
CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty), Alignment);
CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
More information about the cfe-commits
mailing list