[clang] [llvm] [X86][APX] Emit SetZUCC instead of legacy setcc when ZU is enabled (PR #173965)
via cfe-commits
cfe-commits at lists.llvm.org
Tue Dec 30 00:14:19 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Feng Zou (fzou1)
<details>
<summary>Changes</summary>
To avoid false dependency.
---
Patch is 215.17 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/173965.diff
18 Files Affected:
- (modified) clang/lib/Driver/ToolChains/Arch/X86.cpp (+8)
- (modified) clang/test/Driver/cl-x86-flags.c (+4-3)
- (modified) clang/test/Driver/x86-target-features.c (+5-3)
- (modified) llvm/lib/Target/X86/X86.td (+3)
- (modified) llvm/lib/Target/X86/X86FastISel.cpp (+19-12)
- (modified) llvm/lib/Target/X86/X86FixupSetCC.cpp (+7-3)
- (modified) llvm/lib/Target/X86/X86FlagsCopyLowering.cpp (+4-24)
- (modified) llvm/lib/Target/X86/X86InstrCMovSetCC.td (+9-3)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (+2)
- (modified) llvm/test/CodeGen/X86/apx/ccmp.ll (+516)
- (modified) llvm/test/CodeGen/X86/apx/ctest.ll (+443)
- (modified) llvm/test/CodeGen/X86/apx/setzucc.ll (+47-23)
- (modified) llvm/test/CodeGen/X86/fast-isel-fcmp.ll (+764)
- (modified) llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll (+370)
- (modified) llvm/test/CodeGen/X86/pr27591.ll (+49)
- (modified) llvm/test/CodeGen/X86/pr32284.ll (+369)
- (modified) llvm/test/CodeGen/X86/pr54369.ll (+46)
- (modified) llvm/test/CodeGen/X86/scmp.ll (+1214)
``````````diff
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index d6e6657c521f0..b144f4b040b4b 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -269,6 +269,14 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple,
Features.push_back(
Args.MakeArgString((IsNegative ? "-" : "+") + Value));
+
+ // Implicitly add prefer-setzucc feature when ZU feature is enabled. The
+ // prefer-setzucc feature enables exclusively emitting SetZUCC
+ // instruction and never emitting the legacy SETCC instruction.
+ // The latter is susceptible to false dependences.
+ if (Value == "zu")
+ Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") +
+ Twine("prefer-setzucc")));
}
continue;
}
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 84270aae35f7a..6ce9133d6f9f5 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -222,6 +222,7 @@ void f(void) {
// RUN: %clang_cl --target=x86_64-pc-windows -mapxf -### -- 2>&1 %s | FileCheck -check-prefix=APXF %s
// RUN: %clang_cl --target=x86_64-pc-windows -mapxf -mno-apxf -### -- 2>&1 %s | FileCheck -check-prefix=NO-APXF %s
// RUN: %clang_cl --target=x86_64-pc-windows -mapx-features=egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu -### -- 2>&1 %s | FileCheck -check-prefix=APXALL %s
-// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" "-target-feature" "+ccmp" "-target-feature" "+nf" "-target-feature" "+zu"
-// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" "-target-feature" "-ndd" "-target-feature" "-ccmp" "-target-feature" "-nf" "-target-feature" "-zu"
-// APXALL: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" "-target-feature" "+ccmp" "-target-feature" "+nf" "-target-feature" "+cf" "-target-feature" "+zu"
+// The prefer-setzucc feature is added/disabled implicitly when ZU feature is enabled/disabled by -mapxf/-mno-apxf option.
+// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" "-target-feature" "+ccmp" "-target-feature" "+nf" "-target-feature" "+zu" "-target-feature" "+prefer-setzucc"
+// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" "-target-feature" "-ndd" "-target-feature" "-ccmp" "-target-feature" "-nf" "-target-feature" "-zu" "-target-feature" "-prefer-setzucc"
+// APXALL: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" "-target-feature" "+ccmp" "-target-feature" "+nf" "-target-feature" "+cf" "-target-feature" "+zu" "-target-feature" "+prefer-setzucc"
diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c
index f1660b1afb518..cfc848ce72b1e 100644
--- a/clang/test/Driver/x86-target-features.c
+++ b/clang/test/Driver/x86-target-features.c
@@ -443,8 +443,9 @@
// RUN: %clang --target=x86_64-unknown-linux-gnu -mno-apxf -mapxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=APXF %s
// RUN: %clang --target=x86_64-unknown-linux-gnu -mapxf -mno-apxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-APXF %s
//
-// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" "-target-feature" "+ccmp" "-target-feature" "+nf" "-target-feature" "+zu"
-// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" "-target-feature" "-ndd" "-target-feature" "-ccmp" "-target-feature" "-nf" "-target-feature" "-zu"
+// The prefer-setzucc feature is added/disabled implicitly when ZU feature is enabled/disabled by -mapxf/-mno-apxf option.
+// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" "-target-feature" "+ccmp" "-target-feature" "+nf" "-target-feature" "+zu" "-target-feature" "+prefer-setzucc"
+// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" "-target-feature" "-ndd" "-target-feature" "-ccmp" "-target-feature" "-nf" "-target-feature" "-zu" "-target-feature" "-prefer-setzucc"
// RUN: %clang --target=x86_64-unknown-linux-gnu -mapx-features=egpr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR %s
// RUN: %clang --target=x86_64-unknown-linux-gnu -mapx-features=push2pop2 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=PUSH2POP2 %s
@@ -461,7 +462,8 @@
// CCMP: "-target-feature" "+ccmp"
// NF: "-target-feature" "+nf"
// CF: "-target-feature" "+cf"
-// ZU: "-target-feature" "+zu"
+// The prefer-setzucc feature is added implicitly when ZU feature is enabled.
+// ZU: "-target-feature" "+zu" "-target-feature" "+prefer-setzucc"
// RUN: %clang --target=x86_64-unknown-linux-gnu -mapx-features=egpr,ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s
// RUN: %clang --target=x86_64-unknown-linux-gnu -mapx-features=egpr -mapx-features=ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 3e357c9000bea..d41a91f4d94d4 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -364,6 +364,9 @@ def FeatureCF : SubtargetFeature<"cf", "HasCF", "true",
"Support conditional faulting">;
def FeatureZU : SubtargetFeature<"zu", "HasZU", "true",
"Support zero-upper SETcc/IMUL">;
+def FeaturePreferSetZUCC
+ : SubtargetFeature<"prefer-setzucc", "PreferSetZUCC", "true",
+ "Prefer to emit SetZUCC instead of legacy SetCC.">;
def FeatureUseGPR32InInlineAsm
: SubtargetFeature<"inline-asm-use-gpr32", "UseInlineAsmGPR32", "true",
"Enable use of GPR32 in inline assembly for APX">;
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index f007886115d35..d2ed027bd215e 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1434,6 +1434,8 @@ bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT,
return true;
}
+#define GET_SETCC (Subtarget->preferSetZUCC() ? X86::SETZUCCr : X86::SETCCr)
+
bool X86FastISel::X86SelectCmp(const Instruction *I) {
const CmpInst *CI = cast<CmpInst>(I);
@@ -1503,10 +1505,12 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
Register FlagReg1 = createResultReg(&X86::GR8RegClass);
Register FlagReg2 = createResultReg(&X86::GR8RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg1).addImm(SETFOpc[0]);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg2).addImm(SETFOpc[1]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ FlagReg1)
+ .addImm(SETFOpc[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ FlagReg2)
+ .addImm(SETFOpc[1]);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(SETFOpc[2]),
ResultReg).addReg(FlagReg1).addReg(FlagReg2);
updateValueMap(I, ResultReg);
@@ -1525,8 +1529,8 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc()))
return false;
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- ResultReg).addImm(CC);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC), ResultReg)
+ .addImm(CC);
updateValueMap(I, ResultReg);
return true;
}
@@ -2083,10 +2087,12 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
if (SETFOpc) {
Register FlagReg1 = createResultReg(&X86::GR8RegClass);
Register FlagReg2 = createResultReg(&X86::GR8RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg1).addImm(SETFOpc[0]);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg2).addImm(SETFOpc[1]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ FlagReg1)
+ .addImm(SETFOpc[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ FlagReg2)
+ .addImm(SETFOpc[1]);
auto const &II = TII.get(SETFOpc[2]);
if (II.getNumDefs()) {
Register TmpReg = createResultReg(&X86::GR8RegClass);
@@ -2989,8 +2995,9 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
// Assign to a GPR since the overflow return value is lowered to a SETcc.
Register ResultReg2 = createResultReg(&X86::GR8RegClass);
assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- ResultReg2).addImm(CondCode);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ ResultReg2)
+ .addImm(CondCode);
updateValueMap(II, ResultReg, 2);
return true;
diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp
index ea93a575ec530..157d82bfd3ced 100644
--- a/llvm/lib/Target/X86/X86FixupSetCC.cpp
+++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp
@@ -79,10 +79,10 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
if (MI.definesRegister(X86::EFLAGS, /*TRI=*/nullptr))
FlagsDefMI = &MI;
- // Find a setcc that is used by a zext.
+ // Find a setcc/setzucc (if ZU is enabled) that is used by a zext.
// This doesn't have to be the only use, the transformation is safe
// regardless.
- if (MI.getOpcode() != X86::SETCCr)
+ if (MI.getOpcode() != X86::SETCCr && MI.getOpcode() != X86::SETZUCCr)
continue;
MachineInstr *ZExt = nullptr;
@@ -122,7 +122,11 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
// register.
Register ZeroReg = MRI->createVirtualRegister(RC);
if (ST->hasZU()) {
- MI.setDesc(TII->get(X86::SETZUCCr));
+ if (ST->preferSetZUCC())
+ assert((MI.getOpcode() == X86::SETZUCCr) &&
+ "Expect setzucc instruction!");
+ else
+ MI.setDesc(TII->get(X86::SETZUCCr));
BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
TII->get(TargetOpcode::IMPLICIT_DEF), ZeroReg);
} else {
diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
index b3bf37a9a462c..17228eb231f61 100644
--- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
+++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
@@ -745,7 +745,10 @@ Register X86FlagsCopyLoweringPass::promoteCondToReg(
MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
const DebugLoc &TestLoc, X86::CondCode Cond) {
Register Reg = MRI->createVirtualRegister(PromoteRC);
- auto SetI = BuildMI(TestMBB, TestPos, TestLoc, TII->get(X86::SETCCr), Reg)
+ auto SetI = BuildMI(TestMBB, TestPos, TestLoc,
+ TII->get(Subtarget->preferSetZUCC() ? X86::SETZUCCr
+ : X86::SETCCr),
+ Reg)
.addImm(Cond);
(void)SetI;
LLVM_DEBUG(dbgs() << " save cond: "; SetI->dump());
@@ -790,29 +793,6 @@ void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &MBB,
if (!CondReg)
CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
- if (X86::isSETZUCC(MI.getOpcode())) {
- // SETZUCC is generated for register only for now.
- assert(!MI.mayStore() && "Cannot handle memory variants");
- assert(MI.getOperand(0).isReg() &&
- "Cannot have a non-register defined operand to SETZUcc!");
- Register OldReg = MI.getOperand(0).getReg();
- // Drop Kill flags on the old register before replacing. CondReg may have
- // a longer live range.
- MRI->clearKillFlags(OldReg);
- for (auto &Use : MRI->use_instructions(OldReg)) {
- assert(Use.getOpcode() == X86::INSERT_SUBREG &&
- "SETZUCC should be only used by INSERT_SUBREG");
- Use.getOperand(2).setReg(CondReg);
- // Recover MOV32r0 before INSERT_SUBREG, which removed by SETZUCC.
- Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
- BuildMI(*Use.getParent(), &Use, Use.getDebugLoc(), TII->get(X86::MOV32r0),
- ZeroReg);
- Use.getOperand(1).setReg(ZeroReg);
- }
- MI.eraseFromParent();
- return;
- }
-
// Rewriting a register def is trivial: we just replace the register and
// remove the setcc.
if (!MI.mayStore()) {
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 0b9172c1f2b6e..52cd7c4fe3a76 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -137,11 +137,13 @@ let Predicates = [HasCMOV, HasCF] in {
}
// SetCC instructions.
-let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, Predicates = [PreferNoSetZUCC] in {
def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"set${cond}\t$dst",
[(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
TB, Sched<[WriteSETCC]>;
+}
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
"set${cond}\t$dst",
[(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
@@ -150,10 +152,14 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
// SetZUCC and promoted SetCC instructions.
let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
- hasSideEffects = 0, Predicates = [In64BitMode] in {
+ hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [PreferSetZUCC] in {
def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
- "setzu${cond}\t$dst", []>,
+ "setzu${cond}\t$dst",
+ [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
XD, ZU, NoCD8, Sched<[WriteSETCC]>;
+}
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
+ hasSideEffects = 0, Predicates = [In64BitMode] in {
def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"set${cond}\t$dst", []>,
XD, PL, Sched<[WriteSETCC]>;
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index 98104a6fad1a9..56a0811e1ce10 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -46,6 +46,8 @@ def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
def HasNDD : Predicate<"Subtarget->hasNDD()">;
def NoNDD : Predicate<"!Subtarget->hasNDD()">;
def HasZU : Predicate<"Subtarget->hasZU()">;
+def PreferSetZUCC : Predicate<"Subtarget->preferSetZUCC()">;
+def PreferNoSetZUCC : Predicate<"!Subtarget->preferSetZUCC()">;
def HasCF : Predicate<"Subtarget->hasCF()">;
def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index 4c58c8a980314..eb7090597b099 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp -show-mc-encoding -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+ndd -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=NDD
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+zu,+prefer-setzucc -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=SETZUCC
define void @ccmp8rr_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) {
; CHECK-LABEL: ccmp8rr_zf:
@@ -30,6 +31,23 @@ define void @ccmp8rr_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1
; NDD-NEXT: .LBB0_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; SETZUCC-LABEL: ccmp8rr_zf:
+; SETZUCC: # %bb.0: # %entry
+; SETZUCC-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7]
+; SETZUCC-NEXT: je .LBB0_3 # encoding: [0x74,A]
+; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB0_3, kind: FK_PCRel_1
+; SETZUCC-NEXT: # %bb.1: # %entry
+; SETZUCC-NEXT: cmpb %dl, %sil # encoding: [0x40,0x38,0xd6]
+; SETZUCC-NEXT: je .LBB0_3 # encoding: [0x74,A]
+; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB0_3, kind: FK_PCRel_1
+; SETZUCC-NEXT: # %bb.2: # %if.end
+; SETZUCC-NEXT: retq # encoding: [0xc3]
+; SETZUCC-NEXT: .LBB0_3: # %if.then
+; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; SETZUCC-NEXT: jmp foo # TAILCALL
+; SETZUCC-NEXT: # encoding: [0xeb,A]
+; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1
entry:
%cmp = icmp eq i8 %a, %c
%cmp1 = icmp eq i8 %b, %c
@@ -72,6 +90,23 @@ define void @ccmp8rr_cf(i8 noundef %a, i8 noundef %b) {
; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1
; NDD-NEXT: .LBB1_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; SETZUCC-LABEL: ccmp8rr_cf:
+; SETZUCC: # %bb.0: # %entry
+; SETZUCC-NEXT: cmpb $2, %dil # encoding: [0x40,0x80,0xff,0x02]
+; SETZUCC-NEXT: setzul %al # encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
+; SETZUCC-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02]
+; SETZUCC-NEXT: setzub %cl # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc1]
+; SETZUCC-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; SETZUCC-NEXT: jne .LBB1_1 # encoding: [0x75,A]
+; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB1_1, kind: FK_PCRel_1
+; SETZUCC-NEXT: # %bb.2: # %if.then
+; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; SETZUCC-NEXT: jmp foo # TAILCALL
+; SETZUCC-NEXT: # encoding: [0xeb,A]
+; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1
+; SETZUCC-NEXT: .LBB1_1: # %if.end
+; SETZUCC-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i8 %a, 1
%tobool = icmp ugt i8 %b, 1
@@ -110,6 +145,22 @@ define i8 @ccmp8rr_sf(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; SETZUCC-LABEL: ccmp8rr_sf:
+; SETZUCC: # %bb.0: # %entry
+; SETZUCC-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; SETZUCC-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; SETZUCC-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02]
+; SETZUCC-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; SETZUCC-NEXT: andb %al, %cl # encoding: [0x20,0xc1]
+; SETZUCC-NEXT: cmpb $1, %cl # encoding: [0x80,0xf9,0x01]
+; SETZUCC-NEXT: jne .LBB2_2 # encoding: [0x75,A]
+; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB2_2, kind: FK_PCRel_1
+; SETZUCC-NEXT: # %bb.1: # %if.then
+; SETZUCC-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
+; SETZUCC-NEXT: .LBB2_2: # %if.end
+; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; SETZUCC-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = icmp sgt i8 %b, 1
@@ -148,6 +199,22 @@ define i8 @ccmp8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; SETZUCC-LABEL: ccmp8rr_none:
+; SETZUCC: # %bb.0: # %entry
+; SETZUCC-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; SETZUCC-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; SETZUCC-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02]
+; SETZUCC-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; SETZUCC-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; SETZUCC-NEXT: cmpb $1, %cl # encoding: [0x80,0xf9,0x01]
+;...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/173965
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