[clang] [CIR][X86] Add support for `cpuid`/`cpuidex` (PR #173197)

[Roberto Turrado Camblor via cfe-commits]

================
@@ -4248,6 +4193,76 @@ mlir::LogicalResult CIRToLLVMAwaitOpLowering::matchAndRewrite(
   return mlir::failure();
 }
 
+mlir::LogicalResult CIRToLLVMCpuIdOpLowering::matchAndRewrite(
+    cir::CpuIdOp op, OpAdaptor adaptor,
+    mlir::ConversionPatternRewriter &rewriter) const {
+  mlir::Type i32Ty = rewriter.getI32Type();
+  mlir::Type i64Ty = rewriter.getI64Type();
+  mlir::Type i32PtrTy = mlir::LLVM::LLVMPointerType::get(i32Ty.getContext(), 0);
+
+  mlir::Type cpuidRetTy = mlir::LLVM::LLVMStructType::getLiteral(
+      rewriter.getContext(), {i32Ty, i32Ty, i32Ty, i32Ty});
+
+  mlir::Value funcId = adaptor.getFuncId();
+  mlir::Value subFuncId = adaptor.getSubFuncId();
+  mlir::StringAttr opNameAttr = op->getAttrOfType<mlir::StringAttr>("name");
+  if (!opNameAttr)
+    return mlir::failure();
+  if (opNameAttr.getValue() == "cpuid")
+    subFuncId = mlir::LLVM::ConstantOp::create(rewriter, op.getLoc(), i32Ty, 0);
+  std::vector operands{funcId, subFuncId};
+
+  StringRef asmString, constraints;
+  mlir::ModuleOp moduleOp = op->getParentOfType<mlir::ModuleOp>();
+  mlir::StringAttr tripleAttr =
+      moduleOp->getAttrOfType<mlir::StringAttr>("llvm.target_triple");
+  if (!tripleAttr)
+    return mlir::failure();
+  llvm::Triple triple(tripleAttr.getValue().str());
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rturrado wrote:

Perfect, thanks!

https://github.com/llvm/llvm-project/pull/173197