[clang] [CIR][X86] Add CIR codegen support for fpclass x86 builtins (PR #172813)
Jianjian Guan via cfe-commits
cfe-commits at lists.llvm.org
Thu Dec 18 02:12:13 PST 2025
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/172813
>From e2e96814eded4c1a4041ee56a0bd6567a1395a0b Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Thu, 18 Dec 2025 15:52:04 +0800
Subject: [PATCH] [CIR][X86] Add CIR codegen support for fpclass x86 builtins
---
clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 94 ++++
.../X86/avx10_2_512bf16-builtins.c | 39 ++
.../X86/avx10_2bf16-builtins.c | 78 ++++
.../CodeGenBuiltins/X86/avx512dq-builtins.c | 78 ++++
.../CodeGenBuiltins/X86/avx512fp16-builtins.c | 40 ++
.../CodeGenBuiltins/X86/avx512vl-builtins.c | 1 -
.../CodeGenBuiltins/X86/avx512vldq-builtins.c | 420 ++++++++++++++++++
7 files changed, 749 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 32ae1957d3c6a..824d512e3b630 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -417,6 +417,95 @@ static mlir::Value emitX86vpcom(CIRGenBuilderTy &builder, mlir::Location loc,
return builder.createVecCompare(loc, pred, op0, op1);
}
+// Emits masked result similar to EmitX86MaskedCompareResult in
+// clang/lib/CodeGen/TargetBuiltins/X86.cpp
+static mlir::Value emitX86MaskedResult(CIRGenBuilderTy &builder,
+ mlir::Location loc, mlir::Value cmp,
+ unsigned numElts, mlir::Value maskIn) {
+ if (maskIn) {
+ auto constOp =
+ mlir::dyn_cast_or_null<cir::ConstantOp>(maskIn.getDefiningOp());
+ if (!constOp || !constOp.isAllOnesValue()) {
+ mlir::Value maskVec = getBoolMaskVecValue(builder, loc, maskIn, numElts);
+ cmp = builder.createAnd(loc, cmp, maskVec);
+ }
+ }
+
+ // If we have less than 8 elements, we need to pad the result.
+ if (numElts < 8) {
+ SmallVector<mlir::Attribute> indices;
+ mlir::Type i32Ty = builder.getSInt32Ty();
+ for (auto i : llvm::seq<unsigned>(0, numElts))
+ indices.push_back(cir::IntAttr::get(i32Ty, i));
+ for (auto i : llvm::seq<unsigned>(numElts, 8))
+ indices.push_back(cir::IntAttr::get(i32Ty, i % numElts + numElts));
+
+ mlir::Value zero = builder.getNullValue(cmp.getType(), loc);
+ cmp = builder.createVecShuffle(loc, cmp, zero, indices);
+ }
+
+ // Bitcast the result to integer type
+ unsigned resultWidth = std::max(numElts, 8U);
+ cir::IntType resultTy = builder.getUIntNTy(resultWidth);
+ return builder.createBitcast(cmp, resultTy);
+}
+
+static mlir::Value emitX86Fpclass(CIRGenBuilderTy &builder, mlir::Location loc,
+ unsigned builtinID,
+ SmallVectorImpl<mlir::Value> &ops) {
+ unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize();
+ mlir::Value maskIn = ops[2];
+ ops.erase(ops.begin() + 2);
+
+ StringRef intrinsicName;
+ switch (builtinID) {
+ default:
+ llvm_unreachable("Unsupported fpclass builtin");
+ case X86::BI__builtin_ia32_vfpclassbf16128_mask:
+ intrinsicName = "x86.avx10.fpclass.bf16.128";
+ break;
+ case X86::BI__builtin_ia32_vfpclassbf16256_mask:
+ intrinsicName = "x86.avx10.fpclass.bf16.256";
+ break;
+ case X86::BI__builtin_ia32_vfpclassbf16512_mask:
+ intrinsicName = "x86.avx10.fpclass.bf16.512";
+ break;
+ case X86::BI__builtin_ia32_fpclassph128_mask:
+ intrinsicName = "x86.avx512fp16.fpclass.ph.128";
+ break;
+ case X86::BI__builtin_ia32_fpclassph256_mask:
+ intrinsicName = "x86.avx512fp16.fpclass.ph.256";
+ break;
+ case X86::BI__builtin_ia32_fpclassph512_mask:
+ intrinsicName = "x86.avx512fp16.fpclass.ph.512";
+ break;
+ case X86::BI__builtin_ia32_fpclassps128_mask:
+ intrinsicName = "x86.avx512.fpclass.ps.128";
+ break;
+ case X86::BI__builtin_ia32_fpclassps256_mask:
+ intrinsicName = "x86.avx512.fpclass.ps.256";
+ break;
+ case X86::BI__builtin_ia32_fpclassps512_mask:
+ intrinsicName = "x86.avx512.fpclass.ps.512";
+ break;
+ case X86::BI__builtin_ia32_fpclasspd128_mask:
+ intrinsicName = "x86.avx512.fpclass.pd.128";
+ break;
+ case X86::BI__builtin_ia32_fpclasspd256_mask:
+ intrinsicName = "x86.avx512.fpclass.pd.256";
+ break;
+ case X86::BI__builtin_ia32_fpclasspd512_mask:
+ intrinsicName = "x86.avx512.fpclass.pd.512";
+ break;
+ }
+
+ cir::BoolType boolTy = builder.getBoolTy();
+ auto cmpResultTy = cir::VectorType::get(boolTy, numElts);
+ mlir::Value fpclass =
+ emitIntrinsicCallOp(builder, loc, intrinsicName, cmpResultTy, ops);
+ return emitX86MaskedResult(builder, loc, fpclass, numElts, maskIn);
+}
+
std::optional<mlir::Value>
CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -1628,6 +1717,10 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
case X86::BI__builtin_ia32_addcarryx_u64:
case X86::BI__builtin_ia32_subborrow_u32:
case X86::BI__builtin_ia32_subborrow_u64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case X86::BI__builtin_ia32_fpclassps128_mask:
case X86::BI__builtin_ia32_fpclassps256_mask:
case X86::BI__builtin_ia32_fpclassps512_mask:
@@ -1640,6 +1733,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
case X86::BI__builtin_ia32_fpclasspd128_mask:
case X86::BI__builtin_ia32_fpclasspd256_mask:
case X86::BI__builtin_ia32_fpclasspd512_mask:
+ return emitX86Fpclass(builder, getLoc(expr->getExprLoc()), builtinID, ops);
case X86::BI__builtin_ia32_vp2intersect_q_512:
case X86::BI__builtin_ia32_vp2intersect_q_256:
case X86::BI__builtin_ia32_vp2intersect_q_128:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
index e4501889c2d60..6c825af295643 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
@@ -26,3 +26,42 @@ __m512bh test_mm512_undefined_pbh(void) {
// OGCG: ret <32 x bfloat> zeroinitializer
return _mm512_undefined_pbh();
}
+
+__mmask32 test_mm512_mask_fpclass_pbh_mask(__mmask32 __U, __m512bh __A) {
+ // CIR-LABEL: _mm512_mask_fpclass_pbh_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx10.fpclass.bf16.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u32i -> !cir.vector<32 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<32 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<32 x !cir.bool> -> !u32i
+
+ // LLVM-LABEL: test_mm512_mask_fpclass_pbh_mask
+ // LLVM: %[[A:.*]] = call <32 x i1> @llvm.x86.avx10.fpclass.bf16.512
+ // LLVM: %[[B:.*]] = bitcast i32 {{.*}} to <32 x i1>
+ // LLVM: %[[C:.*]] = and <32 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <32 x i1> %[[C]] to i32
+
+ // OGCG-LABEL: test_mm512_mask_fpclass_pbh_mask
+ // OGCG: %[[A:.*]] = call <32 x i1> @llvm.x86.avx10.fpclass.bf16.512
+ // OGCG: %[[B:.*]] = bitcast i32 {{.*}} to <32 x i1>
+ // OGCG: %[[C:.*]] = and <32 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <32 x i1> %[[C]] to i32
+ return _mm512_mask_fpclass_pbh_mask(__U, __A, 4);
+}
+
+__mmask32 test_mm512_fpclass_pbh_mask(__m512bh __A) {
+ // CIR-LABEL: _mm512_fpclass_pbh_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx10.fpclass.bf16.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u32i -> !cir.vector<32 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<32 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<32 x !cir.bool> -> !u32i
+
+ // LLVM-LABEL: test_mm512_fpclass_pbh_mask
+ // LLVM: %[[A:.*]] = call <32 x i1> @llvm.x86.avx10.fpclass.bf16.512
+ // LLVM: %[[B:.*]] = and <32 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <32 x i1> %[[B]] to i32
+
+ // OGCG-LABEL: test_mm512_fpclass_pbh_mask
+ // OGCG: %[[A:.*]] = call <32 x i1> @llvm.x86.avx10.fpclass.bf16.512
+ // OGCG: bitcast <32 x i1> %[[A]] to i32
+ return _mm512_fpclass_pbh_mask(__A, 4);
+}
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
index 4dac4fa2fe811..00469a092a1ef 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
@@ -44,4 +44,82 @@ __m256bh test_mm256_undefined_pbh(void) {
// OGCG-LABEL: test_mm256_undefined_pbh
// OGCG: ret <16 x bfloat> zeroinitializer
return _mm256_undefined_pbh();
+}
+
+__mmask16 test_mm256_mask_fpclass_pbh_mask(__mmask16 __U, __m256bh __A) {
+ // CIR-LABEL: _mm256_mask_fpclass_pbh_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx10.fpclass.bf16.256"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u16i -> !cir.vector<16 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<16 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<16 x !cir.bool> -> !u16i
+
+ // LLVM-LABEL: test_mm256_mask_fpclass_pbh_mask
+ // LLVM: %[[A:.*]] = call <16 x i1> @llvm.x86.avx10.fpclass.bf16.256
+ // LLVM: %[[B:.*]] = bitcast i16 {{.*}} to <16 x i1>
+ // LLVM: %[[C:.*]] = and <16 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <16 x i1> %[[C]] to i16
+
+ // OGCG-LABEL: test_mm256_mask_fpclass_pbh_mask
+ // OGCG: %[[A:.*]] = call <16 x i1> @llvm.x86.avx10.fpclass.bf16.256
+ // OGCG: %[[B:.*]] = bitcast i16 {{.*}} to <16 x i1>
+ // OGCG: %[[C:.*]] = and <16 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <16 x i1> %[[C]] to i16
+ return _mm256_mask_fpclass_pbh_mask(__U, __A, 4);
+}
+
+__mmask16 test_mm256_fpclass_pbh_mask(__m256bh __A) {
+ // CIR-LABEL: _mm256_fpclass_pbh_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx10.fpclass.bf16.256"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u16i -> !cir.vector<16 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<16 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<16 x !cir.bool> -> !u16i
+
+ // LLVM-LABEL: test_mm256_fpclass_pbh_mask
+ // LLVM: %[[A:.*]] = call <16 x i1> @llvm.x86.avx10.fpclass.bf16.256
+ // LLVM: %[[B:.*]] = and <16 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <16 x i1> %[[B]] to i16
+
+ // OGCG-LABEL: test_mm256_fpclass_pbh_mask
+ // OGCG: %[[A:.*]] = call <16 x i1> @llvm.x86.avx10.fpclass.bf16.256
+ // OGCG: bitcast <16 x i1> %[[A]] to i16
+ return _mm256_fpclass_pbh_mask(__A, 4);
+}
+
+__mmask8 test_mm_mask_fpclass_pbh_mask(__mmask8 __U, __m128bh __A) {
+ // CIR-LABEL: _mm_mask_fpclass_pbh_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx10.fpclass.bf16.128"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm_mask_fpclass_pbh_mask
+ // LLVM: %[[A:.*]] = call <8 x i1> @llvm.x86.avx10.fpclass.bf16.128
+ // LLVM: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // LLVM: %[[C:.*]] = and <8 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <8 x i1> %[[C]] to i8
+
+ // OGCG-LABEL: test_mm_mask_fpclass_pbh_mask
+ // OGCG: %[[A:.*]] = call <8 x i1> @llvm.x86.avx10.fpclass.bf16.128
+ // OGCG: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // OGCG: %[[C:.*]] = and <8 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <8 x i1> %[[C]] to i8
+ return _mm_mask_fpclass_pbh_mask(__U, __A, 4);
+}
+
+__mmask8 test_mm_fpclass_pbh_mask(__m128bh __A) {
+ // CIR-LABEL: _mm_fpclass_pbh_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx10.fpclass.bf16.128"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm_fpclass_pbh_mask
+ // LLVM: %[[A:.*]] = call <8 x i1> @llvm.x86.avx10.fpclass.bf16.128
+ // LLVM: %[[B:.*]] = and <8 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <8 x i1> %[[B]] to i8
+
+ // OGCG-LABEL: test_mm_fpclass_pbh_mask
+ // OGCG: %[[A:.*]] = call <8 x i1> @llvm.x86.avx10.fpclass.bf16.128
+ // OGCG: bitcast <8 x i1> %[[A]] to i8
+ return _mm_fpclass_pbh_mask(__A, 4);
}
\ No newline at end of file
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
index 3475e186e0c8f..dec1aa8503234 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
@@ -323,3 +323,81 @@ unsigned char test_ktestz_mask16_u8(__mmask16 A, __mmask16 B) {
// OGCG: trunc i32 %[[RES]] to i8
return _ktestz_mask16_u8(A, B);
}
+
+__mmask8 test_mm512_mask_fpclass_pd_mask(__mmask8 __U, __m512d __A) {
+ // CIR-LABEL: _mm512_mask_fpclass_pd_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.pd.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm512_mask_fpclass_pd_mask
+ // LLVM: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.pd.512
+ // LLVM: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // LLVM: %[[C:.*]] = and <8 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <8 x i1> %[[C]] to i8
+
+ // OGCG-LABEL: test_mm512_mask_fpclass_pd_mask
+ // OGCG: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.pd.512
+ // OGCG: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // OGCG: %[[C:.*]] = and <8 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <8 x i1> %[[C]] to i8
+ return _mm512_mask_fpclass_pd_mask(__U, __A, 4);
+}
+
+__mmask8 test_mm512_fpclass_pd_mask(__m512d __A) {
+ // CIR-LABEL: _mm512_fpclass_pd_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.pd.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm512_fpclass_pd_mask
+ // LLVM: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.pd.512
+ // LLVM: %[[B:.*]] = and <8 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <8 x i1> %[[B]] to i8
+
+ // OGCG-LABEL: test_mm512_fpclass_pd_mask
+ // OGCG: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.pd.512
+ // OGCG: bitcast <8 x i1> %[[A]] to i8
+ return _mm512_fpclass_pd_mask(__A, 4);
+}
+
+__mmask16 test_mm512_mask_fpclass_ps_mask(__mmask16 __U, __m512 __A) {
+ // CIR-LABEL: _mm512_mask_fpclass_ps_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.ps.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u16i -> !cir.vector<16 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<16 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<16 x !cir.bool> -> !u16i
+
+ // LLVM-LABEL: test_mm512_mask_fpclass_ps_mask
+ // LLVM: %[[A:.*]] = call <16 x i1> @llvm.x86.avx512.fpclass.ps.512
+ // LLVM: %[[B:.*]] = bitcast i16 {{.*}} to <16 x i1>
+ // LLVM: %[[C:.*]] = and <16 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <16 x i1> %[[C]] to i16
+
+ // OGCG-LABEL: test_mm512_mask_fpclass_ps_mask
+ // OGCG: %[[A:.*]] = call <16 x i1> @llvm.x86.avx512.fpclass.ps.512
+ // OGCG: %[[B:.*]] = bitcast i16 {{.*}} to <16 x i1>
+ // OGCG: %[[C:.*]] = and <16 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <16 x i1> %[[C]] to i16
+ return _mm512_mask_fpclass_ps_mask(__U, __A, 4);
+}
+
+__mmask16 test_mm512_fpclass_ps_mask(__m512 __A) {
+ // CIR-LABEL: _mm512_fpclass_ps_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.ps.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u16i -> !cir.vector<16 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<16 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<16 x !cir.bool> -> !u16i
+
+ // LLVM-LABEL: test_mm512_fpclass_ps_mask
+ // LLVM: %[[A:.*]] = call <16 x i1> @llvm.x86.avx512.fpclass.ps.512
+ // LLVM: %[[B:.*]] = and <16 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <16 x i1> %[[B]] to i16
+
+ // OGCG-LABEL: test_mm512_fpclass_ps_mask
+ // OGCG: %[[A:.*]] = call <16 x i1> @llvm.x86.avx512.fpclass.ps.512
+ // OGCG: bitcast <16 x i1> %[[A]] to i16
+ return _mm512_fpclass_ps_mask(__A, 4);
+}
\ No newline at end of file
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
index 464fa29fffc20..bea5c249b3c0b 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
@@ -124,3 +124,43 @@ _Float16 test_mm512_reduce_min_ph(__m512h __W) {
// OGCG: call nnan {{.*}}half @llvm.vector.reduce.fmin.v32f16(<32 x half> %{{.*}})
return _mm512_reduce_min_ph(__W);
}
+
+
+__mmask32 test_mm512_mask_fpclass_ph_mask(__mmask32 __U, __m512h __A) {
+ // CIR-LABEL: _mm512_mask_fpclass_ph_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512fp16.fpclass.ph.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u32i -> !cir.vector<32 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<32 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<32 x !cir.bool> -> !u32i
+
+ // LLVM-LABEL: test_mm512_mask_fpclass_ph_mask
+ // LLVM: %[[A:.*]] = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512
+ // LLVM: %[[B:.*]] = bitcast i32 {{.*}} to <32 x i1>
+ // LLVM: %[[C:.*]] = and <32 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <32 x i1> %[[C]] to i32
+
+ // OGCG-LABEL: test_mm512_mask_fpclass_ph_mask
+ // OGCG: %[[A:.*]] = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512
+ // OGCG: %[[B:.*]] = bitcast i32 {{.*}} to <32 x i1>
+ // OGCG: %[[C:.*]] = and <32 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <32 x i1> %[[C]] to i32
+ return _mm512_mask_fpclass_ph_mask(__U, __A, 4);
+}
+
+__mmask32 test_mm512_fpclass_ph_mask(__m512h __A) {
+ // CIR-LABEL: _mm512_fpclass_ph_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512fp16.fpclass.ph.512"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u32i -> !cir.vector<32 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<32 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<32 x !cir.bool> -> !u32i
+
+ // LLVM-LABEL: test_mm512_fpclass_ph_mask
+ // LLVM: %[[A:.*]] = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512
+ // LLVM: %[[B:.*]] = and <32 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <32 x i1> %[[B]] to i32
+
+ // OGCG-LABEL: test_mm512_fpclass_ph_mask
+ // OGCG: %[[A:.*]] = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512
+ // OGCG: bitcast <32 x i1> %[[A]] to i32
+ return _mm512_fpclass_ph_mask(__A, 4);
+}
\ No newline at end of file
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
index 9ba3e19d41566..ea9bce4f5e7b1 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
@@ -231,4 +231,3 @@ __m128d test_mm_maskz_expand_pd(__mmask8 __U, __m128d __A) {
return _mm_maskz_expand_pd(__U,__A);
}
-
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
new file mode 100644
index 0000000000000..fd4ecdbde6228
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
@@ -0,0 +1,420 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512dq -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512dq -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512dq -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s
+
+
+#include <immintrin.h>
+
+__m128d test_mm_mmask_i64gather_pd(__m128d __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mmask_i64gather_pd
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div2.df"
+
+ // LLVM-LABEL: @test_mm_mmask_i64gather_pd
+ // LLVM: @llvm.x86.avx512.mask.gather3div2.df
+
+ // OGCG-LABEL: @test_mm_mmask_i64gather_pd
+ // OGCG: @llvm.x86.avx512.mask.gather3div2.df
+ return _mm_mmask_i64gather_pd(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128i test_mm_mmask_i64gather_epi64(__m128i __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mmask_i64gather_epi64
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div2.di"
+
+ // LLVM-LABEL: @test_mm_mmask_i64gather_epi64
+ // LLVM: @llvm.x86.avx512.mask.gather3div2.di
+
+ // OGCG-LABEL: @test_mm_mmask_i64gather_epi64
+ // OGCG: @llvm.x86.avx512.mask.gather3div2.di
+ return _mm_mmask_i64gather_epi64(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m256d test_mm256_mmask_i64gather_pd(__m256d __v1_old, __mmask8 __mask, __m256i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mmask_i64gather_pd
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div4.df"
+
+ // LLVM-LABEL: @test_mm256_mmask_i64gather_pd
+ // LLVM: @llvm.x86.avx512.mask.gather3div4.df
+
+ // OGCG-LABEL: @test_mm256_mmask_i64gather_pd
+ // OGCG: @llvm.x86.avx512.mask.gather3div4.df
+ return _mm256_mmask_i64gather_pd(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m256i test_mm256_mmask_i64gather_epi64(__m256i __v1_old, __mmask8 __mask, __m256i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mmask_i64gather_epi64
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div4.di"
+
+ // LLVM-LABEL: @test_mm256_mmask_i64gather_epi64
+ // LLVM: @llvm.x86.avx512.mask.gather3div4.di
+
+ // OGCG-LABEL: @test_mm256_mmask_i64gather_epi64
+ // OGCG: @llvm.x86.avx512.mask.gather3div4.di
+ return _mm256_mmask_i64gather_epi64(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128 test_mm_mmask_i64gather_ps(__m128 __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mmask_i64gather_ps
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div4.sf"
+
+ // LLVM-LABEL: @test_mm_mmask_i64gather_ps
+ // LLVM: @llvm.x86.avx512.mask.gather3div4.sf
+
+ // OGCG-LABEL: @test_mm_mmask_i64gather_ps
+ // OGCG: @llvm.x86.avx512.mask.gather3div4.sf
+ return _mm_mmask_i64gather_ps(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128i test_mm_mmask_i64gather_epi32(__m128i __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mmask_i64gather_epi32
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div4.si"
+
+ // LLVM-LABEL: @test_mm_mmask_i64gather_epi32
+ // LLVM: @llvm.x86.avx512.mask.gather3div4.si
+
+ // OGCG-LABEL: @test_mm_mmask_i64gather_epi32
+ // OGCG: @llvm.x86.avx512.mask.gather3div4.si
+ return _mm_mmask_i64gather_epi32(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128 test_mm256_mmask_i64gather_ps(__m128 __v1_old, __mmask8 __mask, __m256i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mmask_i64gather_ps
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div8.sf"
+
+ // LLVM-LABEL: @test_mm256_mmask_i64gather_ps
+ // LLVM: @llvm.x86.avx512.mask.gather3div8.sf
+
+ // OGCG-LABEL: @test_mm256_mmask_i64gather_ps
+ // OGCG: @llvm.x86.avx512.mask.gather3div8.sf
+ return _mm256_mmask_i64gather_ps(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128i test_mm256_mmask_i64gather_epi32(__m128i __v1_old, __mmask8 __mask, __m256i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mmask_i64gather_epi32
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3div8.si"
+
+ // LLVM-LABEL: @test_mm256_mmask_i64gather_epi32
+ // LLVM: @llvm.x86.avx512.mask.gather3div8.si
+
+ // OGCG-LABEL: @test_mm256_mmask_i64gather_epi32
+ // OGCG: @llvm.x86.avx512.mask.gather3div8.si
+ return _mm256_mmask_i64gather_epi32(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128d test_mm_mask_i32gather_pd(__m128d __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mask_i32gather_pd
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv2.df"
+
+ // LLVM-LABEL: @test_mm_mask_i32gather_pd
+ // LLVM: @llvm.x86.avx512.mask.gather3siv2.df
+
+ // OGCG-LABEL: @test_mm_mask_i32gather_pd
+ // OGCG: @llvm.x86.avx512.mask.gather3siv2.df
+ return _mm_mmask_i32gather_pd(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128i test_mm_mask_i32gather_epi64(__m128i __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mask_i32gather_epi64
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv2.di"
+
+ // LLVM-LABEL: @test_mm_mask_i32gather_epi64
+ // LLVM: @llvm.x86.avx512.mask.gather3siv2.di
+
+ // OGCG-LABEL: @test_mm_mask_i32gather_epi64
+ // OGCG: @llvm.x86.avx512.mask.gather3siv2.di
+ return _mm_mmask_i32gather_epi64(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m256d test_mm256_mask_i32gather_pd(__m256d __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mask_i32gather_pd
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv4.df"
+
+ // LLVM-LABEL: @test_mm256_mask_i32gather_pd
+ // LLVM: @llvm.x86.avx512.mask.gather3siv4.df
+
+ // OGCG-LABEL: @test_mm256_mask_i32gather_pd
+ // OGCG: @llvm.x86.avx512.mask.gather3siv4.df
+ return _mm256_mmask_i32gather_pd(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m256i test_mm256_mask_i32gather_epi64(__m256i __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mask_i32gather_epi64
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv4.di"
+
+ // LLVM-LABEL: @test_mm256_mask_i32gather_epi64
+ // LLVM: @llvm.x86.avx512.mask.gather3siv4.di
+
+ // OGCG-LABEL: @test_mm256_mask_i32gather_epi64
+ // OGCG: @llvm.x86.avx512.mask.gather3siv4.di
+ return _mm256_mmask_i32gather_epi64(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128 test_mm_mask_i32gather_ps(__m128 __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mask_i32gather_ps
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv4.sf"
+
+ // LLVM-LABEL: @test_mm_mask_i32gather_ps
+ // LLVM: @llvm.x86.avx512.mask.gather3siv4.sf
+
+ // OGCG-LABEL: @test_mm_mask_i32gather_ps
+ // OGCG: @llvm.x86.avx512.mask.gather3siv4.sf
+ return _mm_mmask_i32gather_ps(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128i test_mm_mask_i32gather_epi32(__m128i __v1_old, __mmask8 __mask, __m128i __index, void const *__addr) {
+ // CIR-LABEL: test_mm_mask_i32gather_epi32
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv4.si"
+
+ // LLVM-LABEL: @test_mm_mask_i32gather_epi32
+ // LLVM: @llvm.x86.avx512.mask.gather3siv4.si
+
+ // OGCG-LABEL: @test_mm_mask_i32gather_epi32
+ // OGCG: @llvm.x86.avx512.mask.gather3siv4.si
+ return _mm_mmask_i32gather_epi32(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m256 test_mm256_mask_i32gather_ps(__m256 __v1_old, __mmask8 __mask, __m256i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mask_i32gather_ps
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv8.sf"
+
+ // LLVM-LABEL: @test_mm256_mask_i32gather_ps
+ // LLVM: @llvm.x86.avx512.mask.gather3siv8.sf
+
+ // OGCG-LABEL: @test_mm256_mask_i32gather_ps
+ // OGCG: @llvm.x86.avx512.mask.gather3siv8.sf
+ return _mm256_mmask_i32gather_ps(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m256i test_mm256_mask_i32gather_epi32(__m256i __v1_old, __mmask8 __mask, __m256i __index, void const *__addr) {
+ // CIR-LABEL: test_mm256_mask_i32gather_epi32
+ // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.gather3siv8.si"
+
+ // LLVM-LABEL: @test_mm256_mask_i32gather_epi32
+ // LLVM: @llvm.x86.avx512.mask.gather3siv8.si
+
+ // OGCG-LABEL: @test_mm256_mask_i32gather_epi32
+ // OGCG: @llvm.x86.avx512.mask.gather3siv8.si
+ return _mm256_mmask_i32gather_epi32(__v1_old, __mask, __index, __addr, 2);
+}
+
+__m128d test_mm_mask_expand_pd(__m128d __W, __mmask8 __U, __m128d __A) {
+ // CIR-LABEL: _mm_mask_expand_pd
+ // CIR: %[[MASK:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.int<u, 1>>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[MASK]], %[[MASK]] : !cir.vector<8 x !cir.int<u, 1>>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<2 x !cir.int<u, 1>>
+
+ // LLVM-LABEL: test_mm_mask_expand_pd
+ // LLVM: %[[BC:.*]] = bitcast i8 %{{.*}} to <8 x i1>
+ // LLVM: %[[SHUF:.*]] = shufflevector <8 x i1> %[[BC]], <8 x i1> %[[BC]], <2 x i32> <i32 0, i32 1>
+
+ // OGCG-LABEL: test_mm_mask_expand_pd
+ // OGCG: %[[BC:.*]] = bitcast i8 %{{.*}} to <8 x i1>
+ // OGCG: %[[SHUF:.*]] = shufflevector <8 x i1> %[[BC]], <8 x i1> %[[BC]], <2 x i32> <i32 0, i32 1>
+
+ return _mm_mask_expand_pd(__W,__U,__A);
+}
+
+__m128d test_mm_maskz_expand_pd(__mmask8 __U, __m128d __A) {
+ // CIR-LABEL: _mm_maskz_expand_pd
+ // CIR: %[[MASK:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.int<u, 1>>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[MASK]], %[[MASK]] : !cir.vector<8 x !cir.int<u, 1>>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<2 x !cir.int<u, 1>>
+
+ // LLVM-LABEL: test_mm_maskz_expand_pd
+ // LLVM: %[[BC:.*]] = bitcast i8 %{{.*}} to <8 x i1>
+ // LLVM: %[[SHUF:.*]] = shufflevector <8 x i1> %[[BC]], <8 x i1> %[[BC]], <2 x i32> <i32 0, i32 1>
+
+ // OGCG-LABEL: test_mm_maskz_expand_pd
+ // OGCG: %[[BC:.*]] = bitcast i8 %{{.*}} to <8 x i1>
+ // OGCG: %[[SHUF:.*]] = shufflevector <8 x i1> %[[BC]], <8 x i1> %[[BC]], <2 x i32> <i32 0, i32 1>
+
+ return _mm_maskz_expand_pd(__U,__A);
+}
+
+__mmask8 test_mm_mask_fpclass_pd_mask(__mmask8 __U, __m128d __A) {
+ // CIR-LABEL: _mm_mask_fpclass_pd_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.pd.128"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[B]], %[[B]] : !cir.vector<8 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<2 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[SHUF]]) : !cir.vector<2 x !cir.bool>
+ // CIR: %[[D:.*]] = cir.const #cir.zero : !cir.vector<2 x !cir.bool>
+ // CIR: %[[E:.*]] = cir.vec.shuffle(%[[C]], %[[D]] : !cir.vector<2 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[E]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm_mask_fpclass_pd_mask
+ // LLVM: %[[A:.*]] = call <2 x i1> @llvm.x86.avx512.fpclass.pd.128
+ // LLVM: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // LLVM: %[[C:.*]] = shufflevector <8 x i1> %[[B]], <8 x i1> %[[B]], <2 x i32> <i32 0, i32 1>
+ // LLVM: %[[D:.*]] = and <2 x i1> %[[A]], %[[C]]
+ // LLVM: %[[E:.*]] = shufflevector <2 x i1> %[[D]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ // LLVM: bitcast <8 x i1> %[[E]] to i8
+
+ // OGCG-LABEL: test_mm_mask_fpclass_pd_mask
+ // OGCG: %[[A:.*]] = call <2 x i1> @llvm.x86.avx512.fpclass.pd.128
+ // OGCG: and <2 x i1>
+ // OGCG: shufflevector
+ // OGCG: bitcast <8 x i1> {{.*}} to i8
+ return _mm_mask_fpclass_pd_mask(__U, __A, 2);
+}
+
+__mmask8 test_mm_fpclass_pd_mask(__m128d __A) {
+ // CIR-LABEL: _mm_fpclass_pd_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.pd.128"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[B]], %[[B]] : !cir.vector<8 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<2 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[SHUF]]) : !cir.vector<2 x !cir.bool>
+ // CIR: %[[D:.*]] = cir.const #cir.zero : !cir.vector<2 x !cir.bool>
+ // CIR: %[[E:.*]] = cir.vec.shuffle(%[[C]], %[[D]] : !cir.vector<2 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[E]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm_fpclass_pd_mask
+ // LLVM: %[[A:.*]] = call <2 x i1> @llvm.x86.avx512.fpclass.pd.128
+ // LLVM: %[[B:.*]] = and <2 x i1> %[[A]], splat (i1 true)
+ // LLVM: %[[C:.*]] = shufflevector <2 x i1> %[[B]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ // LLVM: bitcast <8 x i1> %[[C]] to i8
+
+ // OGCG-LABEL: test_mm_fpclass_pd_mask
+ // OGCG: %[[A:.*]] = call <2 x i1> @llvm.x86.avx512.fpclass.pd.128
+ // OGCG: shufflevector
+ // OGCG: bitcast <8 x i1> {{.*}} to i8
+ return _mm_fpclass_pd_mask(__A, 2);
+}
+
+__mmask8 test_mm256_mask_fpclass_pd_mask(__mmask8 __U, __m256d __A) {
+ // CIR-LABEL: _mm256_mask_fpclass_pd_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.pd.256"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[B]], %[[B]] : !cir.vector<8 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[SHUF]]) : !cir.vector<4 x !cir.bool>
+ // CIR: %[[D:.*]] = cir.const #cir.zero : !cir.vector<4 x !cir.bool>
+ // CIR: %[[E:.*]] = cir.vec.shuffle(%[[C]], %[[D]] : !cir.vector<4 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[E]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm256_mask_fpclass_pd_mask
+ // LLVM: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.pd.256
+ // LLVM: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // LLVM: %[[C:.*]] = shufflevector <8 x i1> %[[B]], <8 x i1> %[[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ // LLVM: %[[D:.*]] = and <4 x i1> %[[A]], %[[C]]
+ // LLVM: %[[E:.*]] = shufflevector <4 x i1> %[[D]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ // LLVM: bitcast <8 x i1> %[[E]] to i8
+
+ // OGCG-LABEL: test_mm256_mask_fpclass_pd_mask
+ // OGCG: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.pd.256
+ // OGCG: and <4 x i1>
+ // OGCG: shufflevector
+ // OGCG: bitcast <8 x i1> {{.*}} to i8
+ return _mm256_mask_fpclass_pd_mask(__U, __A, 2);
+}
+
+__mmask8 test_mm256_fpclass_pd_mask(__m256d __A) {
+ // CIR-LABEL: _mm256_fpclass_pd_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.pd.256"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[B]], %[[B]] : !cir.vector<8 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[SHUF]]) : !cir.vector<4 x !cir.bool>
+ // CIR: %[[D:.*]] = cir.const #cir.zero : !cir.vector<4 x !cir.bool>
+ // CIR: %[[E:.*]] = cir.vec.shuffle(%[[C]], %[[D]] : !cir.vector<4 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[E]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm256_fpclass_pd_mask
+ // LLVM: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.pd.256
+ // LLVM: %[[B:.*]] = and <4 x i1> %[[A]], splat (i1 true)
+ // LLVM: %[[C:.*]] = shufflevector <4 x i1> %[[B]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ // LLVM: bitcast <8 x i1> %[[C]] to i8
+
+ // OGCG-LABEL: test_mm256_fpclass_pd_mask
+ // OGCG: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.pd.256
+ // OGCG: shufflevector
+ // OGCG: bitcast <8 x i1> {{.*}} to i8
+ return _mm256_fpclass_pd_mask(__A, 2);
+}
+
+__mmask8 test_mm_mask_fpclass_ps_mask(__mmask8 __U, __m128 __A) {
+ // CIR-LABEL: _mm_mask_fpclass_ps_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.ps.128"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[B]], %[[B]] : !cir.vector<8 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[SHUF]]) : !cir.vector<4 x !cir.bool>
+ // CIR: %[[D:.*]] = cir.const #cir.zero : !cir.vector<4 x !cir.bool>
+ // CIR: %[[E:.*]] = cir.vec.shuffle(%[[C]], %[[D]] : !cir.vector<4 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[E]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm_mask_fpclass_ps_mask
+ // LLVM: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.ps.128
+ // LLVM: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // LLVM: %[[C:.*]] = shufflevector <8 x i1> %[[B]], <8 x i1> %[[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ // LLVM: %[[D:.*]] = and <4 x i1> %[[A]], %[[C]]
+ // LLVM: %[[E:.*]] = shufflevector <4 x i1> %[[D]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ // LLVM: bitcast <8 x i1> %[[E]] to i8
+
+ // OGCG-LABEL: test_mm_mask_fpclass_ps_mask
+ // OGCG: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.ps.128
+ // OGCG: and <4 x i1>
+ // OGCG: shufflevector
+ // OGCG: bitcast <8 x i1> {{.*}} to i8
+ return _mm_mask_fpclass_ps_mask(__U, __A, 2);
+}
+
+__mmask8 test_mm_fpclass_ps_mask(__m128 __A) {
+ // CIR-LABEL: _mm_fpclass_ps_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.ps.128"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[SHUF:.*]] = cir.vec.shuffle(%[[B]], %[[B]] : !cir.vector<8 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[SHUF]]) : !cir.vector<4 x !cir.bool>
+ // CIR: %[[D:.*]] = cir.const #cir.zero : !cir.vector<4 x !cir.bool>
+ // CIR: %[[E:.*]] = cir.vec.shuffle(%[[C]], %[[D]] : !cir.vector<4 x !cir.bool>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[E]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm_fpclass_ps_mask
+ // LLVM: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.ps.128
+ // LLVM: %[[B:.*]] = and <4 x i1> %[[A]], splat (i1 true)
+ // LLVM: %[[C:.*]] = shufflevector <4 x i1> %[[B]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ // LLVM: bitcast <8 x i1> %[[C]] to i8
+
+ // OGCG-LABEL: test_mm_fpclass_ps_mask
+ // OGCG: %[[A:.*]] = call <4 x i1> @llvm.x86.avx512.fpclass.ps.128
+ // OGCG: shufflevector
+ // OGCG: bitcast <8 x i1> {{.*}} to i8
+ return _mm_fpclass_ps_mask(__A, 2);
+}
+
+__mmask8 test_mm256_mask_fpclass_ps_mask(__mmask8 __U, __m256 __A) {
+ // CIR-LABEL: _mm256_mask_fpclass_ps_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.ps.256"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm256_mask_fpclass_ps_mask
+ // LLVM: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.ps.256
+ // LLVM: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // LLVM: %[[C:.*]] = and <8 x i1> %[[A]], %[[B]]
+ // LLVM: bitcast <8 x i1> %[[C]] to i8
+
+ // OGCG-LABEL: test_mm256_mask_fpclass_ps_mask
+ // OGCG: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.ps.256
+ // OGCG: %[[B:.*]] = bitcast i8 {{.*}} to <8 x i1>
+ // OGCG: %[[C:.*]] = and <8 x i1> %[[A]], %[[B]]
+ // OGCG: bitcast <8 x i1> %[[C]] to i8
+ return _mm256_mask_fpclass_ps_mask(__U, __A, 2);
+}
+
+__mmask8 test_mm256_fpclass_ps_mask(__m256 __A) {
+ // CIR-LABEL: _mm256_fpclass_ps_mask
+ // CIR: %[[A:.*]] = cir.call_llvm_intrinsic "x86.avx512.fpclass.ps.256"
+ // CIR: %[[B:.*]] = cir.cast bitcast {{.*}} : !u8i -> !cir.vector<8 x !cir.bool>
+ // CIR: %[[C:.*]] = cir.binop(and, %[[A]], %[[B]]) : !cir.vector<8 x !cir.bool>
+ // CIR: cir.cast bitcast %[[C]] : !cir.vector<8 x !cir.bool> -> !u8i
+
+ // LLVM-LABEL: test_mm256_fpclass_ps_mask
+ // LLVM: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.ps.256
+ // LLVM: %[[B:.*]] = and <8 x i1> %[[A]], splat (i1 true)
+ // LLVM: bitcast <8 x i1> %[[B]] to i8
+
+ // OGCG-LABEL: test_mm256_fpclass_ps_mask
+ // OGCG: %[[A:.*]] = call <8 x i1> @llvm.x86.avx512.fpclass.ps.256
+ // OGCG: bitcast <8 x i1> %[[A]] to i8
+ return _mm256_fpclass_ps_mask(__A, 2);
+}
+
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