[clang] [CIR][AArch64] Add lowering for `svlen` builtins (1/2) (PR #172346)

[Andy Kaylor via cfe-commits]

Andrzej =?utf-8?q?Warzy=C5=84ski?= <andrzej.warzynski at gmail.com>,
Andrzej =?utf-8?q?Warzy=C5=84ski?= <andrzej.warzynski at gmail.com>,
Andrzej =?utf-8?q?Warzy=C5=84ski?= <andrzej.warzynski at gmail.com>,Andrzej
 Warzynski <andrzej.warzynski at arm.com>,Andrzej Warzynski
 <andrzej.warzynski at arm.com>,Andrzej Warzynski <andrzej.warzynski at arm.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/172346 at github.com>


================
@@ -444,19 +445,21 @@ def CIR_VectorType : CIR_Type<"Vector", "vector", [
   }];
 
   let parameters = (ins
-    CIR_VectorElementType:$elementType,
-    "uint64_t":$size
+    CIR_VectorElementType:$element_type,
+    "uint64_t":$size,
+    OptionalParameter<"bool">:$is_scalable
   );
 
   let assemblyFormat = [{
-    `<` $size `x` $elementType `>`
+    `<` $size `x` $element_type `>`
   }];
 
   let builders = [
     TypeBuilderWithInferredContext<(ins
-      "mlir::Type":$elementType, "uint64_t":$size
+      "mlir::Type":$element_type, "uint64_t":$size, CArg<"bool",
+      "false">:$isScalable
----------------
andykaylor wrote:

```suggestion
      "false">:$is_scalable
```

https://github.com/llvm/llvm-project/pull/172346