[clang] [CIR][AArch64] Add lowering for `svlen` builtins (1/2) (PR #172346)

[Andrzej Warzyński via cfe-commits]

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@@ -588,16 +588,15 @@ class CIRBaseBuilderTy : public mlir::OpBuilder {
 
   cir::CmpOp createCompare(mlir::Location loc, cir::CmpOpKind kind,
                            mlir::Value lhs, mlir::Value rhs) {
-    return cir::CmpOp::create(*this, loc, kind, lhs, rhs);
+    return cir::CmpOp::create(*this, loc, getBoolTy(), kind, lhs, rhs);
   }
 
   cir::VecCmpOp createVecCompare(mlir::Location loc, cir::CmpOpKind kind,
                                  mlir::Value lhs, mlir::Value rhs) {
     VectorType vecCast = mlir::cast<VectorType>(lhs.getType());
     IntType integralTy =
         getSIntNTy(getCIRIntOrFloatBitWidth(vecCast.getElementType()));
-    VectorType integralVecTy =
-        VectorType::get(context, integralTy, vecCast.getSize());
+    VectorType integralVecTy = VectorType::get(integralTy, vecCast.getSize());
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banach-space wrote:

Yeah, the name clash is a bit unfortunate.

https://github.com/llvm/llvm-project/pull/172346