[clang] [CIR][AArch64] Add lowering for `svlen` builtins (1/2) (PR #172346)

[Andrzej Warzyński via cfe-commits]

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@@ -41,6 +53,16 @@ CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID,
     return mlir::Value{};
   }
 
+  mlir::Location loc = getLoc(expr->getExprLoc());
+  // Generate vscale * scalingFactor
+  auto vscaleTimesFactor = [&](int32_t scalingFactor) {
+    StringRef intrinsicName = "vscale.i64";
+    auto vscale = emitIntrinsicCallOp(builder, loc, intrinsicName,
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banach-space wrote:

> Do you think it's useful to add a cir.vscale operation to make this easier to identify in transformation passes?

Yes, similar op in `Vector` ([vector.vscale](https://mlir.llvm.org/docs/Dialects/Vector/#vectorvscale-vectorvectorscaleop)) is widely used. That said, I'm not sure how helpful `cir.vscale` would be just now.

In any case, I am in favour, but I'd defer to a separate PR. Note, we still need to "fix" how scalable vectors are printed in CIR.

https://github.com/llvm/llvm-project/pull/172346