[clang] [CIR][CIRGen][Builtin][X86] Masked compress Intrinsics (PR #169582)

[via cfe-commits]

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@@ -151,6 +151,17 @@ computeFullLaneShuffleMask(CIRGenFunction &cgf, const mlir::Value vec,
 
   outIndices.resize(numElts);
 }
+static mlir::Value emitX86CompressExpand(CIRGenBuilderTy &builder,
+                                         mlir::Location loc, mlir::Value source,
+                                         mlir::Value mask,
+                                         mlir::Value inputVector,
+                                         const std::string &id) {
+  auto ResultTy = cast<cir::VectorType>(mask.getType());
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cs25resch11005-bhuvan wrote:

Addressed in the latest commit

https://github.com/llvm/llvm-project/pull/169582