[clang] [CIR][CIRGen][Builtin][X86] Masked compress Intrinsics (PR #169582)

[Andy Kaylor via cfe-commits]

================
@@ -151,6 +151,17 @@ computeFullLaneShuffleMask(CIRGenFunction &cgf, const mlir::Value vec,
 
   outIndices.resize(numElts);
 }
+static mlir::Value emitX86CompressExpand(CIRGenBuilderTy &builder,
+                                         mlir::Location loc, mlir::Value source,
+                                         mlir::Value mask,
+                                         mlir::Value inputVector,
+                                         const std::string &id) {
+  auto ResultTy = cast<cir::VectorType>(mask.getType());
+  mlir::Value MaskValue = getMaskVecValue(
+      builder, loc, inputVector, cast<cir::VectorType>(ResultTy).getSize());
+  return emitIntrinsicCallOp(builder, loc, id, ResultTy,
+                             mlir::ValueRange{source, mask, MaskValue});
----------------
andykaylor wrote:

```suggestion
  mlir::Value maskValue = getMaskVecValue(
      builder, loc, inputVector, cast<cir::VectorType>(resultTy).getSize());
  return emitIntrinsicCallOp(builder, loc, id, resultTy,
                             mlir::ValueRange{source, mask, maskValue});
```

https://github.com/llvm/llvm-project/pull/169582