[clang] [WIP][SPARC][clang] Add condition code register names for inline asm (PR #168498)

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https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/168498

>From 0139d65db2f7046f12e13c2d073473e5ba132daa Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Tue, 18 Nov 2025 15:03:07 +0700
Subject: [PATCH 1/2] [SPARC][clang] Add condition code register names for
 inline asm

---
 clang/lib/Basic/Targets/Sparc.cpp | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/clang/lib/Basic/Targets/Sparc.cpp b/clang/lib/Basic/Targets/Sparc.cpp
index d1a891092b0f5..7173ac8c22ceb 100644
--- a/clang/lib/Basic/Targets/Sparc.cpp
+++ b/clang/lib/Basic/Targets/Sparc.cpp
@@ -19,6 +19,7 @@ using namespace clang;
 using namespace clang::targets;
 
 const char *const SparcTargetInfo::GCCRegNames[] = {
+    // clang-format off
     // Integer registers
     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
     "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
@@ -30,6 +31,10 @@ const char *const SparcTargetInfo::GCCRegNames[] = {
     "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "f32",
     "f34", "f36", "f38", "f40", "f42", "f44", "f46", "f48", "f50", "f52", "f54",
     "f56", "f58", "f60", "f62",
+
+    // Condition code registers
+    "icc", "fcc", "fcc1", "fcc2", "fcc3"
+    // clang-format on
 };
 
 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
@@ -37,14 +42,17 @@ ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
 }
 
 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
-    {{"g0"}, "r0"},  {{"g1"}, "r1"},  {{"g2"}, "r2"},        {{"g3"}, "r3"},
-    {{"g4"}, "r4"},  {{"g5"}, "r5"},  {{"g6"}, "r6"},        {{"g7"}, "r7"},
-    {{"o0"}, "r8"},  {{"o1"}, "r9"},  {{"o2"}, "r10"},       {{"o3"}, "r11"},
-    {{"o4"}, "r12"}, {{"o5"}, "r13"}, {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},
-    {{"l0"}, "r16"}, {{"l1"}, "r17"}, {{"l2"}, "r18"},       {{"l3"}, "r19"},
-    {{"l4"}, "r20"}, {{"l5"}, "r21"}, {{"l6"}, "r22"},       {{"l7"}, "r23"},
-    {{"i0"}, "r24"}, {{"i1"}, "r25"}, {{"i2"}, "r26"},       {{"i3"}, "r27"},
-    {{"i4"}, "r28"}, {{"i5"}, "r29"}, {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},
+    // clang-format off
+    {{"g0"}, "r0"},   {{"g1"}, "r1"},    {{"g2"}, "r2"},        {{"g3"}, "r3"},
+    {{"g4"}, "r4"},   {{"g5"}, "r5"},    {{"g6"}, "r6"},        {{"g7"}, "r7"},
+    {{"o0"}, "r8"},   {{"o1"}, "r9"},    {{"o2"}, "r10"},       {{"o3"}, "r11"},
+    {{"o4"}, "r12"},  {{"o5"}, "r13"},   {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},
+    {{"l0"}, "r16"},  {{"l1"}, "r17"},   {{"l2"}, "r18"},       {{"l3"}, "r19"},
+    {{"l4"}, "r20"},  {{"l5"}, "r21"},   {{"l6"}, "r22"},       {{"l7"}, "r23"},
+    {{"i0"}, "r24"},  {{"i1"}, "r25"},   {{"i2"}, "r26"},       {{"i3"}, "r27"},
+    {{"i4"}, "r28"},  {{"i5"}, "r29"},   {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},
+    {{"xcc"}, "icc"}, {{"fcc0"}, "fcc"}
+    // clang-format on
 };
 
 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {

>From cbc89c390762ccd85caa0493ecb24ed5968ecb93 Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Tue, 18 Nov 2025 21:14:43 +0700
Subject: [PATCH 2/2] Add tests and match names with GCC ones

---
 clang/lib/Basic/Targets/Sparc.cpp             | 21 ++++++++-----------
 .../test/CodeGen/Sparc/inline-asm-gcc-regs.c  | 13 ++++++++++++
 2 files changed, 22 insertions(+), 12 deletions(-)
 create mode 100644 clang/test/CodeGen/Sparc/inline-asm-gcc-regs.c

diff --git a/clang/lib/Basic/Targets/Sparc.cpp b/clang/lib/Basic/Targets/Sparc.cpp
index 7173ac8c22ceb..6f3c91ffc9f3e 100644
--- a/clang/lib/Basic/Targets/Sparc.cpp
+++ b/clang/lib/Basic/Targets/Sparc.cpp
@@ -33,7 +33,7 @@ const char *const SparcTargetInfo::GCCRegNames[] = {
     "f56", "f58", "f60", "f62",
 
     // Condition code registers
-    "icc", "fcc", "fcc1", "fcc2", "fcc3"
+    "icc", "fcc0", "fcc1", "fcc2", "fcc3"
     // clang-format on
 };
 
@@ -42,17 +42,14 @@ ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
 }
 
 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
-    // clang-format off
-    {{"g0"}, "r0"},   {{"g1"}, "r1"},    {{"g2"}, "r2"},        {{"g3"}, "r3"},
-    {{"g4"}, "r4"},   {{"g5"}, "r5"},    {{"g6"}, "r6"},        {{"g7"}, "r7"},
-    {{"o0"}, "r8"},   {{"o1"}, "r9"},    {{"o2"}, "r10"},       {{"o3"}, "r11"},
-    {{"o4"}, "r12"},  {{"o5"}, "r13"},   {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},
-    {{"l0"}, "r16"},  {{"l1"}, "r17"},   {{"l2"}, "r18"},       {{"l3"}, "r19"},
-    {{"l4"}, "r20"},  {{"l5"}, "r21"},   {{"l6"}, "r22"},       {{"l7"}, "r23"},
-    {{"i0"}, "r24"},  {{"i1"}, "r25"},   {{"i2"}, "r26"},       {{"i3"}, "r27"},
-    {{"i4"}, "r28"},  {{"i5"}, "r29"},   {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},
-    {{"xcc"}, "icc"}, {{"fcc0"}, "fcc"}
-    // clang-format on
+    {{"g0"}, "r0"},  {{"g1"}, "r1"},  {{"g2"}, "r2"},        {{"g3"}, "r3"},
+    {{"g4"}, "r4"},  {{"g5"}, "r5"},  {{"g6"}, "r6"},        {{"g7"}, "r7"},
+    {{"o0"}, "r8"},  {{"o1"}, "r9"},  {{"o2"}, "r10"},       {{"o3"}, "r11"},
+    {{"o4"}, "r12"}, {{"o5"}, "r13"}, {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},
+    {{"l0"}, "r16"}, {{"l1"}, "r17"}, {{"l2"}, "r18"},       {{"l3"}, "r19"},
+    {{"l4"}, "r20"}, {{"l5"}, "r21"}, {{"l6"}, "r22"},       {{"l7"}, "r23"},
+    {{"i0"}, "r24"}, {{"i1"}, "r25"}, {{"i2"}, "r26"},       {{"i3"}, "r27"},
+    {{"i4"}, "r28"}, {{"i5"}, "r29"}, {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},
 };
 
 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
diff --git a/clang/test/CodeGen/Sparc/inline-asm-gcc-regs.c b/clang/test/CodeGen/Sparc/inline-asm-gcc-regs.c
new file mode 100644
index 0000000000000..cf83b9afda4b2
--- /dev/null
+++ b/clang/test/CodeGen/Sparc/inline-asm-gcc-regs.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @icc
+// CHECK: call void asm sideeffect "nop", "~{icc}"()
+void icc() {
+  __asm__ __volatile__("nop" ::: "icc");
+}
+
+// CHECK-LABEL: @fcc
+// CHECK: call void asm sideeffect "nop", "~{fcc0},~{fcc1},~{fcc2},~{fcc3}"()
+void fcc() {
+  __asm__ __volatile__("nop" ::: "fcc0", "fcc1", "fcc2", "fcc3");
+}