[clang] [llvm] [X86] Remove AMX-TRANSPOSE (PR #165556)
Mikołaj Piróg via cfe-commits
cfe-commits at lists.llvm.org
Thu Oct 30 03:59:14 PDT 2025
https://github.com/mikolaj-pirog updated https://github.com/llvm/llvm-project/pull/165556
>From 12269e7679ad35c382fb477f38e2f79def1b813e Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 29 Oct 2025 13:17:46 +0100
Subject: [PATCH 1/6] Remove amx_transpose
---
clang/include/clang/Basic/BuiltinsX86_64.td | 89 -
clang/include/clang/Driver/Options.td | 2 -
clang/lib/Basic/Targets/X86.cpp | 6 -
clang/lib/CodeGen/TargetBuiltins/X86.cpp | 68 -
clang/lib/Headers/CMakeLists.txt | 6 -
clang/lib/Headers/amxbf16transposeintrin.h | 94 -
clang/lib/Headers/amxcomplextransposeintrin.h | 303 -
clang/lib/Headers/amxfp16transposeintrin.h | 94 -
clang/lib/Headers/amxintrin.h | 2 -
clang/lib/Headers/amxmovrstransposeintrin.h | 200 -
clang/lib/Headers/amxtf32transposeintrin.h | 105 -
clang/lib/Headers/amxtransposeintrin.h | 248 -
clang/lib/Headers/immintrin.h | 12 -
clang/lib/Sema/SemaX86.cpp | 17 -
clang/test/CodeGen/X86/amx_movrs_tranpose.c | 53 -
.../test/CodeGen/X86/amx_movrs_tranpose_api.c | 81 -
.../CodeGen/X86/amx_movrs_transpose_errors.c | 22 -
clang/test/CodeGen/X86/amx_tf32.c | 5 -
clang/test/CodeGen/X86/amx_tf32_api.c | 7 -
clang/test/CodeGen/X86/amx_tf32_errors.c | 8 -
clang/test/CodeGen/X86/amx_transpose.c | 75 -
clang/test/CodeGen/X86/amx_transpose_api.c | 114 -
clang/test/CodeGen/X86/amx_transpose_errors.c | 75 -
clang/test/Driver/x86-target-features.c | 7 -
.../Preprocessor/predefined-arch-macros.c | 2 -
clang/test/Preprocessor/x86_target_features.c | 12 -
llvm/include/llvm/CodeGen/TileShapeInfo.h | 88 +-
llvm/include/llvm/IR/IntrinsicsX86.td | 104 -
.../Support/X86DisassemblerDecoderCommon.h | 1 -
.../llvm/TargetParser/X86TargetParser.def | 1 -
llvm/lib/Target/X86/AsmParser/X86Operand.h | 31 -
.../X86/Disassembler/X86Disassembler.cpp | 5 -
.../X86/Disassembler/X86DisassemblerDecoder.h | 7 -
.../X86/MCTargetDesc/X86InstPrinterCommon.cpp | 19 -
.../X86/MCTargetDesc/X86InstPrinterCommon.h | 1 -
llvm/lib/Target/X86/X86.td | 6 +-
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 167 -
llvm/lib/Target/X86/X86FastPreTileConfig.cpp | 32 +-
llvm/lib/Target/X86/X86FastTileConfig.cpp | 6 -
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 78 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 155 +-
llvm/lib/Target/X86/X86InstrAMX.td | 208 -
llvm/lib/Target/X86/X86InstrInfo.cpp | 15 +-
llvm/lib/Target/X86/X86InstrOperands.td | 7 -
llvm/lib/Target/X86/X86InstrPredicates.td | 1 -
llvm/lib/Target/X86/X86LowerAMXType.cpp | 203 +-
llvm/lib/Target/X86/X86PreTileConfig.cpp | 9 -
llvm/lib/Target/X86/X86RegisterInfo.cpp | 70 +-
llvm/lib/Target/X86/X86RegisterInfo.td | 13 +-
llvm/lib/Target/X86/X86TileConfig.cpp | 83 +-
llvm/lib/TargetParser/Host.cpp | 1 -
llvm/lib/TargetParser/X86TargetParser.cpp | 2 +-
.../Inputs/reference_x86_vocab_print.txt | 22 -
.../reference_x86_vocab_wo=0.5_print.txt | 22 -
llvm/test/CodeGen/X86/amx-tf32-internal.ll | 7 +-
llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll | 12 +-
.../X86/amx_movrs_transpose_intrinsics.ll | 122 -
.../CodeGen/X86/amx_tile_pair_O2_to_O0.ll | 136 -
.../X86/amx_tile_pair_configure_O0.mir | 165 -
.../X86/amx_tile_pair_configure_O2.mir | 153 -
llvm/test/CodeGen/X86/amx_tile_pair_copy.mir | 97 -
.../X86/amx_tile_pair_lower_type_O0.ll | 87 -
.../X86/amx_tile_pair_lower_type_O2.ll | 61 -
.../X86/amx_tile_pair_preconfigure_O0.mir | 134 -
.../X86/amx_tile_pair_preconfigure_O2.mir | 113 -
.../CodeGen/X86/amx_transpose_intrinsics.ll | 371 -
llvm/test/CodeGen/X86/ipra-reg-usage.ll | 4 +-
.../Disassembler/X86/AMX/x86-64-amx-movrs.txt | 128 -
.../Disassembler/X86/AMX/x86-64-amx-tf32.txt | 8 -
.../MC/Disassembler/X86/amx-transpose-att.txt | 154 -
llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s | 128 -
llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s | 128 -
llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s | 7 -
llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s | 7 -
llvm/test/MC/X86/amx-transpose-att.s | 153 -
llvm/test/MC/X86/amx-transpose-intel.s | 153 -
llvm/test/TableGen/x86-instr-mapping.inc | 8 -
.../llvm-ir2vec/output/reference_triplets.txt | 52 +-
.../output/reference_x86_entities.txt | 11444 ++++++++--------
llvm/unittests/CodeGen/InstrRefLDVTest.cpp | 2 +-
llvm/utils/TableGen/X86RecognizableInstr.cpp | 1 -
81 files changed, 5810 insertions(+), 11089 deletions(-)
delete mode 100644 clang/lib/Headers/amxbf16transposeintrin.h
delete mode 100644 clang/lib/Headers/amxcomplextransposeintrin.h
delete mode 100644 clang/lib/Headers/amxfp16transposeintrin.h
delete mode 100644 clang/lib/Headers/amxmovrstransposeintrin.h
delete mode 100644 clang/lib/Headers/amxtf32transposeintrin.h
delete mode 100644 clang/lib/Headers/amxtransposeintrin.h
delete mode 100755 clang/test/CodeGen/X86/amx_movrs_tranpose.c
delete mode 100755 clang/test/CodeGen/X86/amx_movrs_tranpose_api.c
delete mode 100755 clang/test/CodeGen/X86/amx_movrs_transpose_errors.c
delete mode 100644 clang/test/CodeGen/X86/amx_transpose.c
delete mode 100644 clang/test/CodeGen/X86/amx_transpose_api.c
delete mode 100644 clang/test/CodeGen/X86/amx_transpose_errors.c
delete mode 100755 llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_O2_to_O0.ll
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_configure_O0.mir
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_configure_O2.mir
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_copy.mir
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O0.ll
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O2.ll
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir
delete mode 100644 llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O2.mir
delete mode 100644 llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
delete mode 100644 llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
delete mode 100644 llvm/test/MC/X86/amx-transpose-att.s
delete mode 100644 llvm/test/MC/X86/amx-transpose-intel.s
diff --git a/clang/include/clang/Basic/BuiltinsX86_64.td b/clang/include/clang/Basic/BuiltinsX86_64.td
index 275278c5ac089..062060e6afbbe 100644
--- a/clang/include/clang/Basic/BuiltinsX86_64.td
+++ b/clang/include/clang/Basic/BuiltinsX86_64.td
@@ -239,57 +239,6 @@ let Features = "amx-complex", Attributes = [NoThrow] in {
def tcmmrlfp16ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
}
-let Features = "amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz0_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-movrs,amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz0rs_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz0t1_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-movrs,amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz0rst1_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz1_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-movrs,amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz1rs_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz1t1_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-movrs,amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz1rst1_internal : X86Builtin<"void(unsigned short, unsigned short, unsigned short, _Vector<256, int *>, _Vector<256, int *>, void const *, size_t)">;
-}
-
-let Features = "amx-transpose", Attributes = [NoThrow] in {
- def ttransposed_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, _Vector<256, int>)">;
-}
-
-let Features = "amx-bf16,amx-transpose", Attributes = [NoThrow] in {
- def ttdpbf16ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
-}
-
-let Features = "amx-fp16,amx-transpose", Attributes = [NoThrow] in {
- def ttdpfp16ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
-}
-
-let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in {
- def ttcmmimfp16ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
- def ttcmmrlfp16ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
- def tconjtcmmimfp16ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
- def tconjtfp16_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, _Vector<256, int>)">;
-}
-
let Features = "amx-avx512,avx10.2", Attributes = [NoThrow] in {
def tcvtrowd2ps_internal : X86Builtin<"_Vector<16, float>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
def tcvtrowps2bf16h_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
@@ -303,10 +252,6 @@ let Features = "amx-tf32", Attributes = [NoThrow] in {
def tmmultf32ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
}
-let Features = "amx-tf32,amx-transpose", Attributes = [NoThrow] in {
- def ttmmultf32ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
-}
-
let Features = "amx-fp8", Attributes = [NoThrow] in {
def tdpbf8ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
def tdpbhf8ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
@@ -321,13 +266,6 @@ let Features = "amx-tile", Attributes = [NoThrow] in {
def tilezero : X86Builtin<"void(unsigned char)">;
}
-let Features = "amx-movrs,amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz0rs : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def t2rpntlvwz0rst1 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def t2rpntlvwz1rs : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def t2rpntlvwz1rst1 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
-}
-
let Features = "amx-movrs", Attributes = [NoThrow] in {
def tileloaddrs64 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
def tileloaddrst164 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
@@ -359,29 +297,6 @@ let Features = "amx-complex", Attributes = [NoThrow] in {
def tcmmrlfp16ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
}
-let Features = "amx-transpose", Attributes = [NoThrow] in {
- def t2rpntlvwz0 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def t2rpntlvwz0t1 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def t2rpntlvwz1 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def t2rpntlvwz1t1 : X86Builtin<"void(_Constant unsigned char, void const *, size_t)">;
- def ttransposed : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char)">;
-}
-
-let Features = "amx-bf16,amx-transpose", Attributes = [NoThrow] in {
- def ttdpbf16ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
-}
-
-let Features = "amx-fp16,amx-transpose", Attributes = [NoThrow] in {
- def ttdpfp16ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
-}
-
-let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in {
- def ttcmmimfp16ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
- def ttcmmrlfp16ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
- def tconjtcmmimfp16ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
- def tconjtfp16 : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char)">;
-}
-
let Features = "amx-avx512,avx10.2", Attributes = [NoThrow] in {
def tcvtrowd2ps : X86Builtin<"_Vector<16, float>(_Constant unsigned char, unsigned int)">;
def tcvtrowps2bf16h : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
@@ -406,10 +321,6 @@ let Features = "amx-tf32", Attributes = [NoThrow] in {
def tmmultf32ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
}
-let Features = "amx-tf32,amx-transpose", Attributes = [NoThrow] in {
- def ttmmultf32ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
-}
-
let Features = "prefetchi", Attributes = [NoThrow, Const] in {
def prefetchi : X86Builtin<"void(void const *, unsigned int)">;
}
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 8784c9d7d206d..1d11db1209e47 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6695,8 +6695,6 @@ def mamx_tf32 : Flag<["-"], "mamx-tf32">, Group<m_x86_Features_Group>;
def mno_amx_tf32 : Flag<["-"], "mno-amx-tf32">, Group<m_x86_Features_Group>;
def mamx_tile : Flag<["-"], "mamx-tile">, Group<m_x86_Features_Group>;
def mno_amx_tile : Flag<["-"], "mno-amx-tile">, Group<m_x86_Features_Group>;
-def mamx_transpose : Flag<["-"], "mamx-transpose">, Group<m_x86_Features_Group>;
-def mno_amx_transpose : Flag<["-"], "mno-amx-transpose">, Group<m_x86_Features_Group>;
def mamx_movrs: Flag<["-"], "mamx-movrs">, Group<m_x86_Features_Group>;
def mno_amx_movrs: Flag<["-"], "mno-amx-movrs">, Group<m_x86_Features_Group>;
def mcmpccxadd : Flag<["-"], "mcmpccxadd">, Group<m_x86_Features_Group>;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index e71f10c4c16fc..7a90c89dd7dc0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -396,8 +396,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasAMXFP8 = true;
} else if (Feature == "+amx-movrs") {
HasAMXMOVRS = true;
- } else if (Feature == "+amx-transpose") {
- HasAMXTRANSPOSE = true;
} else if (Feature == "+amx-avx512") {
HasAMXAVX512 = true;
} else if (Feature == "+amx-tf32") {
@@ -925,8 +923,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__AMX_FP8__");
if (HasAMXMOVRS)
Builder.defineMacro("__AMX_MOVRS__");
- if (HasAMXTRANSPOSE)
- Builder.defineMacro("__AMX_TRANSPOSE__");
if (HasAMXAVX512)
Builder.defineMacro("__AMX_AVX512__");
if (HasAMXTF32)
@@ -1068,7 +1064,6 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("amx-movrs", true)
.Case("amx-tf32", true)
.Case("amx-tile", true)
- .Case("amx-transpose", true)
.Case("avx", true)
.Case("avx10.1", true)
.Case("avx10.2", true)
@@ -1189,7 +1184,6 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("amx-movrs", HasAMXMOVRS)
.Case("amx-tf32", HasAMXTF32)
.Case("amx-tile", HasAMXTILE)
- .Case("amx-transpose", HasAMXTRANSPOSE)
.Case("avx", SSELevel >= AVX)
.Case("avx10.1", HasAVX10_1)
.Case("avx10.2", HasAVX10_2)
diff --git a/clang/lib/CodeGen/TargetBuiltins/X86.cpp b/clang/lib/CodeGen/TargetBuiltins/X86.cpp
index b924407b6ddd7..2381b2e7cf2cf 100644
--- a/clang/lib/CodeGen/TargetBuiltins/X86.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/X86.cpp
@@ -2931,74 +2931,6 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
// instruction, but it will create a memset that won't be optimized away.
return Builder.CreateMemSet(Ops[0], Ops[1], Ops[2], Align(1), true);
}
- // Corresponding to intrisics which will return 2 tiles (tile0_tile1).
- case X86::BI__builtin_ia32_t2rpntlvwz0_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz0rs_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz0t1_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz0rst1_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz1_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz1rs_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz1t1_internal:
- case X86::BI__builtin_ia32_t2rpntlvwz1rst1_internal: {
- Intrinsic::ID IID;
- switch (BuiltinID) {
- default:
- llvm_unreachable("Unsupported intrinsic!");
- case X86::BI__builtin_ia32_t2rpntlvwz0_internal:
- IID = Intrinsic::x86_t2rpntlvwz0_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz0rs_internal:
- IID = Intrinsic::x86_t2rpntlvwz0rs_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz0t1_internal:
- IID = Intrinsic::x86_t2rpntlvwz0t1_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz0rst1_internal:
- IID = Intrinsic::x86_t2rpntlvwz0rst1_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz1_internal:
- IID = Intrinsic::x86_t2rpntlvwz1_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz1rs_internal:
- IID = Intrinsic::x86_t2rpntlvwz1rs_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz1t1_internal:
- IID = Intrinsic::x86_t2rpntlvwz1t1_internal;
- break;
- case X86::BI__builtin_ia32_t2rpntlvwz1rst1_internal:
- IID = Intrinsic::x86_t2rpntlvwz1rst1_internal;
- break;
- }
-
- // Ops = (Row0, Col0, Col1, DstPtr0, DstPtr1, SrcPtr, Stride)
- Value *Call = Builder.CreateCall(CGM.getIntrinsic(IID),
- {Ops[0], Ops[1], Ops[2], Ops[5], Ops[6]});
-
- auto *PtrTy = E->getArg(3)->getType()->getAs<PointerType>();
- assert(PtrTy && "arg3 must be of pointer type");
- QualType PtreeTy = PtrTy->getPointeeType();
- llvm::Type *TyPtee = ConvertType(PtreeTy);
-
- // Bitcast amx type (x86_amx) to vector type (256 x i32)
- // Then store tile0 into DstPtr0
- Value *T0 = Builder.CreateExtractValue(Call, 0);
- Value *VecT0 = Builder.CreateIntrinsic(Intrinsic::x86_cast_tile_to_vector,
- {TyPtee}, {T0});
- Builder.CreateDefaultAlignedStore(VecT0, Ops[3]);
-
- // Then store tile1 into DstPtr1
- Value *T1 = Builder.CreateExtractValue(Call, 1);
- Value *VecT1 = Builder.CreateIntrinsic(Intrinsic::x86_cast_tile_to_vector,
- {TyPtee}, {T1});
- Value *Store = Builder.CreateDefaultAlignedStore(VecT1, Ops[4]);
-
- // Note: Here we escape directly use x86_tilestored64_internal to store
- // the results due to it can't make sure the Mem written scope. This may
- // cause shapes reloads after first amx intrinsic, which current amx reg-
- // ister allocation has no ability to handle it.
-
- return Store;
- }
case X86::BI__ud2:
// llvm.trap makes a ud2a instruction on x86.
return EmitTrapCall(Intrinsic::trap);
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 18589125697b0..33fff7645df65 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -162,18 +162,12 @@ set(x86_files
adxintrin.h
ammintrin.h
amxavx512intrin.h
- amxbf16transposeintrin.h
amxcomplexintrin.h
- amxcomplextransposeintrin.h
amxfp16intrin.h
- amxfp16transposeintrin.h
amxfp8intrin.h
amxintrin.h
amxmovrsintrin.h
- amxmovrstransposeintrin.h
amxtf32intrin.h
- amxtf32transposeintrin.h
- amxtransposeintrin.h
avx10_2_512bf16intrin.h
avx10_2_512convertintrin.h
avx10_2_512minmaxintrin.h
diff --git a/clang/lib/Headers/amxbf16transposeintrin.h b/clang/lib/Headers/amxbf16transposeintrin.h
deleted file mode 100644
index 86f09f2ad8db2..0000000000000
--- a/clang/lib/Headers/amxbf16transposeintrin.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*===----- amxbf16transposeintrin.h - AMX-BF16 and AMX-TRANSPOSE ------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===------------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error \
- "Never use <amxbf16transposeintrin.h> directly; use <immintrin.h> instead."
-#endif /* __IMMINTRIN_H */
-
-#ifndef __AMX_BF16TRANSPOSEINTRIN_H
-#define __AMX_BF16TRANSPOSEINTRIN_H
-#ifdef __x86_64__
-
-/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS \
- __attribute__((__always_inline__, __nodebug__, \
- __target__("amx-bf16,amx-transpose")))
-
-/// Compute transpose and dot-product of BF16 (16-bit) floating-point pairs in
-/// tiles \a a and \a b, accumulating the intermediate single-precision
-/// (32-bit) floating-point elements with elements in \a dst, and store the
-/// 32-bit result back to tile \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// void _tile_tdpbf16ps (__tile dst, __tile a, __tile b)
-/// \endcode
-///
-/// \code{.operation}
-/// FOR m := 0 TO dst.rows - 1
-/// tmp := dst.row[m]
-/// FOR k := 0 TO (a.colsb / 4) - 1
-/// FOR n := 0 TO (dst.colsb / 4) - 1
-/// tmp.bf32[n] += FP32(a.row[m].bf16[2*k+0]) *
-/// FP32(b.row[k].bf16[2*n+0])
-/// tmp.bf32[n] += FP32(a.row[m].bf16[2*k+1]) *
-/// FP32(b.row[k].bf16[2*n+1])
-/// ENDFOR
-/// ENDFOR
-/// write_row_and_zero(dst, m, tmp, dst.colsb)
-/// ENDFOR
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-///
-/// This intrinsic corresponds to the \c TTDPBF16PS instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-#define _tile_tdpbf16ps(dst, a, b) __builtin_ia32_ttdpbf16ps((dst), (a), (b))
-
-/// This is internal intrinsic. C/C++ user should avoid calling it directly.
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS
-_tile_tdpbf16ps_internal(unsigned short m, unsigned short n, unsigned short k,
- _tile1024i dst, _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_ttdpbf16ps_internal(m, n, k, dst, src1, src2);
-}
-
-/// Compute transpose and dot-product of BF16 (16-bit) floating-point pairs in
-/// tiles src0 and src1, accumulating the intermediate single-precision
-/// (32-bit) floating-point elements with elements in "dst", and store the
-/// 32-bit result back to tile "dst".
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TTDPBF16PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS
-static __inline__ void __tile_tdpbf16ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_tdpbf16ps_internal(src0.row, src1.col, src0.col, dst->tile,
- src0.tile, src1.tile);
-}
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif /* __x86_64__ */
-#endif /* __AMX_BF16TRANSPOSEINTRIN_H */
diff --git a/clang/lib/Headers/amxcomplextransposeintrin.h b/clang/lib/Headers/amxcomplextransposeintrin.h
deleted file mode 100644
index 11abaf98e9371..0000000000000
--- a/clang/lib/Headers/amxcomplextransposeintrin.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*===----- amxcomplextransposeintrin.h - AMX-COMPLEX and AMX-TRANSPOSE ------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===------------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error \
- "Never use <amxcomplextransposeintrin.h> directly; include <immintrin.h> instead."
-#endif // __IMMINTRIN_H
-
-#ifndef __AMX_COMPLEXTRANSPOSEINTRIN_H
-#define __AMX_COMPLEXTRANSPOSEINTRIN_H
-#ifdef __x86_64__
-
-#define __DEFAULT_FN_ATTRS \
- __attribute__((__always_inline__, __nodebug__, \
- __target__("amx-complex,amx-transpose")))
-
-/// Perform matrix multiplication of two tiles containing complex elements and
-/// accumulate the results into a packed single precision tile. Each dword
-/// element in input tiles \a a and \a b is interpreted as a complex number
-/// with FP16 real part and FP16 imaginary part.
-/// Calculates the imaginary part of the result. For each possible combination
-/// of (transposed column of \a a, column of \a b), it performs a set of
-/// multiplication and accumulations on all corresponding complex numbers
-/// (one from \a a and one from \a b). The imaginary part of the \a a element
-/// is multiplied with the real part of the corresponding \a b element, and
-/// the real part of the \a a element is multiplied with the imaginary part
-/// of the corresponding \a b elements. The two accumulated results are
-/// added, and then accumulated into the corresponding row and column of
-/// \a dst.
-///
-/// \headerfile <x86intrin.h>
-///
-/// \code
-/// void _tile_tcmmimfp16ps(__tile dst, __tile a, __tile b);
-/// \endcode
-///
-/// \code{.operation}
-/// FOR m := 0 TO dst.rows - 1
-/// tmp := dst.row[m]
-/// FOR k := 0 TO a.rows - 1
-/// FOR n := 0 TO (dst.colsb / 4) - 1
-/// tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+1])
-/// tmp.fp32[n] += FP32(a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+0])
-/// ENDFOR
-/// ENDFOR
-/// write_row_and_zero(dst, m, tmp, dst.colsb)
-/// ENDFOR
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-///
-/// This intrinsic corresponds to the \c TTCMMIMFP16PS instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-#define _tile_tcmmimfp16ps(dst, a, b) \
- __builtin_ia32_ttcmmimfp16ps((dst), (a), (b))
-
-/// Perform matrix multiplication of two tiles containing complex elements and
-/// accumulate the results into a packed single precision tile. Each dword
-/// element in input tiles \a a and \a b is interpreted as a complex number
-/// with FP16 real part and FP16 imaginary part.
-/// Calculates the real part of the result. For each possible combination
-/// of (rtransposed colum of \a a, column of \a b), it performs a set of
-/// multiplication and accumulations on all corresponding complex numbers
-/// (one from \a a and one from \a b). The real part of the \a a element is
-/// multiplied with the real part of the corresponding \a b element, and the
-/// negated imaginary part of the \a a element is multiplied with the
-/// imaginary part of the corresponding \a b elements. The two accumulated
-/// results are added, and then accumulated into the corresponding row and
-/// column of \a dst.
-///
-/// \headerfile <x86intrin.h>
-///
-/// \code
-/// void _tile_tcmmrlfp16ps(__tile dst, __tile a, __tile b);
-/// \endcode
-///
-/// \code{.operation}
-/// FOR m := 0 TO dst.rows - 1
-/// tmp := dst.row[m]
-/// FOR k := 0 TO a.rows - 1
-/// FOR n := 0 TO (dst.colsb / 4) - 1
-/// tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+0])
-/// tmp.fp32[n] += FP32(-a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+1])
-/// ENDFOR
-/// ENDFOR
-/// write_row_and_zero(dst, m, tmp, dst.colsb)
-/// ENDFOR
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-///
-/// This intrinsic corresponds to the \c TTCMMIMFP16PS instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-#define _tile_tcmmrlfp16ps(dst, a, b) \
- __builtin_ia32_ttcmmrlfp16ps((dst), (a), (b))
-
-/// Perform matrix conjugate transpose and multiplication of two tiles
-/// containing complex elements and accumulate the results into a packed
-/// single precision tile. Each dword element in input tiles \a a and \a b
-/// is interpreted as a complex number with FP16 real part and FP16 imaginary
-/// part.
-/// Calculates the imaginary part of the result. For each possible combination
-/// of (transposed column of \a a, column of \a b), it performs a set of
-/// multiplication and accumulations on all corresponding complex numbers
-/// (one from \a a and one from \a b). The negated imaginary part of the \a a
-/// element is multiplied with the real part of the corresponding \a b
-/// element, and the real part of the \a a element is multiplied with the
-/// imaginary part of the corresponding \a b elements. The two accumulated
-/// results are added, and then accumulated into the corresponding row and
-/// column of \a dst.
-///
-/// \headerfile <x86intrin.h>
-///
-/// \code
-/// void _tile_conjtcmmimfp16ps(__tile dst, __tile a, __tile b);
-/// \endcode
-///
-/// \code{.operation}
-/// FOR m := 0 TO dst.rows - 1
-/// tmp := dst.row[m]
-/// FOR k := 0 TO a.rows - 1
-/// FOR n := 0 TO (dst.colsb / 4) - 1
-/// tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+1])
-/// tmp.fp32[n] += FP32(-a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+0])
-/// ENDFOR
-/// ENDFOR
-/// write_row_and_zero(dst, m, tmp, dst.colsb)
-/// ENDFOR
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-///
-/// This intrinsic corresponds to the \c TCONJTCMMIMFP16PS instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-#define _tile_conjtcmmimfp16ps(dst, a, b) \
- __builtin_ia32_tconjtcmmimfp16ps((dst), (a), (b))
-
-/// Perform conjugate transpose of an FP16-pair of complex elements from \a a
-/// and writes the result to \a dst.
-///
-/// \headerfile <x86intrin.h>
-///
-/// \code
-/// void _tile_conjtfp16(__tile dst, __tile a);
-/// \endcode
-///
-/// \code{.operation}
-/// FOR i := 0 TO dst.rows - 1
-/// FOR j := 0 TO (dst.colsb / 4) - 1
-/// tmp.fp16[2*j+0] := a.row[j].fp16[2*i+0]
-/// tmp.fp16[2*j+1] := -a.row[j].fp16[2*i+1]
-/// ENDFOR
-/// write_row_and_zero(dst, i, tmp, dst.colsb)
-/// ENDFOR
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-///
-/// This intrinsic corresponds to the \c TCONJTFP16 instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The source tile. Max size is 1024 Bytes.
-#define _tile_conjtfp16(dst, a) __builtin_ia32_tconjtfp16((dst), (a))
-
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS _tile_tcmmimfp16ps_internal(
- unsigned short m, unsigned short n, unsigned short k, _tile1024i dst,
- _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_ttcmmimfp16ps_internal(m, n, k, dst, src1, src2);
-}
-
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS _tile_tcmmrlfp16ps_internal(
- unsigned short m, unsigned short n, unsigned short k, _tile1024i dst,
- _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_ttcmmrlfp16ps_internal(m, n, k, dst, src1, src2);
-}
-
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS _tile_conjtcmmimfp16ps_internal(
- unsigned short m, unsigned short n, unsigned short k, _tile1024i dst,
- _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_tconjtcmmimfp16ps_internal(m, n, k, dst, src1, src2);
-}
-
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS
-_tile_conjtfp16_internal(unsigned short m, unsigned short n, _tile1024i src) {
- return __builtin_ia32_tconjtfp16_internal(m, n, src);
-}
-
-/// Perform matrix multiplication of two tiles containing complex elements and
-/// accumulate the results into a packed single precision tile. Each dword
-/// element in input tiles src0 and src1 is interpreted as a complex number
-/// with FP16 real part and FP16 imaginary part.
-/// This function calculates the imaginary part of the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TTCMMIMFP16PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS
-static void __tile_tcmmimfp16ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_tcmmimfp16ps_internal(src0.row, src1.col, src0.col,
- dst->tile, src0.tile, src1.tile);
-}
-
-/// Perform matrix multiplication of two tiles containing complex elements and
-/// accumulate the results into a packed single precision tile. Each dword
-/// element in input tiles src0 and src1 is interpreted as a complex number
-/// with FP16 real part and FP16 imaginary part.
-/// This function calculates the real part of the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TTCMMRLFP16PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS
-static void __tile_tcmmrlfp16ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_tcmmrlfp16ps_internal(src0.row, src1.col, src0.col,
- dst->tile, src0.tile, src1.tile);
-}
-
-/// Perform matrix conjugate transpose and multiplication of two tiles
-/// containing complex elements and accumulate the results into a packed
-/// single precision tile. Each dword element in input tiles src0 and src1
-/// is interpreted as a complex number with FP16 real part and FP16 imaginary
-/// part.
-/// This function calculates the imaginary part of the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TCONJTCMMIMFP16PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS
-static void __tile_conjtcmmimfp16ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_conjtcmmimfp16ps_internal(src0.row, src1.col, src0.col,
- dst->tile, src0.tile, src1.tile);
-}
-
-/// Perform conjugate transpose of an FP16-pair of complex elements from src and
-/// writes the result to dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TCONJTFP16 </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src
-/// The source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS
-static void __tile_conjtfp16(__tile1024i *dst, __tile1024i src) {
- dst->tile = _tile_conjtfp16_internal(src.row, src.col, src.tile);
-}
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif // __x86_64__
-#endif // __AMX_COMPLEXTRANSPOSEINTRIN_H
diff --git a/clang/lib/Headers/amxfp16transposeintrin.h b/clang/lib/Headers/amxfp16transposeintrin.h
deleted file mode 100644
index 191f8c6097a2c..0000000000000
--- a/clang/lib/Headers/amxfp16transposeintrin.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*===----- amxfp16transposeintrin.h - AMX-FP16 and AMX-TRANSPOSE ------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===------------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error \
- "Never use <amxfp16transposeintrin.h> directly; use <immintrin.h> instead."
-#endif /* __IMMINTRIN_H */
-
-#ifndef __AMX_FP16TRANSPOSEINTRIN_H
-#define __AMX_FP16TRANSPOSEINTRIN_H
-#ifdef __x86_64__
-
-/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS \
- __attribute__((__always_inline__, __nodebug__, \
- __target__("amx-fp16,amx-transpose")))
-
-/// Compute transpose and dot-product of FP16 (16-bit) floating-point pairs in
-/// tiles \a a and \a b, accumulating the intermediate single-precision
-/// (32-bit) floating-point elements with elements in \a dst, and store the
-/// 32-bit result back to tile \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// void _tile_tdpfp16ps (__tile dst, __tile a, __tile b)
-/// \endcode
-///
-/// \code{.operation}
-/// FOR m := 0 TO dst.rows - 1
-/// tmp := dst.row[m]
-/// FOR k := 0 TO (a.colsb / 4) - 1
-/// FOR n := 0 TO (dst.colsb / 4) - 1
-/// tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) *
-/// FP32(b.row[k].fp16[2*n+0])
-/// tmp.fp32[n] += FP32(a.row[m].fp16[2*k+1]) *
-/// FP32(b.row[k].fp16[2*n+1])
-/// ENDFOR
-/// ENDFOR
-/// write_row_and_zero(dst, m, tmp, dst.colsb)
-/// ENDFOR
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-///
-/// This intrinsic corresponds to the \c TTDPFP16PS instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-#define _tile_tdpfp16ps(dst, a, b) __builtin_ia32_ttdpfp16ps((dst), (a), (b))
-
-/// This is internal intrinsic. C/C++ user should avoid calling it directly.
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS
-_tile_tdpfp16ps_internal(unsigned short m, unsigned short n, unsigned short k,
- _tile1024i dst, _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_ttdpfp16ps_internal(m, n, k, dst, src1, src2);
-}
-
-/// Compute transpose and dot-product of FP16 (16-bit) floating-point pairs in
-/// tiles src0 and src1, accumulating the intermediate single-precision
-/// (32-bit) floating-point elements with elements in "dst", and store the
-/// 32-bit result back to tile "dst".
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TTDPFP16PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS
-static __inline__ void __tile_tdpfp16ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_tdpfp16ps_internal(src0.row, src1.col, src0.col, dst->tile,
- src0.tile, src1.tile);
-}
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif /* __x86_64__ */
-#endif /* __AMX_FP16TRANSPOSEINTRIN_H */
diff --git a/clang/lib/Headers/amxintrin.h b/clang/lib/Headers/amxintrin.h
index a7da10d9951e7..208aa3580625f 100644
--- a/clang/lib/Headers/amxintrin.h
+++ b/clang/lib/Headers/amxintrin.h
@@ -230,8 +230,6 @@ static __inline__ void __DEFAULT_FN_ATTRS_TILE _tile_release(void) {
/// bytes. Since there is no 2D type in llvm IR, we use vector type to
/// represent 2D tile and the fixed size is maximum amx tile register size.
typedef int _tile1024i __attribute__((__vector_size__(1024), __aligned__(64)));
-typedef int _tile1024i_1024a
- __attribute__((__vector_size__(1024), __aligned__(1024)));
/// This is internal intrinsic. C/C++ user should avoid calling it directly.
static __inline__ _tile1024i __DEFAULT_FN_ATTRS_TILE
diff --git a/clang/lib/Headers/amxmovrstransposeintrin.h b/clang/lib/Headers/amxmovrstransposeintrin.h
deleted file mode 100644
index 5f48cba949f34..0000000000000
--- a/clang/lib/Headers/amxmovrstransposeintrin.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* ===--- amxmovrstransposeintrin.h - AMX_MOVRS_TRANSPOSE intrinsics --------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- * ===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error \
- "Never use <amxmovrstransposeintrin.h> directly; use <immintrin.h> instead."
-#endif /* __IMMINTRIN_H */
-
-#ifndef __AMX_MOVRS_TRANSPOSEINTRIN_H
-#define __AMX_MOVRS_TRANSPOSEINTRIN_H
-#ifdef __x86_64__
-
-#define __DEFAULT_FN_ATTRS \
- __attribute__((__always_inline__, __nodebug__, \
- __target__("amx-transpose,amx-movrs")))
-
-#define _tile_2rpntlvwz0rs(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz0rs(tdst, base, stride)
-#define _tile_2rpntlvwz0rst1(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz0rst1(tdst, base, stride)
-#define _tile_2rpntlvwz1rs(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz1rs(tdst, base, stride)
-#define _tile_2rpntlvwz1rst1(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz1rst1(tdst, base, stride)
-
-static __inline__ void __DEFAULT_FN_ATTRS _tile_2rpntlvwz0rs_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- // Use __tile1024i_1024a* to escape the alignment check in
- // clang/test/Headers/x86-intrinsics-headers-clean.cpp
- __builtin_ia32_t2rpntlvwz0rs_internal(
- row, col0, col1, (_tile1024i_1024a *)dst0, (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-static __inline__ void __DEFAULT_FN_ATTRS _tile_2rpntlvwz0rst1_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- __builtin_ia32_t2rpntlvwz0rst1_internal(
- row, col0, col1, (_tile1024i_1024a *)dst0, (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-static __inline__ void __DEFAULT_FN_ATTRS _tile_2rpntlvwz1rs_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- __builtin_ia32_t2rpntlvwz1rs_internal(
- row, col0, col1, (_tile1024i_1024a *)dst0, (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-static __inline__ void __DEFAULT_FN_ATTRS _tile_2rpntlvwz1rst1_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- __builtin_ia32_t2rpntlvwz1rst1_internal(
- row, col0, col1, (_tile1024i_1024a *)dst0, (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written.
-/// Provides a hint to the implementation that the data will likely become
-/// read shared in the near future and the data caching can be optimized.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ0RS </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS
-static void __tile_2rpntlvwz0rs(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz0rs_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ0T1RS </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS
-static void __tile_2rpntlvwz0rst1(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz0rst1_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written. The last row will be not be read from memory but instead
-/// filled with zeros.
-/// Provides a hint to the implementation that the data will likely become
-/// read shared in the near future and the data caching can be optimized.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ1 </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS
-static void __tile_2rpntlvwz1rs(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz1rs_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written. The last row will be not be read from memory but instead
-/// filled with zeros.
-/// Provides a hint to the implementation that the data will likely become
-/// read shared in the near future and the data caching can be optimized.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ1T1RS </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS
-static void __tile_2rpntlvwz1rst1(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz1rst1_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-#undef __DEFAULT_FN_ATTRS
-#endif /* __x86_64__ */
-#endif /* __AMX_MOVRS_TRANSPOSEINTRIN_H */
diff --git a/clang/lib/Headers/amxtf32transposeintrin.h b/clang/lib/Headers/amxtf32transposeintrin.h
deleted file mode 100644
index e1b90c1adfb22..0000000000000
--- a/clang/lib/Headers/amxtf32transposeintrin.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*===--------- amxtf32transposeintrin.h - AMX-TF32 and AMX-TRANSPOSE --------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===------------------------------------------------------------------------===
- */
-#ifndef __IMMINTRIN_H
-#error \
- "Never use <amxtf32transposeintrin.h> directly; include <immintrin.h> instead."
-#endif // __IMMINTRIN_H
-
-#ifndef __AMX_TF32TRANSPOSEINTRIN_H
-#define __AMX_TF32TRANSPOSEINTRIN_H
-#ifdef __x86_64__
-
-#define __DEFAULT_FN_ATTRS_TF32_TRANSPOSE \
- __attribute__((__always_inline__, __nodebug__, \
- __target__("amx-tf32,amx-transpose")))
-
-/// \code
-/// void _tile_tmmultf32ps(constexpr int srcdst, constexpr int a, \
-/// constexpr int b);
-/// \endcode
-///
-/// This intrinsic corresponds to the <c> TTMMULTF32PS </c> instruction.
-///
-/// \param srcdst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-///
-/// \code{.operation}
-/// DEFINE zero_lower_mantissa_bits_fp32(x[31:0]) {
-/// dword[12:0] := 0
-/// dword[31:13] := x[31:13]
-/// return dword
-/// }
-///
-/// DEFINE silence_snan_fp32(x[31:0]) {
-/// IF (x.exponent == 255 and x.fraction != 0 and x.fraction[22] == 0)
-/// x.fraction[22] := 1
-/// return x
-/// }
-///
-/// elements_dest:= srcdst.colsb/4
-///
-/// FOR m := 0 TO (srcdst.rows-1)
-/// tmp[511:0] := 0
-/// FOR k := 0 TO (a.rows-1)
-/// FOR n := 0 TO (elements_dest-1)
-/// a1e := silence_snan_fp32(a.row[k].fp32[m])
-/// a2e := silence_snan_fp32(b.row[k].fp32[n])
-/// s1e := zero_lower_mantissa_bits_fp32(a1e)
-/// s2e := zero_lower_mantissa_bits_fp32(a2e)
-/// tmp.fp32[n] += s1e * s2e
-/// ENDFOR
-/// ENDFOR
-///
-/// FOR n := 0 TO (elements_dest-1)
-/// tmp.fp32[n] += srcdst.row[m].fp32[n]
-/// ENDFOR
-/// write_row_and_zero(srcdst, m, tmp, srcdst.colsb)
-///
-/// ENDFOR
-///
-/// zero_upper_rows(srcdst, srcdst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-#define _tile_tmmultf32ps(srcdst, a, b) \
- __builtin_ia32_ttmmultf32ps((srcdst), (a), (b))
-
-// dst = m x n (srcdest), src1 = k x m, src2 = k x n
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS_TF32_TRANSPOSE
-_tile_tmmultf32ps_internal(unsigned short m, unsigned short n, unsigned short k,
- _tile1024i dst, _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_ttmmultf32ps_internal(m, n, k, dst, src1, src2);
-}
-
-/// Compute transpose and do Matrix Multiplication of src0 and src1, and then do
-/// Matrix Plus with dst. All the calculation is base on float32 but with the
-/// lower 13-bit set to 0.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TTMMULTF32PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS_TF32_TRANSPOSE
-static void __tile_tmmultf32ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_tmmultf32ps_internal(src0.row, src1.col, src0.col,
- dst->tile, src0.tile, src1.tile);
-}
-
-#endif // __x86_64__
-#endif // __AMX_TF32TRANSPOSEINTRIN_H
diff --git a/clang/lib/Headers/amxtransposeintrin.h b/clang/lib/Headers/amxtransposeintrin.h
deleted file mode 100644
index b3fa37d766c45..0000000000000
--- a/clang/lib/Headers/amxtransposeintrin.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/* ===--- amxtransposeintrin.h - AMX_TRANSPOSE intrinsics -*- C++ -*---------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- * ===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <amxtransposeintrin.h> directly; use <immintrin.h> instead."
-#endif /* __IMMINTRIN_H */
-
-#ifndef __AMX_TRANSPOSEINTRIN_H
-#define __AMX_TRANSPOSEINTRIN_H
-#ifdef __x86_64__
-
-#define __DEFAULT_FN_ATTRS_TRANSPOSE \
- __attribute__((__always_inline__, __nodebug__, __target__("amx-transpose")))
-
-#define _tile_2rpntlvwz0(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz0(tdst, base, stride)
-#define _tile_2rpntlvwz0t1(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz0t1(tdst, base, stride)
-#define _tile_2rpntlvwz1(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz1(tdst, base, stride)
-#define _tile_2rpntlvwz1t1(tdst, base, stride) \
- __builtin_ia32_t2rpntlvwz1t1(tdst, base, stride)
-
-/// Transpose 32-bit elements from \a src and write the result to \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// void _tile_transposed(__tile dst, __tile src);
-/// \endcode
-///
-/// This intrinsic corresponds to the <c> TTRANSPOSED </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src
-/// The source tile. Max size is 1024 Bytes.
-///
-/// \code{.operation}
-///
-/// FOR i := 0 TO (dst.rows-1)
-/// tmp[511:0] := 0
-/// FOR j := 0 TO (dst.colsb/4-1)
-/// tmp.dword[j] := src.row[j].dword[i]
-/// ENDFOR
-/// dst.row[i] := tmp
-/// ENDFOR
-///
-/// zero_upper_rows(dst, dst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-#define _tile_transposed(dst, src) __builtin_ia32_ttransposed(dst, src)
-
-static __inline__ void __DEFAULT_FN_ATTRS_TRANSPOSE _tile_2rpntlvwz0_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- // Use __tile1024i_1024a* to escape the alignment check in
- // clang/test/Headers/x86-intrinsics-headers-clean.cpp
- __builtin_ia32_t2rpntlvwz0_internal(row, col0, col1, (_tile1024i_1024a *)dst0,
- (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-static __inline__ void __DEFAULT_FN_ATTRS_TRANSPOSE _tile_2rpntlvwz0t1_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- __builtin_ia32_t2rpntlvwz0t1_internal(
- row, col0, col1, (_tile1024i_1024a *)dst0, (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-static __inline__ void __DEFAULT_FN_ATTRS_TRANSPOSE _tile_2rpntlvwz1_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- __builtin_ia32_t2rpntlvwz1_internal(row, col0, col1, (_tile1024i_1024a *)dst0,
- (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-static __inline__ void __DEFAULT_FN_ATTRS_TRANSPOSE _tile_2rpntlvwz1t1_internal(
- unsigned short row, unsigned short col0, unsigned short col1,
- _tile1024i *dst0, _tile1024i *dst1, const void *base,
- __SIZE_TYPE__ stride) {
- __builtin_ia32_t2rpntlvwz1t1_internal(
- row, col0, col1, (_tile1024i_1024a *)dst0, (_tile1024i_1024a *)dst1, base,
- (__SIZE_TYPE__)(stride));
-}
-
-// This is internal intrinsic. C/C++ user should avoid calling it directly.
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS_TRANSPOSE
-_tile_transposed_internal(unsigned short m, unsigned short n, _tile1024i src) {
- return __builtin_ia32_ttransposed_internal(m, n, src);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written.
-/// Provides a hint to the implementation that the data will likely not be
-/// reused in the near future and the data caching can be optimized.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ0 </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS_TRANSPOSE
-static void __tile_2rpntlvwz0(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz0_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ0T1 </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS_TRANSPOSE
-static void __tile_2rpntlvwz0t1(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz0t1_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written. The last row will be not be read from memory but instead
-/// filled with zeros.
-/// Provides a hint to the implementation that the data will likely not be
-/// reused in the near future and the data caching can be optimized.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ1 </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS_TRANSPOSE
-static void __tile_2rpntlvwz1(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz1_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Converts a pair of tiles from memory into VNNI format, and places the
-/// results in a pair of destinations specified by dst. The pair of tiles
-/// in memory is specified via a tsib; the second tile is after the first
-/// one, separated by the same stride that separates each row.
-/// The tile configuration for the destination tiles indicates the amount
-/// of data to read from memory. The instruction will load a number of rows
-/// that is equal to twice the number of rows in tmm1. The size of each row
-/// is equal to the average width of the destination tiles. If the second
-/// tile is configured with zero rows and columns, only the first tile will
-/// be written. The last row will be not be read from memory but instead
-/// filled with zeros.
-/// Provides a hint to the implementation that the data will likely not be
-/// reused in the near future and the data caching can be optimized.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> T2RPNTLVWZ1T1 </c> instruction.
-///
-/// \param dst0
-/// First tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param dst1
-/// Second tile of destination tile pair. Max size is 1024i*2 Bytes.
-/// \param base
-/// A pointer to base address.
-/// \param stride
-/// The stride between the rows' data to be loaded in memory.
-__DEFAULT_FN_ATTRS_TRANSPOSE
-static void __tile_2rpntlvwz1t1(__tile1024i *dst0, __tile1024i *dst1,
- const void *base, __SIZE_TYPE__ stride) {
- _tile_2rpntlvwz1t1_internal(dst0->row, dst0->col, dst1->col, &dst0->tile,
- &dst1->tile, base, stride);
-}
-
-/// Transpose 32-bit elements from src and write the result to dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TTRANSPOSED </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src
-/// The source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS_TRANSPOSE
-static void __tile_transposed(__tile1024i *dst, __tile1024i src) {
- dst->tile = _tile_transposed_internal(dst->row, dst->col, src.tile);
-}
-
-#endif /* __x86_64__ */
-#endif /* __AMX_TRANSPOSEINTRIN_H */
diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h
index 35f012cc70043..19064a4ff5cea 100644
--- a/clang/lib/Headers/immintrin.h
+++ b/clang/lib/Headers/immintrin.h
@@ -475,24 +475,12 @@ _storebe_i64(void * __P, long long __D) {
#include <amxfp8intrin.h>
-#include <amxtransposeintrin.h>
-
#include <amxmovrsintrin.h>
-#include <amxmovrstransposeintrin.h>
-
#include <amxavx512intrin.h>
#include <amxtf32intrin.h>
-#include <amxtf32transposeintrin.h>
-
-#include <amxbf16transposeintrin.h>
-
-#include <amxfp16transposeintrin.h>
-
-#include <amxcomplextransposeintrin.h>
-
#include <avx512vp2intersectintrin.h>
#include <avx512vlvp2intersectintrin.h>
diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp
index 850bcb17bece1..2f61bdd9a6540 100644
--- a/clang/lib/Sema/SemaX86.cpp
+++ b/clang/lib/Sema/SemaX86.cpp
@@ -489,14 +489,6 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_tileloaddrst164:
case X86::BI__builtin_ia32_tilestored64:
case X86::BI__builtin_ia32_tilezero:
- case X86::BI__builtin_ia32_t2rpntlvwz0:
- case X86::BI__builtin_ia32_t2rpntlvwz0t1:
- case X86::BI__builtin_ia32_t2rpntlvwz1:
- case X86::BI__builtin_ia32_t2rpntlvwz1t1:
- case X86::BI__builtin_ia32_t2rpntlvwz0rst1:
- case X86::BI__builtin_ia32_t2rpntlvwz1rs:
- case X86::BI__builtin_ia32_t2rpntlvwz1rst1:
- case X86::BI__builtin_ia32_t2rpntlvwz0rs:
case X86::BI__builtin_ia32_tcvtrowps2bf16h:
case X86::BI__builtin_ia32_tcvtrowps2bf16l:
case X86::BI__builtin_ia32_tcvtrowps2phh:
@@ -516,17 +508,8 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_tdpbhf8ps:
case X86::BI__builtin_ia32_tdphbf8ps:
case X86::BI__builtin_ia32_tdphf8ps:
- case X86::BI__builtin_ia32_ttdpbf16ps:
- case X86::BI__builtin_ia32_ttdpfp16ps:
- case X86::BI__builtin_ia32_ttcmmimfp16ps:
- case X86::BI__builtin_ia32_ttcmmrlfp16ps:
- case X86::BI__builtin_ia32_tconjtcmmimfp16ps:
case X86::BI__builtin_ia32_tmmultf32ps:
- case X86::BI__builtin_ia32_ttmmultf32ps:
return CheckBuiltinTileRangeAndDuplicate(TheCall, {0, 1, 2});
- case X86::BI__builtin_ia32_ttransposed:
- case X86::BI__builtin_ia32_tconjtfp16:
- return CheckBuiltinTileArgumentsRange(TheCall, {0, 1});
}
}
static bool isX86_32Builtin(unsigned BuiltinID) {
diff --git a/clang/test/CodeGen/X86/amx_movrs_tranpose.c b/clang/test/CodeGen/X86/amx_movrs_tranpose.c
deleted file mode 100755
index 192c153835e1e..0000000000000
--- a/clang/test/CodeGen/X86/amx_movrs_tranpose.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown \
-// RUN: -target-feature +amx-movrs -emit-llvm -o - -Wall -Werror -pedantic \
-// RUN: -target-feature +amx-transpose -Wno-gnu-statement-expression| FileCheck %s
-
-#include <immintrin.h>
-#include <stddef.h>
-
-char buf[2048];
-#define STRIDE 32
-
-// CHECK-LABEL: define dso_local void @test_tile_2rpntlvwz0rs_internal(
-// CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rs.internal(i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}, ptr %{{.*}}, i64 %{{.*}})
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 0
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-// CHECK: store <256 x i32> %{{.*}}, ptr %{{.*}}, align 1024
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 1
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-void test_tile_2rpntlvwz0rs_internal(int row, int col0, int col1, void *D0, void *D1, void *B) {
- _tile_2rpntlvwz0rs_internal(row, col0, col1, D0, D1, B, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_tile_2rpntlvwz0rst1_internal(
-// CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rst1.internal(i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}, ptr %{{.*}}, i64 %{{.*}})
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 0
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-// CHECK: store <256 x i32> %{{.*}}, ptr %{{.*}}, align 1024
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 1
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-void test_tile_2rpntlvwz0rst1_internal(int row, int col0, int col1, void *D0, void *D1, void *B) {
- _tile_2rpntlvwz0rst1_internal(row, col0, col1, D0, D1, B, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_tile_2rpntlvwz1rs_internal(
-// CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rs.internal(i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}, ptr %{{.*}}, i64 %{{.*}})
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 0
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-// CHECK: store <256 x i32> %{{.*}}, ptr %{{.*}}, align 1024
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 1
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-void test_tile_2rpntlvwz1rs_internal(int row, int col0, int col1, void *D0, void *D1, void *B) {
- _tile_2rpntlvwz1rs_internal(row, col0, col1, D0, D1, B, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_tile_2rpntlvwz1rst1_internal(
-// CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rst1.internal(i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}, ptr %{{.*}}, i64 %{{.*}})
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 0
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-// CHECK: store <256 x i32> %{{.*}}, ptr %{{.*}}, align 1024
-// CHECK: extractvalue { x86_amx, x86_amx } %{{.*}}, 1
-// CHECK: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %{{.*}})
-void test_tile_2rpntlvwz1rst1_internal(int row, int col0, int col1, void *D0, void *D1, void *B) {
- _tile_2rpntlvwz1rst1_internal(row, col0, col1, D0, D1, B, 1);
-}
diff --git a/clang/test/CodeGen/X86/amx_movrs_tranpose_api.c b/clang/test/CodeGen/X86/amx_movrs_tranpose_api.c
deleted file mode 100755
index b174cc5067bf3..0000000000000
--- a/clang/test/CodeGen/X86/amx_movrs_tranpose_api.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown \
-// RUN: -target-feature +amx-movrs -emit-llvm -o - -Wall -Werror -pedantic \
-// RUN: -target-feature +amx-transpose -Wno-gnu-statement-expression| FileCheck %s
-
-#include <immintrin.h>
-#include <stddef.h>
-
-char buf[2048];
-#define STRIDE 32
-
-void test_tile_2rpntlvwz0rs(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz0rs
- // CHECK: call void @llvm.x86.t2rpntlvwz0rs(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz0rs(1, A, B);
-}
-
-void test_tile_2rpntlvwz0rst1(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz0rst1
- // CHECK: call void @llvm.x86.t2rpntlvwz0rst1(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz0rst1(1, A, B);
-}
-
-void test_tile_2rpntlvwz1rs(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz1rs
- // CHECK: call void @llvm.x86.t2rpntlvwz1rs(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz1rs(1, A, B);
-}
-
-void test_tile_2rpntlvwz1rst1(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz1rst1
- // CHECK: call void @llvm.x86.t2rpntlvwz1rst1(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz1rst1(1, A, B);
-}
-
-void test__tile_2rpntlvwz0rs(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test__tile_2rpntlvwz0rs
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rs.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz0rs(&dst0, &dst1, buf, STRIDE);
-}
-
-void test__tile_2rpntlvwz0rst1(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test__tile_2rpntlvwz0rst1
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rst1.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz0rst1(&dst0, &dst1, buf, STRIDE);
-}
-
-void test__tile_2rpntlvwz1rs(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test__tile_2rpntlvwz1rs
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rs.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz1rs(&dst0, &dst1, buf, STRIDE);
-}
-
-void test__tile_2rpntlvwz1rst1(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test__tile_2rpntlvwz1rst1
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rst1.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz1rst1(&dst0, &dst1, buf, STRIDE);
-}
diff --git a/clang/test/CodeGen/X86/amx_movrs_transpose_errors.c b/clang/test/CodeGen/X86/amx_movrs_transpose_errors.c
deleted file mode 100755
index 840b52bbb29bb..0000000000000
--- a/clang/test/CodeGen/X86/amx_movrs_transpose_errors.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown \
-// RUN: -target-feature +amx-int8 -target-feature +amx-transpose -target-feature +amx-movrs \
-// RUN: -verify
-
-#include <immintrin.h>
-#include <stddef.h>
-
-void test_tile_2rpntlvwz0rs(const void *A, size_t B) {
- _tile_2rpntlvwz0rs(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_2rpntlvwz0rst1(const void *A, size_t B) {
- _tile_2rpntlvwz0rst1(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_2rpntlvwz1rs(const void *A, size_t B) {
- _tile_2rpntlvwz1rs(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_2rpntlvwz1rst1(const void *A, size_t B) {
- _tile_2rpntlvwz1rst1(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
diff --git a/clang/test/CodeGen/X86/amx_tf32.c b/clang/test/CodeGen/X86/amx_tf32.c
index 661a9dfbc673b..54ad6bb714933 100644
--- a/clang/test/CodeGen/X86/amx_tf32.c
+++ b/clang/test/CodeGen/X86/amx_tf32.c
@@ -10,8 +10,3 @@ void test_tile_mmultf32ps(void) {
_tile_mmultf32ps(1, 2, 3);
}
-void test_tile_tmmultf32ps(void) {
- // CHECK-LABEL: @test_tile_tmmultf32ps(
- // CHECK: call void @llvm.x86.ttmmultf32ps(i8 1, i8 2, i8 3)
- _tile_tmmultf32ps(1, 2, 3);
-}
diff --git a/clang/test/CodeGen/X86/amx_tf32_api.c b/clang/test/CodeGen/X86/amx_tf32_api.c
index 2ac8489e3e0ba..8f574b7bc71dc 100644
--- a/clang/test/CodeGen/X86/amx_tf32_api.c
+++ b/clang/test/CodeGen/X86/amx_tf32_api.c
@@ -18,10 +18,3 @@ void test_tile_mmultf32ps(__tile1024i a, __tile1024i b, __tile1024i c) {
__tile_mmultf32ps(&c, a, b);
}
-void test_tile_tmmultf32ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_tmmultf32ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.ttmmultf32ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_tmmultf32ps(&c, a, b);
-}
diff --git a/clang/test/CodeGen/X86/amx_tf32_errors.c b/clang/test/CodeGen/X86/amx_tf32_errors.c
index 4502130692115..f0fdd060363cf 100644
--- a/clang/test/CodeGen/X86/amx_tf32_errors.c
+++ b/clang/test/CodeGen/X86/amx_tf32_errors.c
@@ -13,11 +13,3 @@ void test_tile_mmultf32ps() {
_tile_mmultf32ps(1, 3, 3); // expected-error {{tile arguments must refer to different tiles}}
}
-void test_tile_tmmultf32ps() {
- _tile_tmmultf32ps(16, 2, 3); // expected-error {{argument value 16 is outside the valid range [0, 7]}}
- _tile_tmmultf32ps(1, 26, 3); // expected-error {{argument value 26 is outside the valid range [0, 7]}}
- _tile_tmmultf32ps(1, 2, 36); // expected-error {{argument value 36 is outside the valid range [0, 7]}}
- _tile_tmmultf32ps(1, 1, 3); // expected-error {{tile arguments must refer to different tiles}}
- _tile_tmmultf32ps(1, 2, 1); // expected-error {{tile arguments must refer to different tiles}}
- _tile_tmmultf32ps(1, 2, 2); // expected-error {{tile arguments must refer to different tiles}}
-}
diff --git a/clang/test/CodeGen/X86/amx_transpose.c b/clang/test/CodeGen/X86/amx_transpose.c
deleted file mode 100644
index 7e88fd80592d6..0000000000000
--- a/clang/test/CodeGen/X86/amx_transpose.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-transpose \
-// RUN: -target-feature +amx-bf16 -target-feature +amx-fp16 -target-feature +amx-complex \
-// RUN: -target-feature +avx512f -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression| FileCheck %s
-
-#include <immintrin.h>
-#include <stddef.h>
-
-void test_tile_2rpntlvwz0(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz0
- // CHECK: call void @llvm.x86.t2rpntlvwz0(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz0(1, A, B);
-}
-
-void test_tile_2rpntlvwz0t1(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz0t1
- // CHECK: call void @llvm.x86.t2rpntlvwz0t1(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz0t1(1, A, B);
-}
-
-void test_tile_2rpntlvwz1(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz1
- // CHECK: call void @llvm.x86.t2rpntlvwz1(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz1(1, A, B);
-}
-
-void test_tile_2rpntlvwz1t1(const void *A, size_t B) {
- // CHECK-LABEL: @test_tile_2rpntlvwz1t1
- // CHECK: call void @llvm.x86.t2rpntlvwz1t1(i8 1, ptr %{{.*}}, i64 %{{.*}})
- _tile_2rpntlvwz1t1(1, A, B);
-}
-
-void test_tile_transposed(void)
-{
- // CHECK-LABEL: @test_tile_transposed
- // CHECK: call void @llvm.x86.ttransposed(i8 1, i8 2)
- _tile_transposed(1, 2);
-}
-
-void test_tile_tdpbf16ps(void)
-{
- // CHECK-LABEL: @test_tile_tdpbf16ps
- // CHECK: call void @llvm.x86.ttdpbf16ps(i8 1, i8 2, i8 3)
- _tile_tdpbf16ps(1, 2, 3);
-}
-
-void test_tile_tdpfp16ps(void)
-{
- // CHECK-LABEL: @test_tile_tdpfp16ps
- // CHECK: call void @llvm.x86.ttdpfp16ps(i8 4, i8 5, i8 6)
- _tile_tdpfp16ps(4, 5, 6);
-}
-
-void test_tile_tcmmimfp16ps(void) {
- // CHECK-LABEL: @test_tile_tcmmimfp16ps
- // CHECK: call void @llvm.x86.ttcmmimfp16ps(i8 1, i8 2, i8 3)
- _tile_tcmmimfp16ps(1, 2, 3);
-}
-
-void test_tile_tcmmrlfp16ps(void) {
- // CHECK-LABEL: @test_tile_tcmmrlfp16ps
- // CHECK: call void @llvm.x86.ttcmmrlfp16ps(i8 1, i8 2, i8 3)
- _tile_tcmmrlfp16ps(1, 2, 3);
-}
-
-void test_tile_conjtcmmimfp16ps(void) {
- // CHECK-LABEL: @test_tile_conjtcmmimfp16ps
- // CHECK: call void @llvm.x86.tconjtcmmimfp16ps(i8 1, i8 2, i8 3)
- _tile_conjtcmmimfp16ps(1, 2, 3);
-}
-
-void test_tile_conjtfp16(void) {
- // CHECK-LABEL: @test_tile_conjtfp16
- // CHECK: call void @llvm.x86.tconjtfp16(i8 1, i8 2)
- _tile_conjtfp16(1, 2);
-}
diff --git a/clang/test/CodeGen/X86/amx_transpose_api.c b/clang/test/CodeGen/X86/amx_transpose_api.c
deleted file mode 100644
index dc3ef5104252c..0000000000000
--- a/clang/test/CodeGen/X86/amx_transpose_api.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512f \
-// RUN: -target-feature +amx-transpose -target-feature +amx-bf16 -target-feature +amx-fp16 -target-feature +amx-complex \
-// RUN: -emit-llvm -o - -Werror -pedantic | FileCheck %s --check-prefixes=CHECK
-
-#include <immintrin.h>
-
-char buf[2048];
-#define STRIDE 32
-
-char buf2[2048];
-
-void test_tile_2rpntlvwz0(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test_tile_2rpntlvwz0
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz0(&dst0, &dst1, buf, STRIDE);
-}
-
-void test_tile_2rpntlvwz0t1(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test_tile_2rpntlvwz0t1
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0t1.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz0t1(&dst0, &dst1, buf, STRIDE);
-}
-
-void test_tile_2rpntlvwz1(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test_tile_2rpntlvwz1
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz1(&dst0, &dst1, buf, STRIDE);
-}
-
-void test_tile_2rpntlvwz1t1(__tile1024i dst0, __tile1024i dst1) {
- //CHECK-LABEL: @test_tile_2rpntlvwz1t1
- //CHECK: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1t1.internal
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 0
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- //CHECK-NEXT: {{%.*}} = extractvalue { x86_amx, x86_amx } {{%.*}}, 1
- //CHECK-NEXT: {{%.*}} = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- //CHECK-NEXT: store <256 x i32> {{%.*}}, ptr {{%.*}}
- __tile_2rpntlvwz1t1(&dst0, &dst1, buf, STRIDE);
-}
-
-void test_tile_transposed(__tile1024i dst, __tile1024i src) {
- //CHECK-LABEL: @test_tile_transposed
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.ttransposed.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_transposed(&dst, src);
-}
-
-void test_tile_tdpbf16ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_tdpbf16ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.ttdpbf16ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_tdpbf16ps(&c, a, b);
-}
-
-void test_tile_tdpfp16ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_tdpfp16ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.ttdpfp16ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_tdpfp16ps(&c, a, b);
-}
-
-void test_tile_tcmmimfp16ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_tcmmimfp16ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.ttcmmimfp16ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_tcmmimfp16ps(&c, a, b);
-}
-
-void test_tile_tcmmrlfp16ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_tcmmrlfp16ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.ttcmmrlfp16ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_tcmmrlfp16ps(&c, a, b);
-}
-
-void test_tile_conjtcmmimfp16ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_conjtcmmimfp16ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.tconjtcmmimfp16ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_conjtcmmimfp16ps(&c, a, b);
-}
-
-void test_tile_conjtfp16(__tile1024i dst, __tile1024i src) {
- //CHECK-LABEL: @test_tile_conjtfp16
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.tconjtfp16.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_conjtfp16(&dst, src);
-}
diff --git a/clang/test/CodeGen/X86/amx_transpose_errors.c b/clang/test/CodeGen/X86/amx_transpose_errors.c
deleted file mode 100644
index 80368c580c793..0000000000000
--- a/clang/test/CodeGen/X86/amx_transpose_errors.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown \
-// RUN: -target-feature +amx-int8 -target-feature +amx-bf16 -target-feature +amx-transpose \
-// RUN: -target-feature +avx512f -target-feature +amx-fp16 -target-feature +amx-complex -verify
-
-#include <immintrin.h>
-#include <stddef.h>
-
-// Transpose
-void test_tile_2rpntlvwz0(const void *A, size_t B) {
- _tile_2rpntlvwz0(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_2rpntlvwz0t1(const void *A, size_t B) {
- _tile_2rpntlvwz0t1(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_2rpntlvwz1(const void *A, size_t B) {
- _tile_2rpntlvwz1(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_2rpntlvwz1t1(const void *A, size_t B) {
- _tile_2rpntlvwz1t1(8, A, B); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_tdpbf16ps()
-{
- _tile_tdpbf16ps(8, 2, 3); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_tdpbf16ps(1, 8, 3); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_tdpbf16ps(1, 2, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_tdpbf16ps(1, 1, 3); // expected-error {{tile arguments must refer to different tiles}}
- _tile_tdpbf16ps(1, 2, 1); // expected-error {{tile arguments must refer to different tiles}}
- _tile_tdpbf16ps(1, 2, 2); // expected-error {{tile arguments must refer to different tiles}}
-}
-
-void test_tile_tdpfp16ps()
-{
- _tile_tdpfp16ps(8, 5, 6); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_tdpfp16ps(1, 8, 6); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_tdpfp16ps(1, 5, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_tdpfp16ps(1, 1, 3); // expected-error {{tile arguments must refer to different tiles}}
- _tile_tdpfp16ps(1, 2, 1); // expected-error {{tile arguments must refer to different tiles}}
- _tile_tdpfp16ps(1, 2, 2); // expected-error {{tile arguments must refer to different tiles}}
-}
-
-void test_tile_transposed()
-{
- _tile_transposed(8, 2); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
- _tile_transposed(1, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
-}
-
-void test_tile_tcmmimfp16ps() {
- _tile_tcmmimfp16ps(16, 2, 3); // expected-error {{argument value 16 is outside the valid range [0, 7]}}
- _tile_tcmmimfp16ps(1, 26, 3); // expected-error {{argument value 26 is outside the valid range [0, 7]}}
- _tile_tcmmimfp16ps(1, 2, 36); // expected-error {{argument value 36 is outside the valid range [0, 7]}}
- _tile_tcmmimfp16ps(1, 1, 3); // expected-error {{tile arguments must refer to different tiles}}
-}
-
-void test_tile_tcmmrlfp16ps() {
- _tile_tcmmrlfp16ps(16, 2, 3); // expected-error {{argument value 16 is outside the valid range [0, 7]}}
- _tile_tcmmrlfp16ps(1, 26, 3); // expected-error {{argument value 26 is outside the valid range [0, 7]}}
- _tile_tcmmrlfp16ps(1, 2, 36); // expected-error {{argument value 36 is outside the valid range [0, 7]}}
- _tile_tcmmrlfp16ps(1, 1, 3); // expected-error {{tile arguments must refer to different tiles}}
-}
-
-void test_tile_conjtcmmimfp16ps() {
- _tile_conjtcmmimfp16ps(16, 2, 3); // expected-error {{argument value 16 is outside the valid range [0, 7]}}
- _tile_conjtcmmimfp16ps(1, 26, 3); // expected-error {{argument value 26 is outside the valid range [0, 7]}}
- _tile_conjtcmmimfp16ps(1, 2, 36); // expected-error {{argument value 36 is outside the valid range [0, 7]}}
- _tile_conjtcmmimfp16ps(1, 2, 1); // expected-error {{tile arguments must refer to different tiles}}
-}
-
-void test_tile_conjtfp16() {
- _tile_conjtfp16(16, 2); // expected-error {{argument value 16 is outside the valid range [0, 7]}}
- _tile_conjtfp16(1, 26); // expected-error {{argument value 26 is outside the valid range [0, 7]}}
-}
diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c
index 3717c449d6601..f1660b1afb518 100644
--- a/clang/test/Driver/x86-target-features.c
+++ b/clang/test/Driver/x86-target-features.c
@@ -304,13 +304,6 @@
// AMX-COMPLEX: "-target-feature" "+amx-complex"
// NO-AMX-COMPLEX: "-target-feature" "-amx-complex"
-// RUN: %clang --target=x86_64-unknown-linux-gnu -mamx-transpose %s \
-// RUN: -### -o %t.o 2>&1 | FileCheck -check-prefix=AMX-TRANSPOSE %s
-// RUN: %clang --target=x86_64-unknown-linux-gnu -mno-amx-transpose %s \
-// RUN: -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-AMX-TRANSPOSE %s
-// AMX-TRANSPOSE: "-target-feature" "+amx-transpose"
-// NO-AMX-TRANSPOSE: "-target-feature" "-amx-transpose"
-
// RUN: %clang --target=x86_64-unknown-linux-gnu -mamx-avx512 %s \
// RUN: -### -o %t.o 2>&1 | FileCheck -check-prefix=AMX-AVX512 %s
// RUN: %clang --target=x86_64-unknown-linux-gnu -mno-amx-avx512 %s \
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index a3c3697c3a0b9..40a287f2003ce 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -1841,7 +1841,6 @@
// CHECK_DMR_M32: #define __AMX_MOVRS__ 1
// CHECK_DMR_M32: #define __AMX_TF32__ 1
// CHECK_GNR_M32: #define __AMX_TILE__ 1
-// CHECK_DMR_M32: #define __AMX_TRANSPOSE__ 1
// CHECK_DMR_M32: #define __AVX10_2_512__ 1
// CHECK_DMR_M32: #define __AVX10_2__ 1
// CHECK_GNR_M32: #define __AVX2__ 1
@@ -1947,7 +1946,6 @@
// CHECK_DMR_M64: #define __AMX_MOVRS__ 1
// CHECK_DMR_M64: #define __AMX_TF32__ 1
// CHECK_GNR_M64: #define __AMX_TILE__ 1
-// CHECK_DMR_M64: #define __AMX_TRANSPOSE__ 1
// CHECK_DMR_M64: #define __AVX10_2_512__ 1
// CHECK_DMR_M64: #define __AVX10_2__ 1
// CHECK_GNR_M64: #define __AVX2__ 1
diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c
index 5f17641878761..78f8b19459c2f 100644
--- a/clang/test/Preprocessor/x86_target_features.c
+++ b/clang/test/Preprocessor/x86_target_features.c
@@ -526,18 +526,6 @@
// NO-AMX-COMPLEX-NOT: #define __AMX_COMPLEX__ 1
-// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mamx-transpose -x c \
-// RUN: -E -dM -o - %s | FileCheck -check-prefix=AMX-TRANSPOSE %s
-
-// AMX-TRANSPOSE: #define __AMX_TRANSPOSE__ 1
-
-// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mno-amx-transpose -x c \
-// RUN: -E -dM -o - %s | FileCheck -check-prefix=NO-AMX-TRANSPOSE %s
-// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mamx-transpose -mno-amx-tile \
-// RUN: -x c -E -dM -o - %s | FileCheck -check-prefix=NO-AMX-TRANSPOSE %s
-
-// NO-AMX-TRANSPOSE-NOT: #define __AMX_TRANSPOSE__ 1
-
// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mamx-avx512 -x c \
// RUN: -E -dM -o - %s | FileCheck -check-prefix=AMX-AVX512 %s
diff --git a/llvm/include/llvm/CodeGen/TileShapeInfo.h b/llvm/include/llvm/CodeGen/TileShapeInfo.h
index 9cea327819895..24d9de842645a 100644
--- a/llvm/include/llvm/CodeGen/TileShapeInfo.h
+++ b/llvm/include/llvm/CodeGen/TileShapeInfo.h
@@ -34,30 +34,9 @@ class ShapeT {
if (MRI)
deduceImm(MRI);
}
- // When ShapeT has multiple shapes, we only use Shapes (never use Row and Col)
- // and ImmShapes. Due to the most case is only one shape (just simply use
- // Shape.Row or Shape.Col), so here we don't merge Row and Col into vector
- // Shapes to keep the speed and code simplicity.
- // TODO: The upper solution is a temporary way to minimize current tile
- // register allocation code changes. It can not handle both Reg shape and
- // Imm shape for different shapes (e.g. shape 1 is reg shape while shape 2
- // is imm shape). Refine me when we have more multi-tile shape instructions!
- ShapeT(ArrayRef<MachineOperand *> ShapesOperands,
- const MachineRegisterInfo *MRI = nullptr)
- : Row(nullptr), Col(nullptr), RowImm(InvalidImmShape),
- ColImm(InvalidImmShape) {
- assert(ShapesOperands.size() % 2 == 0 && "Miss row or col!");
-
- llvm::append_range(Shapes, ShapesOperands);
-
- if (MRI)
- deduceImm(MRI);
- }
ShapeT()
: Row(nullptr), Col(nullptr), RowImm(InvalidImmShape),
ColImm(InvalidImmShape) {}
- // TODO: We need to extern cmp operator for multi-shapes if
- // we have requirement in the future.
bool operator==(const ShapeT &Shape) const {
MachineOperand *R = Shape.Row;
MachineOperand *C = Shape.Col;
@@ -74,40 +53,11 @@ class ShapeT {
bool operator!=(const ShapeT &Shape) const { return !(*this == Shape); }
- MachineOperand *getRow(unsigned I = 0) const {
- if (Shapes.empty())
- return Row;
- assert(Shapes.size() / 2 >= I && "Get invalid row from id!");
- return Shapes[I * 2];
- }
-
- MachineOperand *getCol(unsigned I = 0) const {
- if (Shapes.empty())
- return Col;
- assert(Shapes.size() / 2 >= I && "Get invalid col from id!");
- return Shapes[I * 2 + 1];
- }
-
- int64_t getRowImm(unsigned I = 0) const {
- if (ImmShapes.empty())
- return RowImm;
- assert(ImmShapes.size() / 2 >= I && "Get invalid imm row from id!");
- return ImmShapes[I * 2];
- }
-
- int64_t getColImm(unsigned I = 0) const {
- if (ImmShapes.empty())
- return ColImm;
- assert(ImmShapes.size() / 2 >= I && "Get invalid imm col from id!");
- return ImmShapes[I * 2 + 1];
- }
+ MachineOperand *getRow() const { return Row; }
+ MachineOperand *getCol() const { return Col; }
- unsigned getShapeNum() {
- if (Shapes.empty())
- return isValid() ? 1 : 0;
- else
- return Shapes.size() / 2;
- }
+ int64_t getRowImm() const { return RowImm; }
+ int64_t getColImm() const { return ColImm; }
bool isValid() { return (Row != nullptr) && (Col != nullptr); }
@@ -120,35 +70,14 @@ class ShapeT {
for (const MachineOperand &DefMO : MRI->def_operands(Reg)) {
const auto *MI = DefMO.getParent();
if (MI->isMoveImmediate()) {
- assert(MI->getNumOperands() == 2 &&
- "Unsupported number of operands in instruction for setting "
- "row/column.");
- if (MI->getOperand(1).isImm()) {
- Imm = MI->getOperand(1).getImm();
- } else {
- assert(MI->getOperand(1).isImplicit() &&
- "Operand 1 is assumed to be implicit.");
- Imm = 0;
- }
+ Imm = MI->getOperand(1).getImm();
break;
}
}
return Imm;
};
- if (Shapes.empty()) { // Single Shape
- RowImm = GetImm(Row->getReg());
- ColImm = GetImm(Col->getReg());
- // The number of rows of 2nd destination buffer is assigned by the one of
- // 1st destination buffer. If the column size is equal to zero, the row
- // size should be reset to zero too.
- if (ColImm == 0)
- Row = Col;
- } else { // Multiple Shapes
- for (auto *Shape : Shapes) {
- int64_t ImmShape = GetImm(Shape->getReg());
- ImmShapes.push_back(ImmShape);
- }
- }
+ RowImm = GetImm(Row->getReg());
+ ColImm = GetImm(Col->getReg());
}
private:
@@ -157,9 +86,6 @@ class ShapeT {
MachineOperand *Col;
int64_t RowImm = -1;
int64_t ColImm = -1;
- // Multiple Shapes
- SmallVector<MachineOperand *, 0> Shapes;
- SmallVector<int64_t, 0> ImmShapes;
};
} // namespace llvm
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 81fbfbf0bb1b4..1dd23f60c7e1e 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5505,46 +5505,6 @@ let TargetPrefix = "x86" in {
[ImmArg<ArgIndex<0>>,
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
- // AMX-TRANSPOSE
- def int_x86_t2rpntlvwz0 : ClangBuiltin<"__builtin_ia32_t2rpntlvwz0">,
- Intrinsic<[], [llvm_i8_ty, llvm_ptr_ty, llvm_i64_ty],
- [ImmArg<ArgIndex<0>>]>;
- def int_x86_t2rpntlvwz0t1 : ClangBuiltin<"__builtin_ia32_t2rpntlvwz0t1">,
- Intrinsic<[], [llvm_i8_ty, llvm_ptr_ty, llvm_i64_ty],
- [ImmArg<ArgIndex<0>>]>;
- def int_x86_t2rpntlvwz1 : ClangBuiltin<"__builtin_ia32_t2rpntlvwz1">,
- Intrinsic<[], [llvm_i8_ty, llvm_ptr_ty, llvm_i64_ty],
- [ImmArg<ArgIndex<0>>]>;
- def int_x86_t2rpntlvwz1t1 : ClangBuiltin<"__builtin_ia32_t2rpntlvwz1t1">,
- Intrinsic<[], [llvm_i8_ty, llvm_ptr_ty, llvm_i64_ty],
- [ImmArg<ArgIndex<0>>]>;
- def int_x86_ttransposed : ClangBuiltin<"__builtin_ia32_ttransposed">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
- def int_x86_ttdpbf16ps : ClangBuiltin<"__builtin_ia32_ttdpbf16ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
- def int_x86_ttdpfp16ps : ClangBuiltin<"__builtin_ia32_ttdpfp16ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
- def int_x86_ttcmmimfp16ps : ClangBuiltin<"__builtin_ia32_ttcmmimfp16ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
- def int_x86_ttcmmrlfp16ps : ClangBuiltin<"__builtin_ia32_ttcmmrlfp16ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
- def int_x86_tconjtcmmimfp16ps : ClangBuiltin<"__builtin_ia32_tconjtcmmimfp16ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
- def int_x86_tconjtfp16 : ClangBuiltin<"__builtin_ia32_tconjtfp16">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
-
// AMX-MORVS, AMX-TRANSPOSE
def int_x86_t2rpntlvwz0rs : ClangBuiltin<"__builtin_ia32_t2rpntlvwz0rs">,
Intrinsic<[], [llvm_i8_ty, llvm_ptr_ty, llvm_i64_ty],
@@ -5685,61 +5645,6 @@ let TargetPrefix = "x86" in {
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_ptr_ty, llvm_i64_ty],
[IntrArgMemOnly]>;
- def int_x86_t2rpntlvwz0_internal :
- Intrinsic<[llvm_x86amx_ty, llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_ptr_ty, llvm_i64_ty],
- []>;
- def int_x86_t2rpntlvwz0t1_internal :
- Intrinsic<[llvm_x86amx_ty, llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_ptr_ty, llvm_i64_ty],
- []>;
- def int_x86_t2rpntlvwz1_internal :
- Intrinsic<[llvm_x86amx_ty, llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_ptr_ty, llvm_i64_ty],
- []>;
- def int_x86_t2rpntlvwz1t1_internal :
- Intrinsic<[llvm_x86amx_ty, llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_ptr_ty, llvm_i64_ty],
- []>;
- def int_x86_ttransposed_internal :
- ClangBuiltin<"__builtin_ia32_ttransposed_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty], []>;
- def int_x86_ttdpbf16ps_internal :
- ClangBuiltin<"__builtin_ia32_ttdpbf16ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
- llvm_x86amx_ty, llvm_x86amx_ty,
- llvm_x86amx_ty], []>;
- def int_x86_ttdpfp16ps_internal :
- ClangBuiltin<"__builtin_ia32_ttdpfp16ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
- llvm_x86amx_ty, llvm_x86amx_ty,
- llvm_x86amx_ty], []>;
- def int_x86_ttcmmimfp16ps_internal :
- ClangBuiltin<"__builtin_ia32_ttcmmimfp16ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
- llvm_x86amx_ty, llvm_x86amx_ty,
- llvm_x86amx_ty], []>;
- def int_x86_ttcmmrlfp16ps_internal :
- ClangBuiltin<"__builtin_ia32_ttcmmrlfp16ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
- llvm_x86amx_ty, llvm_x86amx_ty,
- llvm_x86amx_ty], []>;
- def int_x86_tconjtcmmimfp16ps_internal :
- ClangBuiltin<"__builtin_ia32_tconjtcmmimfp16ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
- llvm_x86amx_ty, llvm_x86amx_ty,
- llvm_x86amx_ty], []>;
- def int_x86_tconjtfp16_internal :
- ClangBuiltin<"__builtin_ia32_tconjtfp16_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty], []>;
-
def int_x86_tcvtrowd2ps_internal :
ClangBuiltin<"__builtin_ia32_tcvtrowd2ps_internal">,
Intrinsic<[llvm_v16f32_ty],
@@ -5775,20 +5680,11 @@ let TargetPrefix = "x86" in {
Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
ImmArg<ArgIndex<2>>]>;
- def int_x86_ttmmultf32ps : ClangBuiltin<"__builtin_ia32_ttmmultf32ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
def int_x86_tmmultf32ps_internal :
ClangBuiltin<"__builtin_ia32_tmmultf32ps_internal">,
Intrinsic<[llvm_x86amx_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
llvm_x86amx_ty, llvm_x86amx_ty], []>;
- def int_x86_ttmmultf32ps_internal :
- ClangBuiltin<"__builtin_ia32_ttmmultf32ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
- llvm_x86amx_ty, llvm_x86amx_ty], []>;
def int_x86_tdpbf8ps_internal :
ClangBuiltin<"__builtin_ia32_tdpbf8ps_internal">,
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 4aa6c01d29cc2..6f6f65dc075f3 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -511,7 +511,6 @@ enum OperandEncoding { ENCODINGS ENCODING_max };
ENUM_ENTRY(TYPE_VK, "mask register") \
ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \
ENUM_ENTRY(TYPE_TMM, "tile") \
- ENUM_ENTRY(TYPE_TMM_PAIR, "tile pair") \
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index a94eab1d7ae34..78cf46406192e 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -268,7 +268,6 @@ X86_FEATURE_COMPAT(AVX10_2_512, "avx10.2-512", 0)
X86_FEATURE (MOVRS, "movrs")
X86_FEATURE (ZU, "zu")
X86_FEATURE (AMX_FP8, "amx-fp8")
-X86_FEATURE (AMX_TRANSPOSE, "amx-transpose")
X86_FEATURE (AMX_MOVRS, "amx-movrs")
X86_FEATURE (AMX_AVX512, "amx-avx512")
X86_FEATURE (AMX_TF32, "amx-tf32")
diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h
index 89ac53e0ecac9..a92272573bacd 100644
--- a/llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -620,37 +620,6 @@ struct X86Operand final : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(Reg));
}
- bool isTILEPair() const {
- return Kind == Register &&
- X86MCRegisterClasses[X86::TILERegClassID].contains(getReg());
- }
-
- void addTILEPairOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- MCRegister Reg = getReg();
- switch (Reg.id()) {
- default:
- llvm_unreachable("Invalid tile register!");
- case X86::TMM0:
- case X86::TMM1:
- Reg = X86::TMM0_TMM1;
- break;
- case X86::TMM2:
- case X86::TMM3:
- Reg = X86::TMM2_TMM3;
- break;
- case X86::TMM4:
- case X86::TMM5:
- Reg = X86::TMM4_TMM5;
- break;
- case X86::TMM6:
- case X86::TMM7:
- Reg = X86::TMM6_TMM7;
- break;
- }
- Inst.addOperand(MCOperand::createReg(Reg));
- }
-
void addMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 5) && "Invalid number of operands!");
if (getMemBaseReg())
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 4927b453458ef..7d2b5eb900133 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -810,10 +810,6 @@ static int readModRM(struct InternalInstruction *insn) {
if (index > 7) \
*valid = 0; \
return prefix##_TMM0 + index; \
- case TYPE_TMM_PAIR: \
- if (index > 7) \
- *valid = 0; \
- return prefix##_TMM0_TMM1 + (index / 2); \
case TYPE_VK: \
index &= 0xf; \
if (index > 7) \
@@ -2323,7 +2319,6 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
case TYPE_YMM:
case TYPE_ZMM:
case TYPE_TMM:
- case TYPE_TMM_PAIR:
case TYPE_VK_PAIR:
case TYPE_VK:
case TYPE_DEBUGREG:
diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
index dc9af2caa77b1..b0aa70be12d83 100644
--- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
+++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
@@ -535,12 +535,6 @@ namespace X86Disassembler {
ENTRY(TMM6) \
ENTRY(TMM7)
-#define REGS_TMM_PAIRS \
- ENTRY(TMM0_TMM1) \
- ENTRY(TMM2_TMM3) \
- ENTRY(TMM4_TMM5) \
- ENTRY(TMM6_TMM7)
-
#define ALL_EA_BASES \
EA_BASES_16BIT \
EA_BASES_32BIT \
@@ -565,7 +559,6 @@ namespace X86Disassembler {
REGS_DEBUG \
REGS_CONTROL \
REGS_TMM \
- REGS_TMM_PAIRS \
ENTRY(RIP)
/// All possible values of the base field for effective-address
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
index 1c5f1663d4f52..759d95e5a18ea 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
@@ -467,22 +467,3 @@ void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo,
}
llvm_unreachable("Unknown mask pair register name");
}
-
-void X86InstPrinterCommon::printTILEPair(const MCInst *MI, unsigned OpNo,
- raw_ostream &OS) {
- switch (MI->getOperand(OpNo).getReg()) {
- case X86::TMM0_TMM1:
- printRegName(OS, X86::TMM0);
- return;
- case X86::TMM2_TMM3:
- printRegName(OS, X86::TMM2);
- return;
- case X86::TMM4_TMM5:
- printRegName(OS, X86::TMM4);
- return;
- case X86::TMM6_TMM7:
- printRegName(OS, X86::TMM6);
- return;
- }
- llvm_unreachable("Unknown mask pair register name");
-}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h
index 2c9467ca7c615..cb55f2f0019b5 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h
@@ -40,7 +40,6 @@ class X86InstPrinterCommon : public MCInstPrinter {
const MCSubtargetInfo &STI);
void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
- void printTILEPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
};
} // end namespace llvm
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index a1fd366e59444..9e291a6ae431f 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -274,9 +274,6 @@ def FeatureAMXFP8 : SubtargetFeature<"amx-fp8", "HasAMXFP8", "true",
def FeatureAMXMOVRS : SubtargetFeature<"amx-movrs", "HasAMXMOVRS", "true",
"Support AMX-MOVRS instructions",
[FeatureAMXTILE]>;
-def FeatureAMXTRANSPOSE : SubtargetFeature<"amx-transpose", "HasAMXTRANSPOSE", "true",
- "Support AMX amx-transpose instructions",
- [FeatureAMXTILE]>;
def FeatureAMXAVX512 : SubtargetFeature<"amx-avx512",
"HasAMXAVX512", "true",
"Support AMX-AVX512 instructions",
@@ -1177,8 +1174,7 @@ def ProcessorFeatures {
FeatureAMXMOVRS,
FeatureAMXAVX512,
FeatureAMXFP8,
- FeatureAMXTF32,
- FeatureAMXTRANSPOSE];
+ FeatureAMXTF32];
list<SubtargetFeature> DMRFeatures =
!listconcat(GNRDFeatures, DMRAdditionalFeatures);
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index 4a9b824b0db14..c7e1d3e9db2c8 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -649,149 +649,6 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MI.setDesc(TII->get(Opc));
return true;
}
- // TILEPAIRLOAD is just for TILEPair spill, we don't have corresponding
- // AMX instruction to support it. So, split it to 2 load instructions:
- // "TILEPAIRLOAD TMM0:TMM1, Base, Scale, Index, Offset, Segment" -->
- // "TILELOAD TMM0, Base, Scale, Index, Offset, Segment" +
- // "TILELOAD TMM1, Base, Scale, Index, Offset + TMM_SIZE, Segment"
- case X86::PTILEPAIRLOAD: {
- int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm();
- Register TReg = MBBI->getOperand(0).getReg();
- bool DstIsDead = MBBI->getOperand(0).isDead();
- Register TReg0 = TRI->getSubReg(TReg, X86::sub_t0);
- Register TReg1 = TRI->getSubReg(TReg, X86::sub_t1);
- unsigned TmmSize = TRI->getRegSizeInBits(X86::TILERegClass) / 8;
-
- MachineInstrBuilder MIBLo =
- BuildMI(MBB, MBBI, DL, TII->get(X86::TILELOADD))
- .addReg(TReg0, RegState::Define | getDeadRegState(DstIsDead));
- MachineInstrBuilder MIBHi =
- BuildMI(MBB, MBBI, DL, TII->get(X86::TILELOADD))
- .addReg(TReg1, RegState::Define | getDeadRegState(DstIsDead));
-
- for (int i = 0; i < X86::AddrNumOperands; ++i) {
- MIBLo.add(MBBI->getOperand(1 + i));
- if (i == X86::AddrDisp)
- MIBHi.addImm(Disp + TmmSize);
- else
- MIBHi.add(MBBI->getOperand(1 + i));
- }
-
- // Make sure the first stride reg used in first tileload is alive.
- MachineOperand &Stride =
- MIBLo.getInstr()->getOperand(1 + X86::AddrIndexReg);
- Stride.setIsKill(false);
-
- // Split the memory operand, adjusting the offset and size for the halves.
- MachineMemOperand *OldMMO = MBBI->memoperands().front();
- MachineFunction *MF = MBB.getParent();
- MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, TmmSize);
- MachineMemOperand *MMOHi =
- MF->getMachineMemOperand(OldMMO, TmmSize, TmmSize);
-
- MIBLo.setMemRefs(MMOLo);
- MIBHi.setMemRefs(MMOHi);
-
- // Delete the pseudo.
- MBB.erase(MBBI);
- return true;
- }
- // Similar with TILEPAIRLOAD, TILEPAIRSTORE is just for TILEPair spill, no
- // corresponding AMX instruction to support it. So, split it too:
- // "TILEPAIRSTORE Base, Scale, Index, Offset, Segment, TMM0:TMM1" -->
- // "TILESTORE Base, Scale, Index, Offset, Segment, TMM0" +
- // "TILESTORE Base, Scale, Index, Offset + TMM_SIZE, Segment, TMM1"
- case X86::PTILEPAIRSTORE: {
- int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm();
- Register TReg = MBBI->getOperand(X86::AddrNumOperands).getReg();
- bool SrcIsKill = MBBI->getOperand(X86::AddrNumOperands).isKill();
- Register TReg0 = TRI->getSubReg(TReg, X86::sub_t0);
- Register TReg1 = TRI->getSubReg(TReg, X86::sub_t1);
- unsigned TmmSize = TRI->getRegSizeInBits(X86::TILERegClass) / 8;
-
- MachineInstrBuilder MIBLo =
- BuildMI(MBB, MBBI, DL, TII->get(X86::TILESTORED));
- MachineInstrBuilder MIBHi =
- BuildMI(MBB, MBBI, DL, TII->get(X86::TILESTORED));
-
- for (int i = 0; i < X86::AddrNumOperands; ++i) {
- MIBLo.add(MBBI->getOperand(i));
- if (i == X86::AddrDisp)
- MIBHi.addImm(Disp + TmmSize);
- else
- MIBHi.add(MBBI->getOperand(i));
- }
- MIBLo.addReg(TReg0, getKillRegState(SrcIsKill));
- MIBHi.addReg(TReg1, getKillRegState(SrcIsKill));
-
- // Make sure the first stride reg used in first tilestore is alive.
- MachineOperand &Stride = MIBLo.getInstr()->getOperand(X86::AddrIndexReg);
- Stride.setIsKill(false);
-
- // Split the memory operand, adjusting the offset and size for the halves.
- MachineMemOperand *OldMMO = MBBI->memoperands().front();
- MachineFunction *MF = MBB.getParent();
- MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, TmmSize);
- MachineMemOperand *MMOHi =
- MF->getMachineMemOperand(OldMMO, TmmSize, TmmSize);
-
- MIBLo.setMemRefs(MMOLo);
- MIBHi.setMemRefs(MMOHi);
-
- // Delete the pseudo.
- MBB.erase(MBBI);
- return true;
- }
- case X86::PT2RPNTLVWZ0V:
- case X86::PT2RPNTLVWZ0T1V:
- case X86::PT2RPNTLVWZ1V:
- case X86::PT2RPNTLVWZ1T1V:
- case X86::PT2RPNTLVWZ0RSV:
- case X86::PT2RPNTLVWZ0RST1V:
- case X86::PT2RPNTLVWZ1RSV:
- case X86::PT2RPNTLVWZ1RST1V: {
- for (unsigned i = 3; i > 0; --i)
- MI.removeOperand(i);
- unsigned Opc;
- switch (Opcode) {
- case X86::PT2RPNTLVWZ0V:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0);
- break;
- case X86::PT2RPNTLVWZ0T1V:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0T1);
- break;
- case X86::PT2RPNTLVWZ1V:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1);
- break;
- case X86::PT2RPNTLVWZ1T1V:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1T1);
- break;
- case X86::PT2RPNTLVWZ0RSV:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0RS);
- break;
- case X86::PT2RPNTLVWZ0RST1V:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0RST1);
- break;
- case X86::PT2RPNTLVWZ1RSV:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1RS);
- break;
- case X86::PT2RPNTLVWZ1RST1V:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1RST1);
- break;
- default:
- llvm_unreachable("Impossible Opcode!");
- }
- MI.setDesc(TII->get(Opc));
- return true;
- }
- case X86::PTTRANSPOSEDV:
- case X86::PTCONJTFP16V: {
- for (int i = 2; i > 0; --i)
- MI.removeOperand(i);
- MI.setDesc(TII->get(Opcode == X86::PTTRANSPOSEDV ? X86::TTRANSPOSED
- : X86::TCONJTFP16));
- return true;
- }
case X86::PTCMMIMFP16PSV:
case X86::PTCMMRLFP16PSV:
case X86::PTDPBSSDV:
@@ -800,13 +657,7 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::PTDPBUUDV:
case X86::PTDPBF16PSV:
case X86::PTDPFP16PSV:
- case X86::PTTDPBF16PSV:
- case X86::PTTDPFP16PSV:
- case X86::PTTCMMIMFP16PSV:
- case X86::PTTCMMRLFP16PSV:
- case X86::PTCONJTCMMIMFP16PSV:
case X86::PTMMULTF32PSV:
- case X86::PTTMMULTF32PSV:
case X86::PTDPBF8PSV:
case X86::PTDPBHF8PSV:
case X86::PTDPHBF8PSV:
@@ -824,27 +675,9 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
case X86::PTDPFP16PSV: Opc = X86::TDPFP16PS; break;
- case X86::PTTDPBF16PSV:
- Opc = X86::TTDPBF16PS;
- break;
- case X86::PTTDPFP16PSV:
- Opc = X86::TTDPFP16PS;
- break;
- case X86::PTTCMMIMFP16PSV:
- Opc = X86::TTCMMIMFP16PS;
- break;
- case X86::PTTCMMRLFP16PSV:
- Opc = X86::TTCMMRLFP16PS;
- break;
- case X86::PTCONJTCMMIMFP16PSV:
- Opc = X86::TCONJTCMMIMFP16PS;
- break;
case X86::PTMMULTF32PSV:
Opc = X86::TMMULTF32PS;
break;
- case X86::PTTMMULTF32PSV:
- Opc = X86::TTMMULTF32PS;
- break;
case X86::PTDPBF8PSV:
Opc = X86::TDPBF8PS;
break;
diff --git a/llvm/lib/Target/X86/X86FastPreTileConfig.cpp b/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
index 787b71d425cb3..443d016519504 100644
--- a/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
@@ -268,18 +268,14 @@ void X86FastPreTileConfig::reload(MachineBasicBlock::iterator UseMI,
}
static unsigned getTileDefNum(MachineRegisterInfo *MRI, Register Reg) {
- if (Reg.isVirtual()) {
- unsigned RegClassID = MRI->getRegClass(Reg)->getID();
- if (RegClassID == X86::TILERegClassID)
- return 1;
- if (RegClassID == X86::TILEPAIRRegClassID)
- return 2;
- } else {
- if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
- return 1;
- if (Reg >= X86::TMM0_TMM1 && Reg <= X86::TMM6_TMM7)
- return 2;
+ if (Reg.isVirtual() &&
+ MRI->getRegClass(Reg)->getID() == X86::TILERegClassID) {
+ return 1;
}
+
+ if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
+ return 1;
+
return 0;
}
@@ -636,19 +632,7 @@ bool X86FastPreTileConfig::configBasicBlock(MachineBasicBlock &MBB) {
else if (dominates(MBB, LastShapeMI, ColMI))
LastShapeMI = ColMI;
}
- unsigned TileDefNum = getTileDefNum(MRI, MI.getOperand(0).getReg());
- if (TileDefNum > 1) {
- for (unsigned I = 1; I < TileDefNum; I++) {
- MachineOperand *ColxMO = &MI.getOperand(2 + I);
- MachineInstr *ColxMI = MRI->getVRegDef(ColxMO->getReg());
- if (ColxMI->getParent() == &MBB) {
- if (!LastShapeMI)
- LastShapeMI = ColxMI;
- else if (dominates(MBB, LastShapeMI, ColxMI))
- LastShapeMI = ColxMI;
- }
- }
- }
+
// If there is user live out of the tilecfg, spill it and reload in
// before the user.
Register TileReg = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/X86/X86FastTileConfig.cpp b/llvm/lib/Target/X86/X86FastTileConfig.cpp
index 11d331b11737f..8af708b5c3cc0 100644
--- a/llvm/lib/Target/X86/X86FastTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86FastTileConfig.cpp
@@ -94,13 +94,9 @@ static unsigned getNumDefTiles(MachineRegisterInfo *MRI, MachineInstr &MI) {
if (Reg.isVirtual()) {
if (MRI->getRegClass(Reg)->getID() == X86::TILERegClassID)
return 1;
- if (MRI->getRegClass(Reg)->getID() == X86::TILEPAIRRegClassID)
- return 2;
}
if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
return 1;
- if (Reg >= X86::TMM0_TMM1 && Reg <= X86::TMM6_TMM7)
- return 2;
}
return 0;
@@ -109,8 +105,6 @@ static unsigned getNumDefTiles(MachineRegisterInfo *MRI, MachineInstr &MI) {
static unsigned getTMMIndex(Register Reg) {
if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
return Reg - X86::TMM0;
- if (Reg >= X86::TMM0_TMM1 && Reg <= X86::TMM6_TMM7)
- return (Reg - X86::TMM0_TMM1) * 2;
llvm_unreachable("Invalid Tmm Reg!");
}
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 4393f6ecaa033..d4418c8563780 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -337,23 +337,8 @@ namespace {
// lowering but before ISEL.
bool isAMXSDNode(SDNode *N) const {
// Check if N is AMX SDNode:
- // 1. check specific opcode since these carry MVT::Untyped instead of
- // x86amx_type;
- // 2. check result type;
- // 3. check operand type;
- switch (N->getOpcode()) {
- default:
- break;
- case X86::PT2RPNTLVWZ0V:
- case X86::PT2RPNTLVWZ0T1V:
- case X86::PT2RPNTLVWZ1V:
- case X86::PT2RPNTLVWZ1T1V:
- case X86::PT2RPNTLVWZ0RSV:
- case X86::PT2RPNTLVWZ0RST1V:
- case X86::PT2RPNTLVWZ1RSV:
- case X86::PT2RPNTLVWZ1RST1V:
- return true;
- }
+ // 1. check result type;
+ // 2. check operand type;
for (unsigned Idx = 0, E = N->getNumValues(); Idx != E; ++Idx) {
if (N->getValueType(Idx) == MVT::x86amx)
return true;
@@ -5398,65 +5383,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, CNode);
return;
}
- case Intrinsic::x86_t2rpntlvwz0rs:
- case Intrinsic::x86_t2rpntlvwz0rst1:
- case Intrinsic::x86_t2rpntlvwz1rs:
- case Intrinsic::x86_t2rpntlvwz1rst1:
- if (!Subtarget->hasAMXMOVRS())
- break;
- [[fallthrough]];
- case Intrinsic::x86_t2rpntlvwz0:
- case Intrinsic::x86_t2rpntlvwz0t1:
- case Intrinsic::x86_t2rpntlvwz1:
- case Intrinsic::x86_t2rpntlvwz1t1: {
- if (!Subtarget->hasAMXTRANSPOSE())
- break;
- auto *MFI =
- CurDAG->getMachineFunction().getInfo<X86MachineFunctionInfo>();
- MFI->setAMXProgModel(AMXProgModelEnum::DirectReg);
- unsigned Opc;
- switch (IntNo) {
- default:
- llvm_unreachable("Unexpected intrinsic!");
- case Intrinsic::x86_t2rpntlvwz0:
- Opc = X86::PT2RPNTLVWZ0;
- break;
- case Intrinsic::x86_t2rpntlvwz0t1:
- Opc = X86::PT2RPNTLVWZ0T1;
- break;
- case Intrinsic::x86_t2rpntlvwz1:
- Opc = X86::PT2RPNTLVWZ1;
- break;
- case Intrinsic::x86_t2rpntlvwz1t1:
- Opc = X86::PT2RPNTLVWZ1T1;
- break;
- case Intrinsic::x86_t2rpntlvwz0rs:
- Opc = X86::PT2RPNTLVWZ0RS;
- break;
- case Intrinsic::x86_t2rpntlvwz0rst1:
- Opc = X86::PT2RPNTLVWZ0RST1;
- break;
- case Intrinsic::x86_t2rpntlvwz1rs:
- Opc = X86::PT2RPNTLVWZ1RS;
- break;
- case Intrinsic::x86_t2rpntlvwz1rst1:
- Opc = X86::PT2RPNTLVWZ1RST1;
- break;
- }
- // FIXME: Match displacement and scale.
- unsigned TIndex = Node->getConstantOperandVal(2);
- SDValue TReg = getI8Imm(TIndex, dl);
- SDValue Base = Node->getOperand(3);
- SDValue Scale = getI8Imm(1, dl);
- SDValue Index = Node->getOperand(4);
- SDValue Disp = CurDAG->getTargetConstant(0, dl, MVT::i32);
- SDValue Segment = CurDAG->getRegister(0, MVT::i16);
- SDValue Chain = Node->getOperand(0);
- SDValue Ops[] = {TReg, Base, Scale, Index, Disp, Segment, Chain};
- MachineSDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
- ReplaceNode(Node, CNode);
- return;
- }
}
break;
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5785440a20e43..787f05ebf99d7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -27946,67 +27946,6 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
Operation.getValue(1));
}
- case Intrinsic::x86_t2rpntlvwz0rs_internal:
- case Intrinsic::x86_t2rpntlvwz0rst1_internal:
- case Intrinsic::x86_t2rpntlvwz1rs_internal:
- case Intrinsic::x86_t2rpntlvwz1rst1_internal:
- case Intrinsic::x86_t2rpntlvwz0_internal:
- case Intrinsic::x86_t2rpntlvwz0t1_internal:
- case Intrinsic::x86_t2rpntlvwz1_internal:
- case Intrinsic::x86_t2rpntlvwz1t1_internal: {
- auto *X86MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
- X86MFI->setAMXProgModel(AMXProgModelEnum::ManagedRA);
- unsigned IntNo = Op.getConstantOperandVal(1);
- unsigned Opc = 0;
- switch (IntNo) {
- default:
- llvm_unreachable("Unexpected intrinsic!");
- case Intrinsic::x86_t2rpntlvwz0_internal:
- Opc = X86::PT2RPNTLVWZ0V;
- break;
- case Intrinsic::x86_t2rpntlvwz0t1_internal:
- Opc = X86::PT2RPNTLVWZ0T1V;
- break;
- case Intrinsic::x86_t2rpntlvwz1_internal:
- Opc = X86::PT2RPNTLVWZ1V;
- break;
- case Intrinsic::x86_t2rpntlvwz1t1_internal:
- Opc = X86::PT2RPNTLVWZ1T1V;
- break;
- case Intrinsic::x86_t2rpntlvwz0rs_internal:
- Opc = X86::PT2RPNTLVWZ0RSV;
- break;
- case Intrinsic::x86_t2rpntlvwz0rst1_internal:
- Opc = X86::PT2RPNTLVWZ0RST1V;
- break;
- case Intrinsic::x86_t2rpntlvwz1rs_internal:
- Opc = X86::PT2RPNTLVWZ1RSV;
- break;
- case Intrinsic::x86_t2rpntlvwz1rst1_internal:
- Opc = X86::PT2RPNTLVWZ1RST1V;
- break;
- }
-
- SDLoc DL(Op);
- SDVTList VTs = DAG.getVTList(MVT::Untyped, MVT::Other);
-
- SDValue Ops[] = {Op.getOperand(2), // Row
- Op.getOperand(3), // Col0
- Op.getOperand(4), // Col1
- Op.getOperand(5), // Base
- DAG.getTargetConstant(1, DL, MVT::i8), // Scale
- Op.getOperand(6), // Index
- DAG.getTargetConstant(0, DL, MVT::i32), // Disp
- DAG.getRegister(0, MVT::i16), // Segment
- Op.getOperand(0)}; // Chain
-
- MachineSDNode *Res = DAG.getMachineNode(Opc, DL, VTs, Ops);
- SDValue Res0 = DAG.getTargetExtractSubreg(X86::sub_t0, DL, MVT::x86amx,
- SDValue(Res, 0));
- SDValue Res1 = DAG.getTargetExtractSubreg(X86::sub_t1, DL, MVT::x86amx,
- SDValue(Res, 0));
- return DAG.getMergeValues({Res0, Res1, SDValue(Res, 1)}, DL);
- }
case Intrinsic::x86_atomic_bts_rm:
case Intrinsic::x86_atomic_btc_rm:
case Intrinsic::x86_atomic_btr_rm: {
@@ -37745,10 +37684,6 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
assert (Imm < 8 && "Illegal tmm index");
return X86::TMM0 + Imm;
};
- auto TMMImmToTMMPair = [](unsigned Imm) {
- assert(Imm < 8 && "Illegal tmm pair index.");
- return X86::TMM0_TMM1 + Imm / 2;
- };
switch (MI.getOpcode()) {
default:
llvm_unreachable("Unexpected instr type to insert");
@@ -38129,13 +38064,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::PTDPBHF8PS:
case X86::PTDPHBF8PS:
case X86::PTDPHF8PS:
- case X86::PTTDPBF16PS:
- case X86::PTTDPFP16PS:
- case X86::PTTCMMIMFP16PS:
- case X86::PTTCMMRLFP16PS:
- case X86::PTCONJTCMMIMFP16PS:
- case X86::PTMMULTF32PS:
- case X86::PTTMMULTF32PS: {
+ case X86::PTMMULTF32PS: {
unsigned Opc;
switch (MI.getOpcode()) {
default: llvm_unreachable("illegal opcode!");
@@ -38155,27 +38084,9 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::PTDPBHF8PS: Opc = X86::TDPBHF8PS; break;
case X86::PTDPHBF8PS: Opc = X86::TDPHBF8PS; break;
case X86::PTDPHF8PS: Opc = X86::TDPHF8PS; break;
- case X86::PTTDPBF16PS:
- Opc = X86::TTDPBF16PS;
- break;
- case X86::PTTDPFP16PS:
- Opc = X86::TTDPFP16PS;
- break;
- case X86::PTTCMMIMFP16PS:
- Opc = X86::TTCMMIMFP16PS;
- break;
- case X86::PTTCMMRLFP16PS:
- Opc = X86::TTCMMRLFP16PS;
- break;
- case X86::PTCONJTCMMIMFP16PS:
- Opc = X86::TCONJTCMMIMFP16PS;
- break;
case X86::PTMMULTF32PS:
Opc = X86::TMMULTF32PS;
break;
- case X86::PTTMMULTF32PS:
- Opc = X86::TTMMULTF32PS;
- break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, MIMD, TII->get(Opc));
@@ -38246,70 +38157,6 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
- case X86::PT2RPNTLVWZ0:
- case X86::PT2RPNTLVWZ0T1:
- case X86::PT2RPNTLVWZ1:
- case X86::PT2RPNTLVWZ1T1:
- case X86::PT2RPNTLVWZ0RS:
- case X86::PT2RPNTLVWZ0RST1:
- case X86::PT2RPNTLVWZ1RS:
- case X86::PT2RPNTLVWZ1RST1: {
- const DebugLoc &DL = MI.getDebugLoc();
- unsigned Opc;
-#define GET_EGPR_IF_ENABLED(OPC) (Subtarget.hasEGPR() ? OPC##_EVEX : OPC)
- switch (MI.getOpcode()) {
- default:
- llvm_unreachable("Unexpected instruction!");
- case X86::PT2RPNTLVWZ0:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0);
- break;
- case X86::PT2RPNTLVWZ0T1:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0T1);
- break;
- case X86::PT2RPNTLVWZ1:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1);
- break;
- case X86::PT2RPNTLVWZ1T1:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1T1);
- break;
- case X86::PT2RPNTLVWZ0RS:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0RS);
- break;
- case X86::PT2RPNTLVWZ0RST1:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ0RST1);
- break;
- case X86::PT2RPNTLVWZ1RS:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1RS);
- break;
- case X86::PT2RPNTLVWZ1RST1:
- Opc = GET_EGPR_IF_ENABLED(X86::T2RPNTLVWZ1RST1);
- break;
- }
-#undef GET_EGPR_IF_ENABLED
- MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
- MIB.addReg(TMMImmToTMMPair(MI.getOperand(0).getImm()), RegState::Define);
-
- MIB.add(MI.getOperand(1)); // base
- MIB.add(MI.getOperand(2)); // scale
- MIB.add(MI.getOperand(3)); // index
- MIB.add(MI.getOperand(4)); // displacement
- MIB.add(MI.getOperand(5)); // segment
- MI.eraseFromParent(); // The pseudo is gone now.
- return BB;
- }
- case X86::PTTRANSPOSED:
- case X86::PTCONJTFP16: {
- const DebugLoc &DL = MI.getDebugLoc();
- unsigned Opc = MI.getOpcode() == X86::PTTRANSPOSED ? X86::TTRANSPOSED
- : X86::TCONJTFP16;
-
- MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
- MIB.addReg(TMMImmToTMMReg(MI.getOperand(0).getImm()), RegState::Define);
- MIB.addReg(TMMImmToTMMReg(MI.getOperand(1).getImm()), RegState::Undef);
-
- MI.eraseFromParent(); // The pseudo is gone now.
- return BB;
- }
case X86::PTCVTROWPS2BF16Hrri:
case X86::PTCVTROWPS2BF16Lrri:
case X86::PTCVTROWPS2PHHrri:
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index 69a5115201ef2..522782abd710f 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -338,188 +338,6 @@ let Predicates = [HasAMXFP8, In64BitMode] in {
}
}
-let Predicates = [HasAMXTILE, In64BitMode], isPseudo = true, SchedRW = [WriteSystem] in {
- let mayStore = 1 in
- def PTILEPAIRSTORE : PseudoI<(outs), (ins opaquemem:$src1, TILEPair:$src2), []>;
- let mayLoad = 1 in
- def PTILEPAIRLOAD : PseudoI<(outs TILEPair:$dst), (ins opaquemem:$src), []>;
-}
-
-multiclass T2RPNTLVW_Base<bits<8> op1, bits<8> op2, string rs, string suffix> {
- def Z0#rs#suffix : I<op1, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
- "t2rpntlvwz0" #!tolower(rs)# "\t{$src, $dst|$dst, $src}", []>, PS;
- def Z0#rs#T1#suffix : I<op2, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
- "t2rpntlvwz0" #!tolower(rs)# "t1\t{$src, $dst|$dst, $src}", []>, PS;
- def Z1#rs#suffix : I<op1, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
- "t2rpntlvwz1" #!tolower(rs)# "\t{$src, $dst|$dst, $src}", []>, PD;
- def Z1#rs#T1#suffix : I<op2, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
- "t2rpntlvwz1" #!tolower(rs)# "t1\t{$src, $dst|$dst, $src}", []>, PD;
-}
-
-let Predicates = [HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in
- defm T2RPNTLVW : T2RPNTLVW_Base<0x6e, 0x6f, "", "">, T8, VEX;
-
-let Predicates = [HasAMXTRANSPOSE, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in
- defm T2RPNTLVW : T2RPNTLVW_Base<0x6e, 0x6f, "", "_EVEX">, T8, EVEX, NoCD8;
-
-let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in
- defm T2RPNTLVW : T2RPNTLVW_Base<0xf8, 0xf9, "RS", "">, T_MAP5, VEX;
-
-let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in
- defm T2RPNTLVW : T2RPNTLVW_Base<0xf8, 0xf9, "RS", "_EVEX">, T_MAP5, EVEX, NoCD8;
-
-let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
- let SchedRW = [WriteSystem] in {
- def TTRANSPOSED : I<0x5f, MRMSrcReg, (outs TILE:$dst), (ins TILE:$src),
- "ttransposed\t{$src, $dst|$dst, $src}", []>, VEX, T8, XS;
- let isPseudo = true in {
- def PT2RPNTLVWZ0V : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- def PT2RPNTLVWZ0T1V : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- def PT2RPNTLVWZ1V : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- def PT2RPNTLVWZ1T1V : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- }
-
- def PTTRANSPOSEDV : PseudoI<(outs TILE:$dst),
- (ins GR16:$src1, GR16:$src2, TILE:$src),
- [(set TILE: $dst,
- (int_x86_ttransposed_internal GR16:$src1, GR16:$src2,
- TILE:$src))]>;
-
- let usesCustomInserter = 1 in {
- def PT2RPNTLVWZ0 : PseudoI<(outs), (ins u8imm:$dst,
- sibmem:$src1), []>;
- def PT2RPNTLVWZ0T1 : PseudoI<(outs), (ins u8imm:$dst,
- sibmem:$src1), []>;
- def PT2RPNTLVWZ1 : PseudoI<(outs), (ins u8imm:$dst,
- sibmem:$src1), []>;
- def PT2RPNTLVWZ1T1 : PseudoI<(outs), (ins u8imm:$dst,
- sibmem:$src1), []>;
- def PTTRANSPOSED : PseudoI<(outs), (ins u8imm:$dst, u8imm:$src),
- [(int_x86_ttransposed timm:$dst, timm:$src)]>;
- }
- }
-} // HasAMXTILE, HasAMXTRANSPOSE
-
-let Predicates = [HasAMXBF16, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in {
- let Constraints = "$src1 = $dst" in
- def TTDPBF16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
- (ins TILE:$src1, TILE:$src2, TILE:$src3),
- "ttdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>, VEX, VVVV, T8,XS;
- let Constraints = "$src4 = $dst" in
- def PTTDPBF16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
- GR16:$src2, GR16:$src3, TILE:$src4,
- TILE:$src5, TILE:$src6),
- [(set TILE: $dst,
- (int_x86_ttdpbf16ps_internal GR16:$src1, GR16:$src2,
- GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
- let usesCustomInserter = 1 in
- def PTTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
- [(int_x86_ttdpbf16ps timm:$src1, timm:$src2, timm:$src3)]>;
-}
-
-let Predicates = [HasAMXFP16, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in {
- let Constraints = "$src1 = $dst" in
- def TTDPFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
- (ins TILE:$src1, TILE:$src2, TILE:$src3),
- "ttdpfp16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>, VEX, VVVV, T8,XD;
- let Constraints = "$src4 = $dst" in
- def PTTDPFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
- GR16:$src2, GR16:$src3, TILE:$src4,
- TILE:$src5, TILE:$src6),
- [(set TILE: $dst,
- (int_x86_ttdpfp16ps_internal GR16:$src1, GR16:$src2,
- GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
- let usesCustomInserter = 1 in
- def PTTDPFP16PS : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
- [(int_x86_ttdpfp16ps timm:$src1, timm:$src2, timm:$src3)]>;
-}
-
-let Predicates = [HasAMXCOMPLEX, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in {
- let Constraints = "$src1 = $dst" in {
- def TTCMMIMFP16PS : I<0x6b, MRMSrcReg4VOp3, (outs TILE:$dst),
- (ins TILE:$src1, TILE:$src2, TILE:$src3),
- "ttcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
- []>, VEX, VVVV, T8,XD;
- def TTCMMRLFP16PS: I<0x6b, MRMSrcReg4VOp3, (outs TILE:$dst),
- (ins TILE:$src1, TILE:$src2, TILE:$src3),
- "ttcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
- []>, VEX, VVVV, T8,XS;
- def TCONJTCMMIMFP16PS : I<0x6b, MRMSrcReg4VOp3, (outs TILE:$dst),
- (ins TILE:$src1, TILE:$src2, TILE:$src3),
- "tconjtcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
- []>, VEX, VVVV, WIG, T8,PS;
- }
- def TCONJTFP16 : I<0x6b, MRMSrcReg, (outs TILE:$dst), (ins TILE:$src),
- "tconjtfp16\t{$src, $dst|$dst, $src}", []>, VEX, T8,PD;
-
- let Constraints = "$src4 = $dst" in {
- def PTTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
- GR16:$src2, GR16:$src3, TILE:$src4,
- TILE:$src5, TILE:$src6),
- [(set TILE: $dst,
- (int_x86_ttcmmimfp16ps_internal GR16:$src1, GR16:$src2,
- GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
- def PTTCMMRLFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
- GR16:$src2, GR16:$src3, TILE:$src4,
- TILE:$src5, TILE:$src6),
- [(set TILE: $dst,
- (int_x86_ttcmmrlfp16ps_internal GR16:$src1, GR16:$src2,
- GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
- def PTCONJTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
- GR16:$src2, GR16:$src3, TILE:$src4,
- TILE:$src5, TILE:$src6),
- [(set TILE: $dst,
- (int_x86_tconjtcmmimfp16ps_internal GR16:$src1, GR16:$src2,
- GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
- }
- def PTCONJTFP16V : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2, TILE:$src3),
- [(set TILE: $dst, (int_x86_tconjtfp16_internal GR16:$src1, GR16:$src2, TILE:$src3))]>;
-
- let usesCustomInserter = 1 in {
- def PTTCMMIMFP16PS : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
- [(int_x86_ttcmmimfp16ps timm:$src1, timm:$src2, timm:$src3)]>;
- def PTTCMMRLFP16PS : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
- [(int_x86_ttcmmrlfp16ps timm:$src1, timm:$src2, timm:$src3)]>;
- def PTCONJTCMMIMFP16PS : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
- [(int_x86_tconjtcmmimfp16ps timm:$src1, timm:$src2, timm:$src3)]>;
- def PTCONJTFP16 : PseudoI<(outs), (ins u8imm:$dst, u8imm:$src),
- [(int_x86_tconjtfp16 timm:$dst, timm:$src)]>;
- }
-}
-
-let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in {
- let isPseudo = true in {
- def PT2RPNTLVWZ0RSV : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- def PT2RPNTLVWZ0RST1V : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- def PT2RPNTLVWZ1RSV : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- def PT2RPNTLVWZ1RST1V : PseudoI<(outs TILEPair:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
- []>;
- }
- let usesCustomInserter = 1 in {
- def PT2RPNTLVWZ0RS : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
- def PT2RPNTLVWZ0RST1 : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
- def PT2RPNTLVWZ1RS : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
- def PT2RPNTLVWZ1RST1 : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
- }
-} // HasAMXMOVRS, HasAMXTRANSPOSE
-
multiclass TILELOADDRS_Base<string suffix> {
def suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
"tileloaddrs\t{$src1, $dst|$dst, $src1}", []>, T8, XD;
@@ -721,29 +539,3 @@ let Predicates = [HasAMXTF32, In64BitMode] in {
}
} // SchedRW = [WriteSystem]
} // HasAMXTF32
-
-let Predicates = [HasAMXTF32, HasAMXTRANSPOSE, In64BitMode] in {
- let SchedRW = [WriteSystem] in {
- let Constraints = "$src1 = $dst" in {
- def TTMMULTF32PS: I<0x48, MRMSrcReg4VOp3, (outs TILE:$dst),
- (ins TILE:$src1, TILE:$src2, TILE:$src3),
- "ttmmultf32ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>, VEX, VVVV, T8, PS;
- }
- let Constraints = "$src4 = $dst" in {
- def PTTMMULTF32PSV : PseudoI<(outs TILE:$dst),
- (ins GR16:$src1, GR16:$src2, GR16:$src3,
- TILE:$src4, TILE:$src5, TILE:$src6),
- [(set TILE:$dst,
- (int_x86_ttmmultf32ps_internal GR16:$src1,
- GR16:$src2, GR16:$src3, TILE:$src4,
- TILE:$src5, TILE:$src6))]>;
- }
- let usesCustomInserter = 1 in {
- def PTTMMULTF32PS : PseudoI<(outs),
- (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
- [(int_x86_ttmmultf32ps timm:$src1, timm:$src2,
- timm:$src3)]>;
- }
- } // SchedRW = [WriteSystem]
-} // HasAMXTF32, HasAMXTRANSPOSE
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5c23f917d0530..e97b57a49cefe 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4544,11 +4544,6 @@ static unsigned getLoadStoreRegOpcode(Register Reg,
return Load ? GET_EGPR_IF_ENABLED(X86::TILELOADD)
: GET_EGPR_IF_ENABLED(X86::TILESTORED);
#undef GET_EGPR_IF_ENABLED
- case 2048:
- assert(X86::TILEPAIRRegClass.hasSubClassEq(RC) &&
- "Unknown 2048-byte regclass");
- assert(STI.hasAMXTILE() && "Using 2048-bit register requires AMX-TILE");
- return Load ? X86::PTILEPAIRLOAD : X86::PTILEPAIRSTORE;
}
}
@@ -4741,10 +4736,8 @@ static bool isAMXOpcode(unsigned Opc) {
return false;
case X86::TILELOADD:
case X86::TILESTORED:
- case X86::TILELOADD_EVEX:
case X86::TILESTORED_EVEX:
- case X86::PTILEPAIRLOAD:
- case X86::PTILEPAIRSTORE:
+ case X86::TILELOADD_EVEX:
return true;
}
}
@@ -4757,8 +4750,7 @@ void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB,
default:
llvm_unreachable("Unexpected special opcode!");
case X86::TILESTORED:
- case X86::TILESTORED_EVEX:
- case X86::PTILEPAIRSTORE: {
+ case X86::TILESTORED_EVEX: {
// tilestored %tmm, (%sp, %idx)
MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
@@ -4772,8 +4764,7 @@ void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB,
break;
}
case X86::TILELOADD:
- case X86::TILELOADD_EVEX:
- case X86::PTILEPAIRLOAD: {
+ case X86::TILELOADD_EVEX: {
// tileloadd (%sp, %idx), %tmm
MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
diff --git a/llvm/lib/Target/X86/X86InstrOperands.td b/llvm/lib/Target/X86/X86InstrOperands.td
index 5207ecad127a2..6ba07f74d74c5 100644
--- a/llvm/lib/Target/X86/X86InstrOperands.td
+++ b/llvm/lib/Target/X86/X86InstrOperands.td
@@ -536,10 +536,3 @@ def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> {
def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> {
let ParserMatchClass = VK16PairAsmOperand;
}
-
-let RenderMethod = "addTILEPairOperands" in
- def TILEPairAsmOperand : AsmOperandClass { let Name = "TILEPair"; }
-
-def TILEPair : RegisterOperand<TILEPAIR, "printTILEPair"> {
- let ParserMatchClass = TILEPairAsmOperand;
-}
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index c20bb05018b4d..98104a6fad1a9 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -183,7 +183,6 @@ def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">;
def HasAMXCOMPLEX : Predicate<"Subtarget->hasAMXCOMPLEX()">;
def HasAMXFP8 : Predicate<"Subtarget->hasAMXFP8()">;
def HasAMXMOVRS : Predicate<"Subtarget->hasAMXMOVRS()">;
-def HasAMXTRANSPOSE : Predicate<"Subtarget->hasAMXTRANSPOSE()">;
def HasAMXAVX512 : Predicate<"Subtarget->hasAMXAVX512()">;
def HasAMXTF32 : Predicate<"Subtarget->hasAMXTF32()">;
def HasUINTR : Predicate<"Subtarget->hasUINTR()">;
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index 8ffd454f4f73e..2fc5d38ef5055 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -74,22 +74,6 @@ static bool isAMXCast(Instruction *II) {
match(II, m_Intrinsic<Intrinsic::x86_cast_tile_to_vector>(m_Value()));
}
-// Some instructions may return more than one tiles.
-// e.g: call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal
-static unsigned getNumDefTiles(IntrinsicInst *II) {
- Type *Ty = II->getType();
- if (Ty->isX86_AMXTy())
- return 1;
-
- unsigned Num = 0;
- for (unsigned i = 0; i < Ty->getNumContainedTypes(); i++) {
- Type *STy = Ty->getContainedType(i);
- if (STy->isX86_AMXTy())
- Num++;
- }
- return Num;
-}
-
static bool isAMXIntrinsic(Value *I) {
auto *II = dyn_cast<IntrinsicInst>(I);
if (!II)
@@ -98,7 +82,7 @@ static bool isAMXIntrinsic(Value *I) {
return false;
// Check if return type or parameter is x86_amx. If it is x86_amx
// the intrinsic must be x86 amx intrinsics.
- if (getNumDefTiles(II) > 0)
+ if (II->getType()->isX86_AMXTy())
return true;
for (Value *V : II->args()) {
if (V->getType()->isX86_AMXTy())
@@ -137,27 +121,7 @@ static Instruction *getFirstNonAllocaInTheEntryBlock(Function &F) {
llvm_unreachable("No terminator in the entry block!");
}
-class ShapeCalculator {
-private:
- const TargetMachine *TM = nullptr;
-
- // In AMX intrinsics we let Shape = {Row, Col}, but the
- // RealCol = Col / ElementSize. We may use the RealCol
- // as a new Row for other new created AMX intrinsics.
- std::map<Value *, Value *> Col2Row, Row2Col;
-
-public:
- ShapeCalculator(const TargetMachine *TargetM) : TM(TargetM) {}
- std::pair<Value *, Value *> getShape(IntrinsicInst *II, unsigned OpNo);
- std::pair<Value *, Value *> getShape(PHINode *Phi);
- Value *getRowFromCol(Instruction *II, Value *V, unsigned Granularity);
- Value *getColFromRow(Instruction *II, Value *V, unsigned Granularity);
-};
-
-Value *ShapeCalculator::getRowFromCol(Instruction *II, Value *V,
- unsigned Granularity) {
- if (auto It = Col2Row.find(V); It != Col2Row.end())
- return It->second;
+static Value *getRowFromCol(Instruction *II, Value *V, unsigned Granularity) {
IRBuilder<> Builder(II);
Value *RealRow = nullptr;
if (isa<ConstantInt>(V))
@@ -186,47 +150,16 @@ Value *ShapeCalculator::getRowFromCol(Instruction *II, Value *V,
getFirstNonAllocaInTheEntryBlock(*II->getFunction()));
RealRow = NewBuilder.CreateUDiv(V, NewBuilder.getInt16(Granularity));
}
- Col2Row[V] = RealRow;
return RealRow;
}
-Value *ShapeCalculator::getColFromRow(Instruction *II, Value *V,
- unsigned Granularity) {
- if (auto It = Row2Col.find(V); It != Row2Col.end())
- return It->second;
- IRBuilder<> Builder(II);
- Value *RealCol = nullptr;
- if (isa<ConstantInt>(V))
- RealCol =
- Builder.getInt16((cast<ConstantInt>(V)->getSExtValue()) * Granularity);
- else if (isa<Instruction>(V)) {
- Builder.SetInsertPoint(cast<Instruction>(V));
- RealCol = Builder.CreateNUWMul(V, Builder.getInt16(Granularity));
- cast<Instruction>(RealCol)->moveAfter(cast<Instruction>(V));
- } else {
- // When it is not a const value and it is a function argument, we create
- // Row at the entry bb.
- IRBuilder<> NewBuilder(
- getFirstNonAllocaInTheEntryBlock(*II->getFunction()));
- RealCol = NewBuilder.CreateNUWMul(V, NewBuilder.getInt16(Granularity));
- }
- Row2Col[V] = RealCol;
- return RealCol;
-}
-
// TODO: Refine the row and col-in-bytes of tile to row and col of matrix.
-std::pair<Value *, Value *> ShapeCalculator::getShape(IntrinsicInst *II,
- unsigned OpNo) {
- (void)TM;
+std::pair<Value *, Value *> getShape(IntrinsicInst *II, unsigned OpNo) {
IRBuilder<> Builder(II);
Value *Row = nullptr, *Col = nullptr;
switch (II->getIntrinsicID()) {
default:
llvm_unreachable("Expect amx intrinsics");
- case Intrinsic::x86_t2rpntlvwz0_internal:
- case Intrinsic::x86_t2rpntlvwz0t1_internal:
- case Intrinsic::x86_t2rpntlvwz1_internal:
- case Intrinsic::x86_t2rpntlvwz1t1_internal:
case Intrinsic::x86_tileloadd64_internal:
case Intrinsic::x86_tileloaddt164_internal:
case Intrinsic::x86_tilestored64_internal:
@@ -271,13 +204,6 @@ std::pair<Value *, Value *> ShapeCalculator::getShape(IntrinsicInst *II,
}
break;
}
- case Intrinsic::x86_ttransposed_internal:
- case Intrinsic::x86_tconjtfp16_internal: {
- assert((OpNo == 2) && "Illegal Operand Number.");
- Row = getRowFromCol(II, II->getArgOperand(1), 4);
- Col = getColFromRow(II, II->getArgOperand(0), 4);
- break;
- }
case Intrinsic::x86_tcvtrowd2ps_internal:
case Intrinsic::x86_tcvtrowps2bf16h_internal:
case Intrinsic::x86_tcvtrowps2bf16l_internal:
@@ -289,34 +215,12 @@ std::pair<Value *, Value *> ShapeCalculator::getShape(IntrinsicInst *II,
Col = II->getArgOperand(1);
break;
}
- case Intrinsic::x86_ttdpbf16ps_internal:
- case Intrinsic::x86_ttdpfp16ps_internal:
- case Intrinsic::x86_ttcmmimfp16ps_internal:
- case Intrinsic::x86_ttcmmrlfp16ps_internal:
- case Intrinsic::x86_tconjtcmmimfp16ps_internal:
- case Intrinsic::x86_ttmmultf32ps_internal: {
- switch (OpNo) {
- case 3:
- Row = II->getArgOperand(0);
- Col = II->getArgOperand(1);
- break;
- case 4:
- Row = getRowFromCol(II, II->getArgOperand(2), 4);
- Col = getColFromRow(II, II->getArgOperand(0), 4);
- break;
- case 5:
- Row = getRowFromCol(II, II->getArgOperand(2), 4);
- Col = II->getArgOperand(1);
- break;
- }
- break;
- }
}
return std::make_pair(Row, Col);
}
-std::pair<Value *, Value *> ShapeCalculator::getShape(PHINode *Phi) {
+static std::pair<Value *, Value *> getShape(PHINode *Phi) {
Use &U = *(Phi->use_begin());
unsigned OpNo = U.getOperandNo();
User *V = U.getUser();
@@ -349,15 +253,14 @@ std::pair<Value *, Value *> ShapeCalculator::getShape(PHINode *Phi) {
namespace {
class X86LowerAMXType {
Function &Func;
- ShapeCalculator *SC;
// In AMX intrinsics we let Shape = {Row, Col}, but the
// RealCol = Col / ElementSize. We may use the RealCol
// as a new Row for other new created AMX intrinsics.
- std::map<Value *, Value *> Col2Row, Row2Col;
+ std::map<Value *, Value *> Col2Row;
public:
- X86LowerAMXType(Function &F, ShapeCalculator *ShapeC) : Func(F), SC(ShapeC) {}
+ X86LowerAMXType(Function &F) : Func(F) {}
bool visit();
void combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast);
void combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST);
@@ -374,7 +277,7 @@ void X86LowerAMXType::combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast) {
Use &U = *(Bitcast->use_begin());
unsigned OpNo = U.getOperandNo();
auto *II = cast<IntrinsicInst>(U.getUser());
- std::tie(Row, Col) = SC->getShape(II, OpNo);
+ std::tie(Row, Col) = getShape(II, OpNo);
IRBuilder<> Builder(Bitcast);
// Use the maximun column as stride.
Value *Stride = Builder.getInt64(64);
@@ -454,7 +357,7 @@ bool X86LowerAMXType::transformBitcast(BitCastInst *Bitcast) {
Builder.CreateStore(Src, AllocaAddr);
// TODO we can pick an constant operand for the shape.
Value *Row = nullptr, *Col = nullptr;
- std::tie(Row, Col) = SC->getShape(II, OpNo);
+ std::tie(Row, Col) = getShape(II, OpNo);
std::array<Value *, 4> Args = {Row, Col, I8Ptr, Stride};
Value *NewInst =
Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal, Args);
@@ -594,18 +497,11 @@ static Value *getAllocaPos(BasicBlock *BB) {
static Instruction *createTileStore(Instruction *TileDef, Value *Ptr) {
assert(TileDef->getType()->isX86_AMXTy() && "Not define tile!");
- auto *II = dyn_cast<IntrinsicInst>(TileDef);
- unsigned Idx = 0;
- // Extract tile from multiple tiles' def.
- if (auto *Extr = dyn_cast<ExtractValueInst>(TileDef)) {
- assert(Extr->hasIndices() && "Tile extract miss index!");
- Idx = Extr->getIndices()[0];
- II = cast<IntrinsicInst>(Extr->getOperand(0));
- }
+ auto *II = cast<IntrinsicInst>(TileDef);
assert(II && "Not tile intrinsic!");
- Value *Row = II->getOperand(Idx);
- Value *Col = II->getOperand(Idx + 1);
+ Value *Row = II->getOperand(0);
+ Value *Col = II->getOperand(1);
BasicBlock *BB = TileDef->getParent();
BasicBlock::iterator Iter = TileDef->getIterator();
@@ -624,20 +520,14 @@ static void replaceWithTileLoad(Use &U, Value *Ptr, bool IsPHI = false) {
// Get tile shape.
IntrinsicInst *II = nullptr;
- unsigned Idx = 0;
if (IsPHI) {
Value *PhiOp = cast<PHINode>(V)->getIncomingValue(0);
II = cast<IntrinsicInst>(PhiOp);
- } else if (auto *Extr = dyn_cast<ExtractValueInst>(V)) {
- // Extract tile from multiple tiles' def.
- assert(Extr->hasIndices() && "Tile extract miss index!");
- Idx = Extr->getIndices()[0];
- II = cast<IntrinsicInst>(Extr->getOperand(0));
} else {
II = cast<IntrinsicInst>(V);
}
- Value *Row = II->getOperand(Idx);
- Value *Col = II->getOperand(Idx + 1);
+ Value *Row = II->getOperand(0);
+ Value *Col = II->getOperand(1);
Instruction *UserI = cast<Instruction>(U.getUser());
IRBuilder<> Builder(UserI);
@@ -848,12 +738,10 @@ namespace {
class X86LowerAMXCast {
Function &Func;
- ShapeCalculator *SC;
std::unique_ptr<DominatorTree> DT;
public:
- X86LowerAMXCast(Function &F, ShapeCalculator *ShapeC)
- : Func(F), SC(ShapeC), DT(nullptr) {}
+ X86LowerAMXCast(Function &F) : Func(F), DT(nullptr) {}
bool combineCastStore(IntrinsicInst *Cast, StoreInst *ST);
bool combineLoadCast(IntrinsicInst *Cast, LoadInst *LD);
bool combineTilezero(IntrinsicInst *Cast);
@@ -932,7 +820,7 @@ bool X86LowerAMXCast::optimizeAMXCastFromPhi(
if (!isa<UndefValue>(IncValue) && !IncConst->isZeroValue())
return false;
Value *Row = nullptr, *Col = nullptr;
- std::tie(Row, Col) = SC->getShape(OldPN);
+ std::tie(Row, Col) = getShape(OldPN);
// TODO: If it is not constant the Row and Col must domoniate tilezero
// that we are going to create.
if (!Row || !Col || !isa<Constant>(Row) || !isa<Constant>(Col))
@@ -1063,19 +951,6 @@ bool X86LowerAMXCast::optimizeAMXCastFromPhi(
return true;
}
-static Value *getShapeFromAMXIntrinsic(Value *Inst, unsigned ShapeIdx,
- bool IsRow) {
- if (!isAMXIntrinsic(Inst))
- return nullptr;
-
- auto *II = cast<IntrinsicInst>(Inst);
- if (IsRow)
- return II->getOperand(0);
-
- assert(ShapeIdx < 2 && "Currently 2 shapes in 1 instruction at most!");
- return II->getOperand(ShapeIdx + 1);
-}
-
// %43 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %42)
// store <256 x i32> %43, <256 x i32>* %p, align 64
// -->
@@ -1090,38 +965,13 @@ bool X86LowerAMXCast::combineCastStore(IntrinsicInst *Cast, StoreInst *ST) {
if (!Tile->hasOneUse())
return false;
- // We don't fetch shape from tilestore, we only get shape from tiledef,
- // so we can set the max tile shape to tilestore for special cases.
+ auto *II = cast<IntrinsicInst>(Tile);
+ // Tile is output from AMX intrinsic. The first operand of the
+ // intrinsic is row, the second operand of the intrinsic is column.
+ Value *Row = II->getOperand(0);
+ Value *Col = II->getOperand(1);
+
IRBuilder<> Builder(ST);
- Value *Row = nullptr;
- Value *Col = nullptr;
-
- if (isAMXIntrinsic(Tile)) {
- auto *II = cast<IntrinsicInst>(Tile);
- // Tile is output from AMX intrinsic. The first operand of the
- // intrinsic is row, the second operand of the intrinsic is column.
- Row = II->getOperand(0);
- Col = II->getOperand(1);
- } else {
- // Now we supported multi-tiles value in structure, so we may get tile
- // from extracting multi-tiles structure.
- // For example:
- // %6 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 %1,
- // i16 %2, i16 %3, i8* %4, i64 %5)
- // %7 = extractvalue { x86_amx, x86_amx } %6, 0
- // %8 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %7)
- // store <256 x i32> %8, <256 x i32>* %0, align 1024
- //
- // TODO: Currently we only handle extractvalue case, enhance me for other
- // cases if possible.
- auto *II = cast<ExtractValueInst>(Tile);
- assert(II && "We meet unhandle source in fetching tile value!");
- unsigned ShapeIdx = II->getIndices()[0];
- Value *Tiles = II->getOperand(0);
- Row = getShapeFromAMXIntrinsic(Tiles, ShapeIdx, true);
- Col = getShapeFromAMXIntrinsic(Tiles, ShapeIdx, false);
- }
- assert(Row && Col && "Shape got failed!");
// Stride should be equal to col(measured by bytes)
Value *Stride = Builder.CreateSExt(Col, Builder.getInt64Ty());
@@ -1146,7 +996,7 @@ bool X86LowerAMXCast::combineLoadCast(IntrinsicInst *Cast, LoadInst *LD) {
// shape information through def-use chain.
if (!isAMXIntrinsic(II))
return false;
- std::tie(Row, Col) = SC->getShape(II, OpNo);
+ std::tie(Row, Col) = getShape(II, OpNo);
IRBuilder<> Builder(LD);
// Stride should be equal to col(measured by bytes)
Value *Stride = Builder.CreateSExt(Col, Builder.getInt64Ty());
@@ -1189,7 +1039,7 @@ bool X86LowerAMXCast::combineTilezero(IntrinsicInst *Cast) {
if (!isAMXIntrinsic(II))
return false;
- std::tie(Row, Col) = SC->getShape(II, OpNo);
+ std::tie(Row, Col) = getShape(II, OpNo);
IRBuilder<> Builder(Cast);
Value *NewInst =
@@ -1384,7 +1234,7 @@ bool X86LowerAMXCast::transformAMXCast(IntrinsicInst *AMXCast) {
Builder.CreateStore(Src, AllocaAddr);
// TODO we can pick an constant operand for the shape.
Value *Row = nullptr, *Col = nullptr;
- std::tie(Row, Col) = SC->getShape(II, OpNo);
+ std::tie(Row, Col) = getShape(II, OpNo);
std::array<Value *, 4> Args = {
Row, Col, I8Ptr, Builder.CreateSExt(Col, Builder.getInt64Ty())};
Value *NewInst =
@@ -1445,14 +1295,13 @@ bool lowerAmxType(Function &F, const TargetMachine *TM,
return false;
bool C = false;
- ShapeCalculator SC(TM);
- X86LowerAMXCast LAC(F, &SC);
+ X86LowerAMXCast LAC(F);
C |= LAC.combineAMXcast(TLI);
// There might be remaining AMXcast after combineAMXcast and they should be
// handled elegantly.
C |= LAC.transformAllAMXCast();
- X86LowerAMXType LAT(F, &SC);
+ X86LowerAMXType LAT(F);
C |= LAT.visit();
// Prepare for fast register allocation at O0.
diff --git a/llvm/lib/Target/X86/X86PreTileConfig.cpp b/llvm/lib/Target/X86/X86PreTileConfig.cpp
index 2a1c49957bf7a..c28a578256334 100644
--- a/llvm/lib/Target/X86/X86PreTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86PreTileConfig.cpp
@@ -144,8 +144,6 @@ class X86PreTileConfig : public MachineFunctionPass {
unsigned Shapes = 0;
if (MRI->getRegClass(MO.getReg())->getID() == X86::TILERegClassID)
Shapes = 1;
- if (MRI->getRegClass(MO.getReg())->getID() == X86::TILEPAIRRegClassID)
- Shapes = 2;
if (!Shapes)
return false;
@@ -252,13 +250,6 @@ void X86PreTileConfig::collectShapeInfo(MachineInstr &MI, unsigned Shapes) {
if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second)
continue;
- // This happens when column = 0 in multi-tile operand.
- if (DefMI->getOpcode() == X86::COPY) {
- MachineInstr *MI = MRI->getVRegDef(DefMI->getOperand(1).getReg());
- if (MI && MI->isMoveImmediate())
- continue;
- }
-
if (DefMI->isPHI()) {
for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2)
if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB()))
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 76979e37c4618..72f38133e21ff 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -597,10 +597,6 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(*AI);
}
- // Reserve low half pair registers in case they are used by RA aggressively.
- Reserved.set(X86::TMM0_TMM1);
- Reserved.set(X86::TMM2_TMM3);
-
assert(checkAllSuperRegsMarked(Reserved,
{X86::SIL, X86::DIL, X86::BPL, X86::SPL,
X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
@@ -621,7 +617,7 @@ unsigned X86RegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const {
// and try to return the minimum number of registers supported by the target.
static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
(X86::K6_K7 + 1 == X86::TMMCFG) &&
- (X86::TMM6_TMM7 + 1 == X86::R16) &&
+ (X86::TMM7 + 1 == X86::R16) &&
(X86::R31WH + 1 == X86::NUM_TARGET_REGS),
"Register number may be incorrect");
@@ -694,8 +690,7 @@ bool X86RegisterInfo::isFixedRegister(const MachineFunction &MF,
}
bool X86RegisterInfo::isTileRegisterClass(const TargetRegisterClass *RC) const {
- return RC->getID() == X86::TILERegClassID ||
- RC->getID() == X86::TILEPAIRRegClassID;
+ return RC->getID() == X86::TILERegClassID;
}
void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
@@ -1062,17 +1057,9 @@ static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
case X86::PTDPFP16PSV:
case X86::PTCMMIMFP16PSV:
case X86::PTCMMRLFP16PSV:
- case X86::PTTRANSPOSEDV:
- case X86::PTTDPBF16PSV:
- case X86::PTTDPFP16PSV:
- case X86::PTTCMMIMFP16PSV:
- case X86::PTTCMMRLFP16PSV:
- case X86::PTCONJTCMMIMFP16PSV:
- case X86::PTCONJTFP16V:
case X86::PTILELOADDRSV:
case X86::PTILELOADDRST1V:
case X86::PTMMULTF32PSV:
- case X86::PTTMMULTF32PSV:
case X86::PTDPBF8PSV:
case X86::PTDPBHF8PSV:
case X86::PTDPHBF8PSV:
@@ -1083,56 +1070,7 @@ static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
VRM->assignVirt2Shape(VirtReg, Shape);
return Shape;
}
- case X86::PT2RPNTLVWZ0V:
- case X86::PT2RPNTLVWZ0T1V:
- case X86::PT2RPNTLVWZ1V:
- case X86::PT2RPNTLVWZ1T1V:
- case X86::PT2RPNTLVWZ0RSV:
- case X86::PT2RPNTLVWZ0RST1V:
- case X86::PT2RPNTLVWZ1RSV:
- case X86::PT2RPNTLVWZ1RST1V: {
- MachineOperand &MO1 = MI->getOperand(1);
- MachineOperand &MO2 = MI->getOperand(2);
- MachineOperand &MO3 = MI->getOperand(3);
- ShapeT Shape({&MO1, &MO2, &MO1, &MO3}, MRI);
- VRM->assignVirt2Shape(VirtReg, Shape);
- return Shape;
- }
- }
-}
-
-static bool canHintShape(ShapeT &PhysShape, ShapeT &VirtShape) {
- unsigned PhysShapeNum = PhysShape.getShapeNum();
- unsigned VirtShapeNum = VirtShape.getShapeNum();
-
- if (PhysShapeNum < VirtShapeNum)
- return false;
-
- if (PhysShapeNum == VirtShapeNum) {
- if (PhysShapeNum == 1)
- return PhysShape == VirtShape;
-
- for (unsigned I = 0; I < PhysShapeNum; I++) {
- ShapeT PShape(PhysShape.getRow(I), PhysShape.getCol(I));
- ShapeT VShape(VirtShape.getRow(I), VirtShape.getCol(I));
- if (VShape != PShape)
- return false;
- }
- return true;
- }
-
- // Hint subreg of mult-tile reg to single tile reg.
- if (VirtShapeNum == 1) {
- for (unsigned I = 0; I < PhysShapeNum; I++) {
- ShapeT PShape(PhysShape.getRow(I), PhysShape.getCol(I));
- if (VirtShape == PShape)
- return true;
- }
}
-
- // Note: Currently we have no requirement for case of
- // (VirtShapeNum > 1 and PhysShapeNum > VirtShapeNum)
- return false;
}
bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
@@ -1153,7 +1091,7 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
if (!VRM)
return BaseImplRetVal;
- if (ID != X86::TILERegClassID && ID != X86::TILEPAIRRegClassID) {
+ if (ID != X86::TILERegClassID) {
if (DisableRegAllocNDDHints || !ST.hasNDD() ||
!TRI.isGeneralPurposeRegisterClass(&RC))
return BaseImplRetVal;
@@ -1204,7 +1142,7 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
return;
}
ShapeT PhysShape = getTileShape(VReg, const_cast<VirtRegMap *>(VRM), MRI);
- if (canHintShape(PhysShape, VirtShape))
+ if (PhysShape == VirtShape)
Hints.push_back(PhysReg);
};
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 99b7910131dc5..1806561e9d7cf 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -29,9 +29,7 @@ let Namespace = "X86" in {
def sub_xmm : SubRegIndex<128>;
def sub_ymm : SubRegIndex<256>;
def sub_mask_0 : SubRegIndex<-1>;
- def sub_mask_1 : SubRegIndex<-1, -1>;
- def sub_t0 : SubRegIndex<8192>;
- def sub_t1 : SubRegIndex<8192, 8192>;
+ def sub_mask_1 : SubRegIndex<-1, -1>;
}
//===----------------------------------------------------------------------===//
@@ -431,11 +429,7 @@ def TMM3: X86Reg<"tmm3", 3>;
def TMM4: X86Reg<"tmm4", 4>;
def TMM5: X86Reg<"tmm5", 5>;
def TMM6: X86Reg<"tmm6", 6>;
-def TMM7: X86Reg<"tmm7", 7>;
-// TMM register pairs
-def TPAIRS : RegisterTuples<[sub_t0, sub_t1],
- [(add TMM0, TMM2, TMM4, TMM6),
- (add TMM1, TMM3, TMM5, TMM7)]>;
+def TMM7 : X86Reg<"tmm7", 7>;
}
// Floating point stack registers. These don't map one-to-one to the FP
@@ -862,9 +856,6 @@ def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
let CopyCost = -1 in // Don't allow copying of tile registers
def TILE : RegisterClass<"X86", [x86amx], 8192,
(sequence "TMM%u", 0, 7)> {let Size = 8192;}
-// Need check alignment 3rd operand size=1024*2*8
-let isAllocatable = 1 in
-def TILEPAIR : RegisterClass<"X86", [untyped], 512, (add TPAIRS)> {let Size = 16384;}
//===----------------------------------------------------------------------===//
// Register categories.
diff --git a/llvm/lib/Target/X86/X86TileConfig.cpp b/llvm/lib/Target/X86/X86TileConfig.cpp
index 17a44dde6480f..09ef8fbc12de9 100644
--- a/llvm/lib/Target/X86/X86TileConfig.cpp
+++ b/llvm/lib/Target/X86/X86TileConfig.cpp
@@ -74,63 +74,6 @@ INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
INITIALIZE_PASS_END(X86TileConfig, DEBUG_TYPE, "Tile Register Configure", false,
false)
-unsigned getAMXRegNum(MachineRegisterInfo *MRI, Register Reg) {
- if (Reg.isVirtual()) {
- unsigned RegClassID = MRI->getRegClass(Reg)->getID();
- if (RegClassID == X86::TILERegClassID)
- return 1;
- if (RegClassID == X86::TILEPAIRRegClassID)
- return 2;
- } else {
- if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
- return 1;
- if (Reg >= X86::TMM0_TMM1 && Reg <= X86::TMM6_TMM7)
- return 2;
- }
- return 0;
-}
-
-static void collectVirtRegShapes(MachineRegisterInfo *MRI, VirtRegMap &VRM,
- Register VirtReg,
- SmallVector<ShapeT, 8> &Phys2Shapes) {
- unsigned Num = getAMXRegNum(MRI, VirtReg);
- MCRegister PhysReg = VRM.getPhys(VirtReg);
- if (!PhysReg)
- return;
-
- if (Num == 1) {
- unsigned Index = PhysReg - X86::TMM0;
- if (!Phys2Shapes[Index].isValid()) {
- ShapeT Shape = VRM.getShape(VirtReg);
- Phys2Shapes[Index] = std::move(Shape);
- return;
- }
- }
- // Split tile pair shape info to 2 single tile shape info. e.g:
- // Put TMM0_TMM1's Shape to TMM0's shape + TMM1's Shape in Phys2Shapes.
- if (Num == 2) {
- unsigned Index0 = (PhysReg - X86::TMM0_TMM1) * 2;
- unsigned Index1 = (PhysReg - X86::TMM0_TMM1) * 2 + 1;
-
- ShapeT Shape = VRM.getShape(VirtReg);
- assert(Shape.getShapeNum() == 2 && "Unexpected shape number!");
-
- if (!Phys2Shapes[Index0].isValid()) {
- ShapeT Shape0(Shape.getRow(0), Shape.getCol(0), MRI);
- Phys2Shapes[Index0] = std::move(Shape0);
- }
-
- if (!Phys2Shapes[Index1].isValid()) {
- ShapeT Shape1(Shape.getRow(1), Shape.getCol(1), MRI);
- Phys2Shapes[Index1] = std::move(Shape1);
- }
- }
-}
-
-static bool isAMXRegClass(MachineRegisterInfo *MRI, Register Reg) {
- return getAMXRegNum(MRI, Reg) > 0;
-}
-
bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
// Early exit in the common case of non-AMX code.
@@ -138,7 +81,7 @@ bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
return false;
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
- const TargetRegisterInfo *TRI = ST.getRegisterInfo();
+ const X86RegisterInfo *TRI = ST.getRegisterInfo();
const TargetInstrInfo *TII = ST.getInstrInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
@@ -176,24 +119,29 @@ bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
assert(ConstMI && "Cannot find an insertion point");
unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs();
- SmallVector<ShapeT, 8> Phys2Shapes(AMXRegNum, ShapeT());
+ SmallVector<Register, 8> Phys2Virt(AMXRegNum, 0);
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register VirtReg = Register::index2VirtReg(I);
if (MRI.reg_nodbg_empty(VirtReg))
continue;
- if (!isAMXRegClass(&MRI, VirtReg))
+ if (!TRI->isTileRegisterClass(MRI.getRegClass(VirtReg)))
+ continue;
+ MCRegister PhysReg = VRM.getPhys(VirtReg);
+ if (!PhysReg)
continue;
- collectVirtRegShapes(&MRI, VRM, VirtReg, Phys2Shapes);
+ unsigned Index = PhysReg - X86::TMM0;
+ if (!Phys2Virt[Index])
+ Phys2Virt[Index] = VirtReg;
}
// Fill in the shape of each tile physical register.
for (unsigned I = 0; I < AMXRegNum; ++I) {
- ShapeT Shape = Phys2Shapes[I];
- if (!Shape.isValid())
+ if (!Phys2Virt[I])
continue;
DebugLoc DL;
bool IsRow = true;
MachineInstr *NewMI = nullptr;
+ ShapeT Shape = VRM.getShape(Phys2Virt[I]);
for (auto &R : {Shape.getRow()->getReg(), Shape.getCol()->getReg()}) {
// Here is the data format for the tile config.
// 0 palette
@@ -222,14 +170,7 @@ bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
"Cannot initialize with different shapes");
continue;
}
- if (DefMI.getOperand(1).isImm()) {
- Imm = DefMI.getOperand(1).getImm();
- } else {
- assert(DefMI.getOpcode() == X86::MOV32r0 &&
- "The opcode is assumed to be MOV32r0 if the operand is not "
- "immediate.");
- Imm = 0;
- }
+ Imm = DefMI.getOperand(1).getImm();
NewMI = addFrameReference(
BuildMI(MF.front(), ++ConstMI->getIterator(), DL,
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 0849fc7d55a32..c164762de2966 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -2192,7 +2192,6 @@ StringMap<bool> sys::getHostCPUFeatures() {
bool HasLeaf1E = MaxLevel >= 0x1e &&
!getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);
Features["amx-fp8"] = HasLeaf1E && ((EAX >> 4) & 1) && HasAMXSave;
- Features["amx-transpose"] = HasLeaf1E && ((EAX >> 5) & 1) && HasAMXSave;
Features["amx-tf32"] = HasLeaf1E && ((EAX >> 6) & 1) && HasAMXSave;
Features["amx-avx512"] = HasLeaf1E && ((EAX >> 7) & 1) && HasAMXSave;
Features["amx-movrs"] = HasLeaf1E && ((EAX >> 8) & 1) && HasAMXSave;
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index b13c795c1649c..adbcc610f669a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -143,7 +143,7 @@ constexpr FeatureBitset FeaturesDiamondRapids =
FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
FeaturePPX | FeatureNDD | FeatureNF | FeatureMOVRS | FeatureAMX_MOVRS |
- FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 | FeatureAMX_TRANSPOSE;
+ FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32;
// Intel Atom processors.
// Bonnell has feature parity with Core2 and adds MOVBE.
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index d3c0da9862245..000c67efb1de7 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -1439,11 +1439,8 @@ Key: PSUBWrm: [ 0.00 0.00 ]
Key: PSUBWrr: [ 0.00 0.00 ]
Key: PSWAPDrm: [ 0.00 0.00 ]
Key: PSWAPDrr: [ 0.00 0.00 ]
-Key: PT: [ 0.00 0.00 ]
Key: PTCMMIMFP: [ 0.00 0.00 ]
Key: PTCMMRLFP: [ 0.00 0.00 ]
-Key: PTCONJTCMMIMFP: [ 0.00 0.00 ]
-Key: PTCONJTFP: [ 0.00 0.00 ]
Key: PTCVTROWD: [ 0.00 0.00 ]
Key: PTCVTROWPS: [ 0.00 0.00 ]
Key: PTDPBF: [ 0.00 0.00 ]
@@ -1471,20 +1468,11 @@ Key: PTILEMOVROWrre: [ 0.00 0.00 ]
Key: PTILEMOVROWrreV: [ 0.00 0.00 ]
Key: PTILEMOVROWrri: [ 0.00 0.00 ]
Key: PTILEMOVROWrriV: [ 0.00 0.00 ]
-Key: PTILEPAIRLOAD: [ 0.00 0.00 ]
-Key: PTILEPAIRSTORE: [ 0.00 0.00 ]
Key: PTILESTORED: [ 0.00 0.00 ]
Key: PTILESTOREDV: [ 0.00 0.00 ]
Key: PTILEZERO: [ 0.00 0.00 ]
Key: PTILEZEROV: [ 0.00 0.00 ]
Key: PTMMULTF: [ 0.00 0.00 ]
-Key: PTTCMMIMFP: [ 0.00 0.00 ]
-Key: PTTCMMRLFP: [ 0.00 0.00 ]
-Key: PTTDPBF: [ 0.00 0.00 ]
-Key: PTTDPFP: [ 0.00 0.00 ]
-Key: PTTMMULTF: [ 0.00 0.00 ]
-Key: PTTRANSPOSED: [ 0.00 0.00 ]
-Key: PTTRANSPOSEDV: [ 0.00 0.00 ]
Key: PTWRITE: [ 0.00 0.00 ]
Key: PTWRITEm: [ 0.00 0.00 ]
Key: PTWRITEr: [ 0.00 0.00 ]
@@ -1717,8 +1705,6 @@ Key: TAILJMPm: [ 0.00 0.00 ]
Key: TAILJMPr: [ 0.00 0.00 ]
Key: TCMMIMFP: [ 0.00 0.00 ]
Key: TCMMRLFP: [ 0.00 0.00 ]
-Key: TCONJTCMMIMFP: [ 0.00 0.00 ]
-Key: TCONJTFP: [ 0.00 0.00 ]
Key: TCRETURN_HIPE: [ 0.00 0.00 ]
Key: TCRETURN_WIN: [ 0.00 0.00 ]
Key: TCRETURN_WINmi: [ 0.00 0.00 ]
@@ -1764,12 +1750,6 @@ Key: TPAUSE: [ 0.00 0.00 ]
Key: TRAP: [ 0.00 0.00 ]
Key: TST_F: [ 0.00 0.00 ]
Key: TST_Fp: [ 0.00 0.00 ]
-Key: TTCMMIMFP: [ 0.00 0.00 ]
-Key: TTCMMRLFP: [ 0.00 0.00 ]
-Key: TTDPBF: [ 0.00 0.00 ]
-Key: TTDPFP: [ 0.00 0.00 ]
-Key: TTMMULTF: [ 0.00 0.00 ]
-Key: TTRANSPOSED: [ 0.00 0.00 ]
Key: TZCNT: [ 0.00 0.00 ]
Key: TZMSK: [ 0.00 0.00 ]
Key: UBSAN_UD: [ 0.00 0.00 ]
@@ -7034,7 +7014,6 @@ Key: PhyReg_VR256: [ 0.00 0.00 ]
Key: PhyReg_VR512: [ 0.00 0.00 ]
Key: PhyReg_VR512_0_15: [ 0.00 0.00 ]
Key: PhyReg_TILE: [ 0.00 0.00 ]
-Key: PhyReg_TILEPAIR: [ 0.00 0.00 ]
Key: VirtReg_GR8: [ 0.00 0.00 ]
Key: VirtReg_GRH8: [ 0.00 0.00 ]
Key: VirtReg_GR8_NOREX2: [ 0.00 0.00 ]
@@ -7170,4 +7149,3 @@ Key: VirtReg_VR256: [ 0.00 0.00 ]
Key: VirtReg_VR512: [ 0.00 0.00 ]
Key: VirtReg_VR512_0_15: [ 0.00 0.00 ]
Key: VirtReg_TILE: [ 0.00 0.00 ]
-Key: VirtReg_TILEPAIR: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index c6e5508248b9b..bb72886f73bfd 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -1439,11 +1439,8 @@ Key: PSUBWrm: [ 0.00 0.00 ]
Key: PSUBWrr: [ 0.00 0.00 ]
Key: PSWAPDrm: [ 0.00 0.00 ]
Key: PSWAPDrr: [ 0.00 0.00 ]
-Key: PT: [ 0.00 0.00 ]
Key: PTCMMIMFP: [ 0.00 0.00 ]
Key: PTCMMRLFP: [ 0.00 0.00 ]
-Key: PTCONJTCMMIMFP: [ 0.00 0.00 ]
-Key: PTCONJTFP: [ 0.00 0.00 ]
Key: PTCVTROWD: [ 0.00 0.00 ]
Key: PTCVTROWPS: [ 0.00 0.00 ]
Key: PTDPBF: [ 0.00 0.00 ]
@@ -1471,20 +1468,11 @@ Key: PTILEMOVROWrre: [ 0.00 0.00 ]
Key: PTILEMOVROWrreV: [ 0.00 0.00 ]
Key: PTILEMOVROWrri: [ 0.00 0.00 ]
Key: PTILEMOVROWrriV: [ 0.00 0.00 ]
-Key: PTILEPAIRLOAD: [ 0.00 0.00 ]
-Key: PTILEPAIRSTORE: [ 0.00 0.00 ]
Key: PTILESTORED: [ 0.00 0.00 ]
Key: PTILESTOREDV: [ 0.00 0.00 ]
Key: PTILEZERO: [ 0.00 0.00 ]
Key: PTILEZEROV: [ 0.00 0.00 ]
Key: PTMMULTF: [ 0.00 0.00 ]
-Key: PTTCMMIMFP: [ 0.00 0.00 ]
-Key: PTTCMMRLFP: [ 0.00 0.00 ]
-Key: PTTDPBF: [ 0.00 0.00 ]
-Key: PTTDPFP: [ 0.00 0.00 ]
-Key: PTTMMULTF: [ 0.00 0.00 ]
-Key: PTTRANSPOSED: [ 0.00 0.00 ]
-Key: PTTRANSPOSEDV: [ 0.00 0.00 ]
Key: PTWRITE: [ 0.00 0.00 ]
Key: PTWRITEm: [ 0.00 0.00 ]
Key: PTWRITEr: [ 0.00 0.00 ]
@@ -1717,8 +1705,6 @@ Key: TAILJMPm: [ 0.00 0.00 ]
Key: TAILJMPr: [ 0.00 0.00 ]
Key: TCMMIMFP: [ 0.00 0.00 ]
Key: TCMMRLFP: [ 0.00 0.00 ]
-Key: TCONJTCMMIMFP: [ 0.00 0.00 ]
-Key: TCONJTFP: [ 0.00 0.00 ]
Key: TCRETURN_HIPE: [ 0.00 0.00 ]
Key: TCRETURN_WIN: [ 0.00 0.00 ]
Key: TCRETURN_WINmi: [ 0.00 0.00 ]
@@ -1764,12 +1750,6 @@ Key: TPAUSE: [ 0.00 0.00 ]
Key: TRAP: [ 0.00 0.00 ]
Key: TST_F: [ 0.00 0.00 ]
Key: TST_Fp: [ 0.00 0.00 ]
-Key: TTCMMIMFP: [ 0.00 0.00 ]
-Key: TTCMMRLFP: [ 0.00 0.00 ]
-Key: TTDPBF: [ 0.00 0.00 ]
-Key: TTDPFP: [ 0.00 0.00 ]
-Key: TTMMULTF: [ 0.00 0.00 ]
-Key: TTRANSPOSED: [ 0.00 0.00 ]
Key: TZCNT: [ 0.00 0.00 ]
Key: TZMSK: [ 0.00 0.00 ]
Key: UBSAN_UD: [ 0.00 0.00 ]
@@ -7034,7 +7014,6 @@ Key: PhyReg_VR256: [ 0.00 0.00 ]
Key: PhyReg_VR512: [ 0.00 0.00 ]
Key: PhyReg_VR512_0_15: [ 0.00 0.00 ]
Key: PhyReg_TILE: [ 0.00 0.00 ]
-Key: PhyReg_TILEPAIR: [ 0.00 0.00 ]
Key: VirtReg_GR8: [ 0.00 0.00 ]
Key: VirtReg_GRH8: [ 0.00 0.00 ]
Key: VirtReg_GR8_NOREX2: [ 0.00 0.00 ]
@@ -7170,4 +7149,3 @@ Key: VirtReg_VR256: [ 0.00 0.00 ]
Key: VirtReg_VR512: [ 0.00 0.00 ]
Key: VirtReg_VR512_0_15: [ 0.00 0.00 ]
Key: VirtReg_TILE: [ 0.00 0.00 ]
-Key: VirtReg_TILEPAIR: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/X86/amx-tf32-internal.ll b/llvm/test/CodeGen/X86/amx-tf32-internal.ll
index 6d0f3c57c08d8..caf7a1cb7bd2d 100644
--- a/llvm/test/CodeGen/X86/amx-tf32-internal.ll
+++ b/llvm/test/CodeGen/X86/amx-tf32-internal.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+avx512f, \
-; RUN: -mattr=+amx-tf32,+amx-transpose -verify-machineinstrs | FileCheck %s
+; RUN: -mattr=+amx-tf32 -verify-machineinstrs | FileCheck %s
define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
; CHECK-LABEL: test_amx:
@@ -20,7 +20,6 @@ define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
; CHECK-NEXT: tilezero %tmm1
; CHECK-NEXT: tilezero %tmm2
; CHECK-NEXT: tmmultf32ps %tmm1, %tmm0, %tmm2
-; CHECK-NEXT: ttmmultf32ps %tmm1, %tmm0, %tmm2
; CHECK-NEXT: tilestored %tmm2, (%rdi,%rdx)
; CHECK-NEXT: tilerelease
; CHECK-NEXT: vzeroupper
@@ -31,9 +30,8 @@ define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
%c = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 8)
%c1 = call x86_amx @llvm.x86.tmmultf32ps.internal(i16 8, i16 8, i16 8, x86_amx %c, x86_amx %a, x86_amx %b)
- %c2 = call x86_amx @llvm.x86.ttmmultf32ps.internal(i16 8, i16 8, i16 8, x86_amx %c1, x86_amx %a, x86_amx %b)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %pointer, i64 %stride, x86_amx %c2)
+ call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %pointer, i64 %stride, x86_amx %c1)
ret void
}
@@ -43,4 +41,3 @@ declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
declare x86_amx @llvm.x86.tmmultf32ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
-declare x86_amx @llvm.x86.ttmmultf32ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
diff --git a/llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll b/llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
index af1a7ae102975..642c1b7317f81 100644
--- a/llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-tf32,+amx-transpose -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-tf32 -verify-machineinstrs | FileCheck %s
define void @test_tmmultf32ps() {
; CHECK-LABEL: test_tmmultf32ps:
@@ -11,13 +11,3 @@ define void @test_tmmultf32ps() {
}
declare void @llvm.x86.tmmultf32ps(i8 %A, i8 %B, i8 %C)
-define void @test_ttmmultf32ps() {
-; CHECK-LABEL: test_ttmmultf32ps:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ttmmultf32ps %tmm3, %tmm2, %tmm1
-; CHECK-NEXT: retq
- call void @llvm.x86.ttmmultf32ps(i8 1, i8 2, i8 3)
- ret void
-}
-declare void @llvm.x86.ttmmultf32ps(i8 %A, i8 %B, i8 %C)
-
diff --git a/llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll b/llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
deleted file mode 100755
index 1f5758c804b2b..0000000000000
--- a/llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
+++ /dev/null
@@ -1,122 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-transpose,+amx-movrs | FileCheck %s --check-prefixes=CHECK,O0
-; RUN: llc < %s -O2 -mtriple=x86_64-unknown-unknown -mattr=+amx-transpose,+amx-movrs | FileCheck %s --check-prefixes=CHECK,O2
-; RUN: llc < %s -O2 -mtriple=x86_64-unknown-unknown -mattr=+amx-transpose,+amx-movrs,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
-
-define void @test_amx(i64 %stride, i8* %addr1) #0 {
-; CHECK-LABEL: test_amx:
-; CHECK: # %bb.0:
-; CHECK-NEXT: t2rpntlvwz0rs (%rsi,%rdi), %tmm0
-; CHECK-NEXT: t2rpntlvwz0rst1 (%rsi,%rdi), %tmm2
-; CHECK-NEXT: t2rpntlvwz1rs (%rsi,%rdi), %tmm0
-; CHECK-NEXT: t2rpntlvwz1rst1 (%rsi,%rdi), %tmm2
-; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_amx:
-; EGPR: # %bb.0:
-; EGPR-NEXT: t2rpntlvwz0rs (%rsi,%rdi), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x78,0xf8,0x04,0x3e]
-; EGPR-NEXT: t2rpntlvwz0rst1 (%rsi,%rdi), %tmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x78,0xf9,0x14,0x3e]
-; EGPR-NEXT: t2rpntlvwz1rs (%rsi,%rdi), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x79,0xf8,0x04,0x3e]
-; EGPR-NEXT: t2rpntlvwz1rst1 (%rsi,%rdi), %tmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x79,0xf9,0x14,0x3e]
-; EGPR-NEXT: retq # encoding: [0xc3]
- call void @llvm.x86.t2rpntlvwz0rs(i8 1, i8* %addr1, i64 %stride)
- call void @llvm.x86.t2rpntlvwz0rst1(i8 2, i8* %addr1, i64 %stride)
- call void @llvm.x86.t2rpntlvwz1rs(i8 1, i8* %addr1, i64 %stride)
- call void @llvm.x86.t2rpntlvwz1rst1(i8 2, i8* %addr1, i64 %stride)
- ret void
-}
-declare void @llvm.x86.t2rpntlvwz0rs(i8 , i8* , i64 )
-declare void @llvm.x86.t2rpntlvwz0rst1(i8 , i8* , i64 )
-declare void @llvm.x86.t2rpntlvwz1rs(i8 , i8* , i64 )
-declare void @llvm.x86.t2rpntlvwz1rst1(i8 , i8* , i64 )
-
-define void @test_amx2(i8* %base, i64 %stride) #0 {
-; O0-LABEL: test_amx2:
-; O0: # %bb.0:
-; O0-NEXT: xorps %xmm0, %xmm0
-; O0-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movb $1, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw $8, %ax
-; O0-NEXT: # implicit-def: $al
-; O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; O0-NEXT: # implicit-def: $al
-; O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; O0-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
-; O0-NEXT: t2rpntlvwz0rst1 (%rdi,%rsi), %tmm4
-; O0-NEXT: movw $8, %ax
-; O0-NEXT: # implicit-def: $al
-; O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; O0-NEXT: # implicit-def: $al
-; O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; O0-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
-; O0-NEXT: t2rpntlvwz1rs (%rdi,%rsi), %tmm4
-; O0-NEXT: movw $8, %ax
-; O0-NEXT: # implicit-def: $al
-; O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; O0-NEXT: # implicit-def: $al
-; O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
-; O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
-; O0-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
-; O0-NEXT: t2rpntlvwz1rst1 (%rdi,%rsi), %tmm4
-; O0-NEXT: tilerelease
-; O0-NEXT: retq
-;
-; O2-LABEL: test_amx2:
-; O2: # %bb.0:
-; O2-NEXT: xorps %xmm0, %xmm0
-; O2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movb $1, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; O2-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; O2-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
-; O2-NEXT: movw $8, %ax
-; O2-NEXT: t2rpntlvwz0rs (%rdi,%rsi), %tmm4
-; O2-NEXT: t2rpntlvwz0rst1 (%rdi,%rsi), %tmm4
-; O2-NEXT: t2rpntlvwz1rs (%rdi,%rsi), %tmm4
-; O2-NEXT: t2rpntlvwz1rst1 (%rdi,%rsi), %tmm4
-; O2-NEXT: tilerelease
-; O2-NEXT: retq
-;
-; EGPR-LABEL: test_amx2:
-; EGPR: # %bb.0:
-; EGPR-NEXT: xorps %xmm0, %xmm0 # encoding: [0x0f,0x57,0xc0]
-; EGPR-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp) # encoding: [0x0f,0x11,0x44,0x24,0xc0]
-; EGPR-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp) # encoding: [0x0f,0x11,0x44,0x24,0xd0]
-; EGPR-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp) # encoding: [0x0f,0x11,0x44,0x24,0xe0]
-; EGPR-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp) # encoding: [0x0f,0x11,0x44,0x24,0xf0]
-; EGPR-NEXT: movb $1, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xc0,0x01]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xf4,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0xd8,0x08,0x00]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xf5,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0xda,0x08,0x00]
-; EGPR-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x44,0x24,0xc0]
-; EGPR-NEXT: movw $8, %ax # encoding: [0x66,0xb8,0x08,0x00]
-; EGPR-NEXT: t2rpntlvwz0rs (%rdi,%rsi), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x78,0xf8,0x24,0x37]
-; EGPR-NEXT: t2rpntlvwz0rst1 (%rdi,%rsi), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x78,0xf9,0x24,0x37]
-; EGPR-NEXT: t2rpntlvwz1rs (%rdi,%rsi), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x79,0xf8,0x24,0x37]
-; EGPR-NEXT: t2rpntlvwz1rst1 (%rdi,%rsi), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe5,0x79,0xf9,0x24,0x37]
-; EGPR-NEXT: tilerelease # encoding: [0xc4,0xe2,0x78,0x49,0xc0]
-; EGPR-NEXT: retq # encoding: [0xc3]
- call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rs.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rst1.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rs.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rst1.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- ret void
-}
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rs.internal(i16, i16, i16, i8*, i64)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0rst1.internal(i16, i16, i16, i8*, i64)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rs.internal(i16, i16, i16, i8*, i64)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1rst1.internal(i16, i16, i16, i8*, i64)
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_O2_to_O0.ll b/llvm/test/CodeGen/X86/amx_tile_pair_O2_to_O0.ll
deleted file mode 100644
index 4f41410010302..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_O2_to_O0.ll
+++ /dev/null
@@ -1,136 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
-; RUN: -mattr=+amx-transpose -verify-machineinstrs | FileCheck %s
-
- at buf = dso_local global [2048 x i8] zeroinitializer, align 16
- at buf2 = dso_local global [2048 x i8] zeroinitializer, align 16
-
-define dso_local void @test_tile_2rpntlvwz0(i16 noundef signext %row, i16 noundef signext %col0, i16 noundef signext %col1) local_unnamed_addr #0 {
-; CHECK-LABEL: test_tile_2rpntlvwz0:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rbp
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset %rbp, -16
-; CHECK-NEXT: movq %rsp, %rbp
-; CHECK-NEXT: .cfi_def_cfa_register %rbp
-; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: andq $-1024, %rsp # imm = 0xFC00
-; CHECK-NEXT: subq $8192, %rsp # imm = 0x2000
-; CHECK-NEXT: .cfi_offset %rbx, -24
-; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # kill: def $dx killed $dx killed $edx
-; CHECK-NEXT: movw %si, %cx
-; CHECK-NEXT: movw %di, %ax
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %dx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %dx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %cx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $cl
-; CHECK-NEXT: movb %cl, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %dx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %cx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %cx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %cx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: # implicit-def: $al
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw %dx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movl $buf, %esi
-; CHECK-NEXT: movl $32, %edi
-; CHECK-NEXT: t2rpntlvwz0 (%rsi,%rdi), %tmm4
-; CHECK-NEXT: movabsq $64, %rbx
-; CHECK-NEXT: tilestored %tmm5, (%rsp,%rbx) # 1024-byte Folded Spill
-; CHECK-NEXT: tileloadd (%rsp,%rbx), %tmm0 # 1024-byte Folded Reload
-; CHECK-NEXT: movabsq $64, %rbx
-; CHECK-NEXT: tilestored %tmm4, 1024(%rsp,%rbx) # 1024-byte Folded Spill
-; CHECK-NEXT: tileloadd 1024(%rsp,%rbx), %tmm1 # 1024-byte Folded Reload
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tilestored %tmm1, (%rsi,%rdi)
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tilestored %tmm0, (%rsi,%rdi)
-; CHECK-NEXT: tilezero %tmm0
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tilestored %tmm0, (%rsi,%rdi)
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tileloadd (%rsi,%rdi), %tmm1
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tileloadd (%rsi,%rdi), %tmm2
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tileloadd (%rsi,%rdi), %tmm0
-; CHECK-NEXT: tdpbssd %tmm2, %tmm1, %tmm0
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tilestored %tmm0, (%rsi,%rdi)
-; CHECK-NEXT: movl $64, %edi
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
-; CHECK-NEXT: tileloadd (%rsi,%rdi), %tmm0
-; CHECK-NEXT: movl $buf2, %edx
-; CHECK-NEXT: movl $32, %esi
-; CHECK-NEXT: tilestored %tmm0, (%rdx,%rsi)
-; CHECK-NEXT: leaq -8(%rbp), %rsp
-; CHECK-NEXT: popq %rbx
-; CHECK-NEXT: popq %rbp
-; CHECK-NEXT: .cfi_def_cfa %rsp, 8
-; CHECK-NEXT: tilerelease
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
-entry:
- %0 = tail call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 %row, i16 %col0, i16 %col1, ptr @buf, i64 32) #3
- %1 = extractvalue { x86_amx, x86_amx } %0, 0
- %2 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %1) #3
- %3 = extractvalue { x86_amx, x86_amx } %0, 1
- %4 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %3) #3
- %5 = tail call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 %col0) #3
- %6 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %5) #3
- %7 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %6) #3
- %8 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %2) #3
- %9 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %4) #3
- %10 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %row, i16 %col1, i16 %col0, x86_amx %7, x86_amx %8, x86_amx %9) #3
- %11 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %10) #3
- %12 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %11) #3
- tail call void @llvm.x86.tilestored64.internal(i16 %row, i16 %col0, ptr @buf2, i64 32, x86_amx %12) #3
- ret void
-}
-
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16, i16, i16, ptr, i64) #1
-
-declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx) #2
-
-declare x86_amx @llvm.x86.tilezero.internal(i16, i16) #3
-
-declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx) #3
-
-declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>) #2
-
-declare void @llvm.x86.tilestored64.internal(i16, i16, ptr, i64, x86_amx) #4
-
-attributes #0 = { nounwind uwtable "target-cpu"="x86-64" "target-features"="+amx-bf16,+amx-int8,+amx-tile,+amx-transpose" }
-attributes #1 = { argmemonly nofree nounwind readonly }
-attributes #2 = { nofree nosync nounwind readnone }
-attributes #3 = { nounwind }
-attributes #4 = { argmemonly nounwind writeonly }
-
-!llvm.module.flags = !{!0, !1, !2}
-
-!0 = !{i32 1, !"wchar_size", i32 4}
-!1 = !{i32 7, !"uwtable", i32 2}
-!2 = !{i32 7, !"frame-pointer", i32 2}
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_configure_O0.mir b/llvm/test/CodeGen/X86/amx_tile_pair_configure_O0.mir
deleted file mode 100644
index ab12ab3a4f13d..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_configure_O0.mir
+++ /dev/null
@@ -1,165 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
-# RUN: -mattr=+amx-transpose -run-pass=fasttileconfig -o - %s | FileCheck %s
-
----
-name: test_tile_2rpntlvwz0
-alignment: 16
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHContTarget: false
-hasEHScopes: false
-hasEHFunclets: false
-failsVerification: false
-tracksDebugUserValues: false
-registers: []
-liveins:
- - { reg: '$edi', virtual-reg: '' }
- - { reg: '$esi', virtual-reg: '' }
- - { reg: '$edx', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1024
- adjustsStack: false
- hasCalls: true
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- localFrameSize: 0
- savePoint: []
- restorePoint: []
-fixedStack: []
-stack:
- - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 4, name: '', type: default, offset: 0, size: 64, alignment: 4,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 5, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 6, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 7, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- amxProgModel: ManagedRA
-body: |
- bb.0.entry:
- liveins: $rdi, $rsi, $rdx, $rax
-
- ; CHECK-LABEL: name: test_tile_2rpntlvwz0
- ; CHECK: liveins: $rdi, $rsi, $rdx, $rax
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $zmm0 = AVX512_512_SET0
- ; CHECK-NEXT: VMOVUPSZmr %stack.4, 1, $noreg, 0, $noreg, killed renamable $zmm0 :: (store (s512) into %stack.4, align 4)
- ; CHECK-NEXT: MOV8mi %stack.4, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.4, align 4)
- ; CHECK-NEXT: renamable $rcx = MOV32ri64 64
- ; CHECK-NEXT: MOV64mr %stack.7, 1, $noreg, 0, $noreg, $rcx :: (store (s64) into %stack.7)
- ; CHECK-NEXT: renamable $cx = MOV16ri 64
- ; CHECK-NEXT: MOV16mr %stack.5, 1, $noreg, 0, $noreg, $cx :: (store (s16) into %stack.5)
- ; CHECK-NEXT: renamable $cx = MOV16ri 16
- ; CHECK-NEXT: renamable $r8w = MOV16ri 16
- ; CHECK-NEXT: MOV16mr %stack.6, 1, $noreg, 0, $noreg, $r8w :: (store (s16) into %stack.6)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 48, $noreg, $al :: (store (s512) into %stack.4 + 48, align 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 16, $noreg, $cx :: (store (s512) into %stack.4 + 16, align 4)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 50, $noreg, $al :: (store (s512) into %stack.4 + 50, align 2, basealign 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 20, $noreg, $cx :: (store (s512) into %stack.4 + 20, align 4)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 49, $noreg, $al :: (store (s512) into %stack.4 + 49, align 1, basealign 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 18, $noreg, $di :: (store (s512) into %stack.4 + 18, align 2, basealign 4)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 48, $noreg, $al :: (store (s512) into %stack.4 + 48, align 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 16, $noreg, $cx :: (store (s512) into %stack.4 + 16, align 4)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 48, $noreg, $al :: (store (s512) into %stack.4 + 48, align 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 16, $noreg, $cx :: (store (s512) into %stack.4 + 16, align 4)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 52, $noreg, $al :: (store (s512) into %stack.4 + 52, align 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 24, $noreg, $cx :: (store (s512) into %stack.4 + 24, align 4)
- ; CHECK-NEXT: $al = IMPLICIT_DEF
- ; CHECK-NEXT: MOV8mr %stack.4, 1, $noreg, 53, $noreg, $al :: (store (s512) into %stack.4 + 53, align 1, basealign 4)
- ; CHECK-NEXT: MOV16mr %stack.4, 1, $noreg, 26, $noreg, $di :: (store (s512) into %stack.4 + 26, align 2, basealign 4)
- ; CHECK-NEXT: PLDTILECFGV %stack.4, 1, $noreg, 0, $noreg, implicit-def dead $tmm0, implicit-def dead $tmm1, implicit-def dead $tmm2, implicit-def dead $tmm3, implicit-def dead $tmm4, implicit-def dead $tmm5, implicit-def dead $tmm6, implicit-def dead $tmm7 :: (load (s512) from %stack.4, align 4)
- ; CHECK-NEXT: renamable $r9 = COPY $rsi
- ; CHECK-NEXT: $rsi = MOV64rm %stack.7, 1, $noreg, 0, $noreg :: (load (s64) from %stack.7)
- ; CHECK-NEXT: renamable $r8 = COPY $rdi
- ; CHECK-NEXT: $di = MOV16rm %stack.6, 1, $noreg, 0, $noreg :: (load (s16) from %stack.6)
- ; CHECK-NEXT: renamable $r10 = COPY $rax
- ; CHECK-NEXT: $ax = MOV16rm %stack.5, 1, $noreg, 0, $noreg :: (load (s16) from %stack.5)
- ; CHECK-NEXT: renamable $tmm4_tmm5 = PT2RPNTLVWZ0V renamable $ax, renamable $cx, renamable $di, renamable $rdx, 1, killed renamable $r10, 0, $noreg
- ; CHECK-NEXT: renamable $tmm0 = COPY renamable $tmm5
- ; CHECK-NEXT: renamable $tmm1 = COPY renamable $tmm4, implicit killed $tmm4_tmm5
- ; CHECK-NEXT: PTILESTOREDV renamable $ax, renamable $cx, renamable $r9, 1, renamable $rsi, 0, $noreg, killed renamable $tmm1
- ; CHECK-NEXT: PTILESTOREDV renamable $ax, renamable $di, renamable $r8, 1, renamable $rsi, 0, $noreg, killed renamable $tmm0
- ; CHECK-NEXT: renamable $tmm0 = PTILEZEROV renamable $ax, renamable $cx
- ; CHECK-NEXT: PTILESTOREDV renamable $ax, renamable $cx, renamable $rdx, 1, renamable $rsi, 0, $noreg, killed renamable $tmm0
- ; CHECK-NEXT: renamable $tmm0 = PTILELOADDV renamable $ax, renamable $cx, killed renamable $r9, 1, renamable $rsi, 0, $noreg
- ; CHECK-NEXT: renamable $tmm1 = PTILELOADDV renamable $ax, renamable $di, killed renamable $r8, 1, renamable $rsi, 0, $noreg
- ; CHECK-NEXT: renamable $tmm2 = PTILELOADDV renamable $ax, renamable $cx, renamable $rdx, 1, renamable $rsi, 0, $noreg
- ; CHECK-NEXT: renamable $tmm0 = PTDPBSSDV renamable $ax, renamable $cx, killed renamable $di, renamable $tmm0, killed renamable $tmm1, killed renamable $tmm2
- ; CHECK-NEXT: PTILESTOREDV killed renamable $ax, killed renamable $cx, killed renamable $rdx, 1, killed renamable $rsi, 0, $noreg, killed renamable $tmm0
- renamable $zmm0 = AVX512_512_SET0
- VMOVUPSZmr %stack.4, 1, $noreg, 0, $noreg, killed renamable $zmm0 :: (store (s512) into %stack.4, align 4)
- MOV8mi %stack.4, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.4, align 4)
- renamable $rcx = MOV32ri64 64
- MOV64mr %stack.7, 1, $noreg, 0, $noreg, $rcx :: (store (s64) into %stack.7)
- renamable $cx = MOV16ri 64
- MOV16mr %stack.5, 1, $noreg, 0, $noreg, $cx :: (store (s16) into %stack.5)
- renamable $cx = MOV16ri 16
- renamable $r8w = MOV16ri 16
- MOV16mr %stack.6, 1, $noreg, 0, $noreg, $r8w :: (store (s16) into %stack.6)
- PLDTILECFGV %stack.4, 1, $noreg, 0, $noreg, implicit-def dead $tmm0, implicit-def dead $tmm1, implicit-def dead $tmm2, implicit-def dead $tmm3, implicit-def dead $tmm4, implicit-def dead $tmm5, implicit-def dead $tmm6, implicit-def dead $tmm7 :: (load (s512) from %stack.4, align 4)
- renamable $r9 = COPY $rsi
- $rsi = MOV64rm %stack.7, 1, $noreg, 0, $noreg :: (load (s64) from %stack.7)
- renamable $r8 = COPY $rdi
- $di = MOV16rm %stack.6, 1, $noreg, 0, $noreg :: (load (s16) from %stack.6)
- renamable $r10 = COPY $rax
- $ax = MOV16rm %stack.5, 1, $noreg, 0, $noreg :: (load (s16) from %stack.5)
- renamable $tmm4_tmm5 = PT2RPNTLVWZ0V renamable $ax, renamable $cx, renamable $di, renamable $rdx, 1, killed renamable $r10, 0, $noreg
- renamable $tmm0 = COPY renamable $tmm5
- renamable $tmm1 = COPY renamable $tmm4, implicit killed $tmm4_tmm5
- PTILESTOREDV renamable $ax, renamable $cx, renamable $r9, 1, renamable $rsi, 0, $noreg, killed renamable $tmm1
- PTILESTOREDV renamable $ax, renamable $di, renamable $r8, 1, renamable $rsi, 0, $noreg, killed renamable $tmm0
- renamable $tmm0 = PTILEZEROV renamable $ax, renamable $cx
- PTILESTOREDV renamable $ax, renamable $cx, renamable $rdx, 1, renamable $rsi, 0, $noreg, killed renamable $tmm0
- renamable $tmm0 = PTILELOADDV renamable $ax, renamable $cx, killed renamable $r9, 1, renamable $rsi, 0, $noreg
- renamable $tmm1 = PTILELOADDV renamable $ax, renamable $di, killed renamable $r8, 1, renamable $rsi, 0, $noreg
- renamable $tmm2 = PTILELOADDV renamable $ax, renamable $cx, renamable $rdx, 1, renamable $rsi, 0, $noreg
- renamable $tmm0 = PTDPBSSDV renamable $ax, renamable $cx, killed renamable $di, renamable $tmm0, killed renamable $tmm1, killed renamable $tmm2
- PTILESTOREDV killed renamable $ax, killed renamable $cx, killed renamable $rdx, 1, killed renamable $rsi, 0, $noreg, killed renamable $tmm0
-...
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_configure_O2.mir b/llvm/test/CodeGen/X86/amx_tile_pair_configure_O2.mir
deleted file mode 100644
index c7d241f8a98b6..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_configure_O2.mir
+++ /dev/null
@@ -1,153 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O2 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
-# RUN: -mattr=+amx-transpose -run-pass=greedy,tileconfig -o - %s | FileCheck %s
-
---- |
- @buf = dso_local global [2048 x i8] zeroinitializer, align 16
- @buf2 = dso_local global [2048 x i8] zeroinitializer, align 16
-
- define dso_local void @test_tile_2rpntlvwz0(i16 noundef signext %row, i16 noundef signext %col0, i16 noundef signext %col1) local_unnamed_addr #0 {
- entry:
- %0 = tail call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 %row, i16 %col0, i16 %col1, i8* getelementptr inbounds ([2048 x i8], [2048 x i8]* @buf, i64 0, i64 0), i64 32) #5
- %1 = extractvalue { x86_amx, x86_amx } %0, 0
- %2 = extractvalue { x86_amx, x86_amx } %0, 1
- %3 = tail call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 %col0) #5
- %4 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %row, i16 %col1, i16 %col0, x86_amx %3, x86_amx %1, x86_amx %2) #5
- tail call void @llvm.x86.tilestored64.internal(i16 %row, i16 %col0, i8* getelementptr inbounds ([2048 x i8], [2048 x i8]* @buf2, i64 0, i64 0), i64 32, x86_amx %4) #5
- ret void
- }
-
- declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16, i16, i16, i8*, i64) #1
-
- declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx) #2
-
- declare x86_amx @llvm.x86.tilezero.internal(i16, i16) #3
-
- declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx) #3
-
- declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>) #2
-
- declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx) #4
-
- attributes #0 = { nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="8192" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+amx-bf16,+amx-int8,+amx-tile,+amx-transpose,+avx,+avx2,+avx512f,+crc32,+cx8,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+amx-tile,+amx-bf16,+avx512f,+amx-transpose" "tune-cpu"="generic" }
- attributes #1 = { argmemonly nounwind readonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #2 = { nounwind readnone "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #3 = { nounwind "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #4 = { argmemonly nounwind writeonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #5 = { nounwind }
-
-...
----
-name: test_tile_2rpntlvwz0
-alignment: 16
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHContTarget: false
-hasEHScopes: false
-hasEHFunclets: false
-failsVerification: false
-tracksDebugUserValues: false
-registers:
- - { id: 0, class: gr32, preferred-register: '' }
- - { id: 1, class: gr32, preferred-register: '' }
- - { id: 2, class: gr32, preferred-register: '' }
- - { id: 3, class: gr16, preferred-register: '' }
- - { id: 4, class: gr16, preferred-register: '' }
- - { id: 5, class: gr16, preferred-register: '' }
- - { id: 6, class: gr64, preferred-register: '' }
- - { id: 7, class: gr64_nosp, preferred-register: '' }
- - { id: 8, class: tilepair, preferred-register: '' }
- - { id: 9, class: tile, preferred-register: '' }
- - { id: 10, class: tile, preferred-register: '' }
- - { id: 11, class: tile, preferred-register: '' }
- - { id: 12, class: tile, preferred-register: '' }
- - { id: 13, class: gr64, preferred-register: '' }
- - { id: 14, class: vr512, preferred-register: '' }
-liveins:
- - { reg: '$edi', virtual-reg: '%0' }
- - { reg: '$esi', virtual-reg: '%1' }
- - { reg: '$edx', virtual-reg: '%2' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 4
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- localFrameSize: 0
- savePoint: []
- restorePoint: []
-fixedStack: []
-stack:
- - { id: 0, name: '', type: default, offset: 0, size: 64, alignment: 4,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- amxProgModel: ManagedRA
-body: |
- bb.0.entry:
- liveins: $edi, $esi, $edx
-
-
- ; CHECK-LABEL: name: test_tile_2rpntlvwz0
- ; CHECK: liveins: $edi, $esi, $edx
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK-NEXT: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET0
- ; CHECK-NEXT: VMOVUPSZmr %stack.0, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.0, align 4)
- ; CHECK-NEXT: MOV8mi %stack.0, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.0, align 4)
- ; CHECK-NEXT: MOV16mr %stack.0, 1, $noreg, 26, $noreg, [[COPY]].sub_16bit :: (store (s512) into %stack.0 + 26, align 2, basealign 4)
- ; CHECK-NEXT: MOV8mr %stack.0, 1, $noreg, 53, $noreg, [[COPY2]].sub_8bit :: (store (s512) into %stack.0 + 53, align 1, basealign 4)
- ; CHECK-NEXT: MOV16mr %stack.0, 1, $noreg, 24, $noreg, [[COPY1]].sub_16bit :: (store (s512) into %stack.0 + 24, align 4)
- ; CHECK-NEXT: MOV8mr %stack.0, 1, $noreg, 52, $noreg, [[COPY2]].sub_8bit :: (store (s512) into %stack.0 + 52, align 4)
- ; CHECK-NEXT: MOV16mr %stack.0, 1, $noreg, 16, $noreg, [[COPY]].sub_16bit :: (store (s512) into %stack.0 + 16, align 4)
- ; CHECK-NEXT: MOV8mr %stack.0, 1, $noreg, 48, $noreg, [[COPY2]].sub_8bit :: (store (s512) into %stack.0 + 48, align 4)
- ; CHECK-NEXT: PLDTILECFGV %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $tmm0, implicit-def dead $tmm1, implicit-def dead $tmm2, implicit-def dead $tmm3, implicit-def dead $tmm4, implicit-def dead $tmm5, implicit-def dead $tmm6, implicit-def dead $tmm7 :: (load (s512) from %stack.0, align 4)
- ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64 = MOV32ri64 @buf
- ; CHECK-NEXT: [[MOV32ri64_1:%[0-9]+]]:gr64_nosp = MOV32ri64 32
- ; CHECK-NEXT: [[PT2RPNTLVWZ0V:%[0-9]+]]:tilepair = PT2RPNTLVWZ0V [[COPY2]].sub_16bit, [[COPY1]].sub_16bit, [[COPY]].sub_16bit, [[MOV32ri64_]], 1, [[MOV32ri64_1]], 0, $noreg
- ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV [[COPY2]].sub_16bit, [[COPY1]].sub_16bit
- ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTDPBSSDV [[COPY2]].sub_16bit, [[COPY]].sub_16bit, [[COPY1]].sub_16bit, [[PTILEZEROV]], [[PT2RPNTLVWZ0V]].sub_t0, [[PT2RPNTLVWZ0V]].sub_t1
- ; CHECK-NEXT: [[MOV32ri64_2:%[0-9]+]]:gr64 = MOV32ri64 @buf2
- ; CHECK-NEXT: PTILESTOREDV [[COPY2]].sub_16bit, [[COPY1]].sub_16bit, [[MOV32ri64_2]], 1, [[MOV32ri64_1]], 0, $noreg, [[PTILEZEROV]]
- ; CHECK-NEXT: RET 0
- %2:gr32 = COPY $edx
- %1:gr32 = COPY $esi
- %0:gr32 = COPY $edi
- %14:vr512 = AVX512_512_SET0
- VMOVUPSZmr %stack.0, 1, $noreg, 0, $noreg, %14 :: (store (s512) into %stack.0, align 4)
- MOV8mi %stack.0, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.0, align 4)
- PLDTILECFGV %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $tmm0, implicit-def dead $tmm1, implicit-def dead $tmm2, implicit-def dead $tmm3, implicit-def dead $tmm4, implicit-def dead $tmm5, implicit-def dead $tmm6, implicit-def dead $tmm7 :: (load (s512) from %stack.0, align 4)
- %6:gr64 = MOV32ri64 @buf
- %7:gr64_nosp = MOV32ri64 32
- %8:tilepair = PT2RPNTLVWZ0V %0.sub_16bit, %1.sub_16bit, %2.sub_16bit, %6, 1, %7, 0, $noreg
- %12:tile = PTILEZEROV %0.sub_16bit, %1.sub_16bit
- %12:tile = PTDPBSSDV %0.sub_16bit, %2.sub_16bit, %1.sub_16bit, %12, %8.sub_t0, %8.sub_t1
- %13:gr64 = MOV32ri64 @buf2
- PTILESTOREDV %0.sub_16bit, %1.sub_16bit, %13, 1, %7, 0, $noreg, %12
- RET 0
-
-...
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_copy.mir b/llvm/test/CodeGen/X86/amx_tile_pair_copy.mir
deleted file mode 100644
index 66b15aa5b3cde..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_copy.mir
+++ /dev/null
@@ -1,97 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
-# RUN: -mattr=+amx-transpose -run-pass=lowertilecopy -o - %s | FileCheck %s
-
----
-name: test_tile_2rpntlvwz0
-alignment: 16
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHContTarget: false
-hasEHScopes: false
-hasEHFunclets: false
-failsVerification: false
-tracksDebugUserValues: false
-registers: []
-liveins:
- - { reg: '$edi', virtual-reg: '' }
- - { reg: '$esi', virtual-reg: '' }
- - { reg: '$edx', virtual-reg: '' }
- - { reg: '$cx', virtual-reg: '' }
- - { reg: '$r9', virtual-reg: '' }
- - { reg: '$r10', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1024
- adjustsStack: false
- hasCalls: true
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- localFrameSize: 0
- savePoint: []
- restorePoint: []
-fixedStack: []
-stack:
- - { id: 43, name: '', type: default, offset: 0, size: 64, alignment: 4,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 68, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- amxProgModel: ManagedRA
-body: |
- bb.0.entry:
- liveins: $edi, $esi, $edx, $cx, $di, $r8w, $r11, $r10, $rbx, $r8, $r9
-
-
- ; CHECK-LABEL: name: test_tile_2rpntlvwz0
- ; CHECK: liveins: $edi, $esi, $edx, $cx, $di, $r8w, $r11, $r10, $rbx, $r8, $r9
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: PLDTILECFGV %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $tmm0, implicit-def dead $tmm1, implicit-def dead $tmm2, implicit-def dead $tmm3, implicit-def dead $tmm4, implicit-def dead $tmm5, implicit-def dead $tmm6, implicit-def dead $tmm7 :: (load (s512) from %stack.0, align 4)
- ; CHECK-NEXT: renamable $tmm4_tmm5 = PT2RPNTLVWZ0V killed renamable $cx, killed renamable $di, killed renamable $r8w, killed renamable $r11, 1, killed renamable $rbx, 0, $noreg
- ; CHECK-NEXT: $rax = MOV64ri 64
- ; CHECK-NEXT: TILESTORED %stack.3, 1, $rax, 0, $noreg, $tmm5 :: (store (s8192) into %stack.3)
- ; CHECK-NEXT: $tmm0 = TILELOADD %stack.3, 1, killed $rax, 0, $noreg :: (load (s8192) from %stack.3)
- ; CHECK-NEXT: $rax = MOV64ri 64
- ; CHECK-NEXT: TILESTORED %stack.2, 1, $rax, 0, $noreg, $tmm4 :: (store (s8192) into %stack.2)
- ; CHECK-NEXT: $tmm1 = TILELOADD %stack.2, 1, killed $rax, 0, $noreg :: (load (s8192) from %stack.2)
- ; CHECK-NEXT: renamable $r8 = MOV32ri64 64
- ; CHECK-NEXT: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $r8 :: (store (s64) into %stack.1)
- ; CHECK-NEXT: renamable $di = MOV16ri 64
- ; CHECK-NEXT: renamable $cx = MOV16ri 16
- ; CHECK-NEXT: PTILESTOREDV renamable $cx, renamable $di, killed renamable $r10, 1, renamable $r8, 0, $noreg, killed renamable $tmm1
- ; CHECK-NEXT: PTILESTOREDV killed renamable $cx, killed renamable $di, killed renamable $r9, 1, renamable $r8, 0, $noreg, killed renamable $tmm0
- PLDTILECFGV %stack.43, 1, $noreg, 0, $noreg, implicit-def dead $tmm0, implicit-def dead $tmm1, implicit-def dead $tmm2, implicit-def dead $tmm3, implicit-def dead $tmm4, implicit-def dead $tmm5, implicit-def dead $tmm6, implicit-def dead $tmm7 :: (load (s512) from %stack.43, align 4)
- renamable $tmm4_tmm5 = PT2RPNTLVWZ0V killed renamable $cx, killed renamable $di, killed renamable $r8w, killed renamable $r11, 1, killed renamable $rbx, 0, $noreg
- renamable $tmm0 = COPY renamable $tmm5
- renamable $tmm1 = COPY renamable $tmm4, implicit killed $tmm4_tmm5
- renamable $r8 = MOV32ri64 64
- MOV64mr %stack.68, 1, $noreg, 0, $noreg, $r8 :: (store (s64) into %stack.68)
- renamable $di = MOV16ri 64
- renamable $cx = MOV16ri 16
- PTILESTOREDV renamable $cx, renamable $di, killed renamable $r10, 1, renamable $r8, 0, $noreg, killed renamable $tmm1
- PTILESTOREDV killed renamable $cx, killed renamable $di, killed renamable $r9, 1, renamable $r8, 0, $noreg, killed renamable $tmm0
-
-...
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O0.ll b/llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O0.ll
deleted file mode 100644
index 3549875e858a9..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O0.ll
+++ /dev/null
@@ -1,87 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
- ; RUN: opt --codegen-opt-level=0 -mtriple=x86_64 -x86-lower-amx-type %s -S | FileCheck %s
- ; RUN: opt --codegen-opt-level=0 -mtriple=x86_64 -passes=x86-lower-amx-type %s -S | FileCheck %s
-
- @buf = dso_local global [2048 x i8] zeroinitializer, align 16
-
- ; Function Attrs: noinline nounwind optnone uwtable
- define dso_local void @test_tile_2rpntlvwz0(i16 noundef signext %row, i16 noundef signext %col0, i16 noundef signext %col1, ptr %m) #0 {
-; CHECK-LABEL: @test_tile_2rpntlvwz0(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = udiv i16 [[COL1:%.*]], 4
-; CHECK-NEXT: [[TMP1:%.*]] = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 [[ROW:%.*]], i16 [[COL0:%.*]], i16 [[COL1]], ptr @buf, i64 32) #[[ATTR3:[0-9]+]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { x86_amx, x86_amx } [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[COL0]] to i64
-; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 [[COL0]], ptr [[M:%.*]], i64 [[TMP3]], x86_amx [[TMP2]])
-; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { x86_amx, x86_amx } [[TMP1]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[COL1]] to i64
-; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 [[COL1]], ptr [[M]], i64 [[TMP6]], x86_amx [[TMP5]])
-; CHECK-NEXT: [[TMP8:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 [[ROW]], i16 [[COL0]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP9:%.*]] = sext i16 [[COL0]] to i64
-; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 [[COL0]], ptr [[M]], i64 [[TMP9]], x86_amx [[TMP8]])
-; CHECK-NEXT: [[TMP11:%.*]] = sext i16 [[COL0]] to i64
-; CHECK-NEXT: [[TMP13:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 [[ROW]], i16 [[COL0]], ptr [[M]], i64 [[TMP11]])
-; CHECK-NEXT: [[TMP14:%.*]] = sext i16 [[COL1]] to i64
-; CHECK-NEXT: [[TMP16:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 [[ROW]], i16 [[COL1]], ptr [[M]], i64 [[TMP14]])
-; CHECK-NEXT: [[TMP17:%.*]] = sext i16 [[COL0]] to i64
-; CHECK-NEXT: [[TMP19:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 [[TMP0]], i16 [[COL0]], ptr [[M]], i64 [[TMP17]])
-; CHECK-NEXT: [[TMP20:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 [[ROW]], i16 [[COL0]], i16 [[COL1]], x86_amx [[TMP13]], x86_amx [[TMP16]], x86_amx [[TMP19]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP21:%.*]] = sext i16 [[COL0]] to i64
-; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 [[COL0]], ptr [[M]], i64 [[TMP21]], x86_amx [[TMP20]])
-; CHECK-NEXT: ret void
-;
- entry:
-
- %0 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 %row, i16 %col0, i16 %col1, ptr getelementptr inbounds ([2048 x i8], ptr @buf, i64 0, i64 0), i64 32) #7
- %1 = extractvalue { x86_amx, x86_amx } %0, 0
- %2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %1) #7
- store <256 x i32> %2, ptr %m, align 1024
-
- %3 = extractvalue { x86_amx, x86_amx } %0, 1
- %4 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %3) #7
- store <256 x i32> %4, ptr %m, align 1024
-
- %5 = call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 %col0) #7
- %6 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %5) #7
- store <256 x i32> %6, ptr %m, align 64
-
- %7 = load <256 x i32>, ptr %m, align 64
- %8 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %7) #7
- %9 = load <256 x i32>, ptr %m, align 64
- %10 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %9) #7
- %11 = load <256 x i32>, ptr %m, align 64
- %12 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %11) #7
-
- %13 = call x86_amx @llvm.x86.tdpbssd.internal(i16 %row, i16 %col0, i16 %col1, x86_amx %8, x86_amx %10, x86_amx %12) #7
- %14 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %13) #7
- store <256 x i32> %14, ptr %m, align 64
-
- ret void
- }
-
- ; Function Attrs: argmemonly nounwind readonly
- declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16, i16, i16, ptr, i64) #2
-
- ; Function Attrs: nounwind readnone
- declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx) #3
-
- ; Function Attrs: nounwind
- declare x86_amx @llvm.x86.tilezero.internal(i16, i16) #4
-
- ; Function Attrs: nounwind
- declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx) #4
-
- ; Function Attrs: nounwind readnone
- declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>) #3
-
- ; Function Attrs: argmemonly nounwind writeonly
- declare void @llvm.x86.tilestored64.internal(i16, i16, ptr, i64, x86_amx) #5
-
- attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="8192" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+amx-bf16,+amx-int8,+amx-tile,+amx-transpose,+avx,+avx2,+avx512f,+crc32,+cx8,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+amx-tile,+amx-bf16,+avx512f,+amx-transpose" "tune-cpu"="generic" }
- attributes #1 = { argmemonly nofree nounwind willreturn writeonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #2 = { argmemonly nounwind readonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #3 = { nounwind readnone "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #4 = { nounwind "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #5 = { argmemonly nounwind writeonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #6 = { argmemonly nofree nounwind willreturn "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #7 = { nounwind }
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O2.ll b/llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O2.ll
deleted file mode 100644
index 96966264e0515..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_lower_type_O2.ll
+++ /dev/null
@@ -1,61 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt --codegen-opt-level=2 -mtriple=x86_64 -x86-lower-amx-type %s -S | FileCheck %s
-; RUN: opt --codegen-opt-level=2 -mtriple=x86_64 -passes=x86-lower-amx-type %s -S | FileCheck %s
-
- @buf = dso_local global [2048 x i8] zeroinitializer, align 16
- @buf2 = dso_local global [2048 x i8] zeroinitializer, align 16
-
- ; Function Attrs: nounwind uwtable
- define dso_local void @test_tile_2rpntlvwz0(i16 noundef signext %row, i16 noundef signext %col0, i16 noundef signext %col1) local_unnamed_addr #0 {
-; CHECK-LABEL: @test_tile_2rpntlvwz0(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = tail call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 [[ROW:%.*]], i16 [[COL0:%.*]], i16 [[COL1:%.*]], ptr @buf, i64 32) #[[ATTR3:[0-9]+]]
-; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { x86_amx, x86_amx } [[TMP0]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { x86_amx, x86_amx } [[TMP0]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = tail call x86_amx @llvm.x86.tilezero.internal(i16 [[ROW]], i16 [[COL0]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP4:%.*]] = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 [[ROW]], i16 [[COL1]], i16 [[COL0]], x86_amx [[TMP3]], x86_amx [[TMP1]], x86_amx [[TMP2]]) #[[ATTR3]]
-; CHECK-NEXT: tail call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 [[COL0]], ptr @buf2, i64 32, x86_amx [[TMP4]]) #[[ATTR3]]
-; CHECK-NEXT: ret void
-;
- entry:
- %0 = tail call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 %row, i16 %col0, i16 %col1, ptr @buf, i64 32) #5
- %1 = extractvalue { x86_amx, x86_amx } %0, 0
- %2 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %1) #5
- %3 = extractvalue { x86_amx, x86_amx } %0, 1
- %4 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %3) #5
- %5 = tail call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 %col0) #5
- %6 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %5) #5
- %7 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %6) #5
- %8 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %2) #5
- %9 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %4) #5
- %10 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %row, i16 %col1, i16 %col0, x86_amx %7, x86_amx %8, x86_amx %9) #5
- %11 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %10) #5
- %12 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %11) #5
- tail call void @llvm.x86.tilestored64.internal(i16 %row, i16 %col0, ptr @buf2, i64 32, x86_amx %12) #5
- ret void
- }
-
- ; Function Attrs: argmemonly nounwind readonly
- declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16, i16, i16, ptr, i64) #1
-
- ; Function Attrs: nounwind readnone
- declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx) #2
-
- ; Function Attrs: nounwind
- declare x86_amx @llvm.x86.tilezero.internal(i16, i16) #3
-
- ; Function Attrs: nounwind
- declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx) #3
-
- ; Function Attrs: nounwind readnone
- declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>) #2
-
- ; Function Attrs: argmemonly nounwind writeonly
- declare void @llvm.x86.tilestored64.internal(i16, i16, ptr, i64, x86_amx) #4
-
- attributes #0 = { nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="8192" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+amx-bf16,+amx-int8,+amx-tile,+amx-transpose,+avx,+avx2,+avx512f,+crc32,+cx8,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+amx-tile,+amx-bf16,+avx512f,+amx-transpose" "tune-cpu"="generic" }
- attributes #1 = { argmemonly nounwind readonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #2 = { nounwind readnone "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #3 = { nounwind "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #4 = { argmemonly nounwind writeonly "target-features"="+amx-tile,+amx-bf16,+avx512f,+amx-transpose" }
- attributes #5 = { nounwind }
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir b/llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir
deleted file mode 100644
index 1e3b242bca96c..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir
+++ /dev/null
@@ -1,134 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
-# RUN: -mattr=+amx-transpose -run-pass=fastpretileconfig -o - %s | FileCheck %s
-
----
-name: test_tile_2rpntlvwz0
-alignment: 16
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHContTarget: false
-hasEHScopes: false
-hasEHFunclets: false
-failsVerification: false
-tracksDebugUserValues: false
-registers:
- - { id: 0, class: gr64_nosp, preferred-register: '' }
- - { id: 1, class: gr16, preferred-register: '' }
- - { id: 2, class: gr16, preferred-register: '' }
- - { id: 3, class: gr16, preferred-register: '' }
- - { id: 4, class: gr64, preferred-register: '' }
- - { id: 5, class: gr64, preferred-register: '' }
- - { id: 6, class: gr64, preferred-register: '' }
- - { id: 7, class: gr64_nosp, preferred-register: '' }
- - { id: 8, class: tilepair, preferred-register: '' }
- - { id: 9, class: tile, preferred-register: '' }
- - { id: 10, class: tile, preferred-register: '' }
- - { id: 11, class: tile, preferred-register: '' }
- - { id: 181, class: tile, preferred-register: '' }
- - { id: 183, class: tile, preferred-register: '' }
- - { id: 185, class: tile, preferred-register: '' }
- - { id: 186, class: tile, preferred-register: '' }
-liveins:
- - { reg: '$edi', virtual-reg: '%0' }
- - { reg: '$esi', virtual-reg: '%1' }
- - { reg: '$edx', virtual-reg: '%2' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1024
- adjustsStack: false
- hasCalls: true
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- localFrameSize: 0
- savePoint: []
- restorePoint: []
-fixedStack: []
-stack:
- - { id: 18, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 19, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 20, name: '', type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- - { id: 21, name: '', type: default, offset: 0, size: 8,
- alignment: 8, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- amxProgModel: ManagedRA
-body: |
- bb.0.entry:
- liveins: $rdi, $rsi, $rdx, $rax
-
- ; CHECK-LABEL: name: test_tile_2rpntlvwz0
- ; CHECK: liveins: $rdi, $rsi, $rdx, $rax
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET0
- ; CHECK-NEXT: VMOVUPSZmr %stack.4, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.4, align 4)
- ; CHECK-NEXT: MOV8mi %stack.4, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.4, align 4)
- ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 64
- ; CHECK-NEXT: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 64
- ; CHECK-NEXT: [[MOV16ri1:%[0-9]+]]:gr16 = MOV16ri 16
- ; CHECK-NEXT: [[MOV16ri2:%[0-9]+]]:gr16 = MOV16ri 16
- ; CHECK-NEXT: PLDTILECFGV %stack.4, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.4, align 4)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64_nosp = COPY $rax
- ; CHECK-NEXT: [[PT2RPNTLVWZ0V:%[0-9]+]]:tilepair = PT2RPNTLVWZ0V [[MOV16ri]], [[MOV16ri1]], [[MOV16ri2]], [[COPY2]], 1, killed [[COPY3]], 0, $noreg
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:tile = COPY [[PT2RPNTLVWZ0V]].sub_t1
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:tile = COPY [[PT2RPNTLVWZ0V]].sub_t0
- ; CHECK-NEXT: PTILESTOREDV [[MOV16ri]], [[MOV16ri1]], [[COPY]], 1, [[MOV32ri64_]], 0, $noreg, killed [[COPY5]]
- ; CHECK-NEXT: PTILESTOREDV [[MOV16ri]], [[MOV16ri2]], [[COPY1]], 1, [[MOV32ri64_]], 0, $noreg, killed [[COPY4]]
- ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV [[MOV16ri]], [[MOV16ri1]]
- ; CHECK-NEXT: PTILESTOREDV [[MOV16ri]], [[MOV16ri1]], [[COPY2]], 1, [[MOV32ri64_]], 0, $noreg, killed [[PTILEZEROV]]
- ; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri]], [[MOV16ri1]], [[COPY]], 1, [[MOV32ri64_]], 0, $noreg
- ; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri]], [[MOV16ri2]], [[COPY1]], 1, [[MOV32ri64_]], 0, $noreg
- ; CHECK-NEXT: [[PTILELOADDV2:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri]], [[MOV16ri1]], [[COPY2]], 1, [[MOV32ri64_]], 0, $noreg
- ; CHECK-NEXT: [[PTDPBSSDV:%[0-9]+]]:tile = PTDPBSSDV [[MOV16ri]], [[MOV16ri1]], [[MOV16ri2]], [[PTILELOADDV]], killed [[PTILELOADDV1]], killed [[PTILELOADDV2]]
- ; CHECK-NEXT: PTILESTOREDV killed [[MOV16ri]], killed [[MOV16ri1]], killed [[COPY2]], 1, killed [[MOV32ri64_]], 0, $noreg, killed [[PTDPBSSDV]]
- %0:gr64_nosp = MOV32ri64 64
- %1:gr16 = MOV16ri 64
- %2:gr16 = MOV16ri 16
- %3:gr16 = MOV16ri 16
- %4:gr64 = COPY $rsi
- %5:gr64 = COPY $rdi
- %6:gr64 = COPY $rdx
- %7:gr64_nosp = COPY $rax
- %8:tilepair = PT2RPNTLVWZ0V %1, %2, %3, %6, 1, killed %7, 0, $noreg
- %9:tile = COPY %8.sub_t1
- %10:tile = COPY %8.sub_t0
- PTILESTOREDV %1, %2, %4, 1, %0, 0, $noreg, killed %10
- PTILESTOREDV %1, %3, %5, 1, %0, 0, $noreg, killed %9
- %11:tile = PTILEZEROV %1, %2
- PTILESTOREDV %1, %2, %6, 1, %0, 0, $noreg, killed %11
- %181:tile = PTILELOADDV %1, %2, %4, 1, %0, 0, $noreg
- %183:tile = PTILELOADDV %1, %3, %5, 1, %0, 0, $noreg
- %185:tile = PTILELOADDV %1, %2, %6, 1, %0, 0, $noreg
- %186:tile = PTDPBSSDV %1, %2, %3, %181, killed %183, killed %185
- PTILESTOREDV killed %1, killed %2, killed %6, 1, killed %0, 0, $noreg, killed %186
-...
diff --git a/llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O2.mir b/llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O2.mir
deleted file mode 100644
index ac2cdb4a50568..0000000000000
--- a/llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O2.mir
+++ /dev/null
@@ -1,113 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O2 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
-# RUN: -mattr=+amx-transpose -run-pass=tilepreconfig -o - %s | FileCheck %s
-
----
-name: test_tile_2rpntlvwz0
-alignment: 16
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHContTarget: false
-hasEHScopes: false
-hasEHFunclets: false
-failsVerification: false
-tracksDebugUserValues: false
-registers:
- - { id: 0, class: gr32, preferred-register: '' }
- - { id: 1, class: gr32, preferred-register: '' }
- - { id: 2, class: gr32, preferred-register: '' }
- - { id: 3, class: gr16, preferred-register: '' }
- - { id: 4, class: gr16, preferred-register: '' }
- - { id: 5, class: gr16, preferred-register: '' }
- - { id: 6, class: gr64, preferred-register: '' }
- - { id: 7, class: gr64_nosp, preferred-register: '' }
- - { id: 8, class: tilepair, preferred-register: '' }
- - { id: 9, class: tile, preferred-register: '' }
- - { id: 10, class: tile, preferred-register: '' }
- - { id: 11, class: tile, preferred-register: '' }
- - { id: 12, class: tile, preferred-register: '' }
- - { id: 13, class: gr64, preferred-register: '' }
-liveins:
- - { reg: '$edi', virtual-reg: '%0' }
- - { reg: '$esi', virtual-reg: '%1' }
- - { reg: '$edx', virtual-reg: '%2' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- localFrameSize: 0
- savePoint: []
- restorePoint: []
-fixedStack: []
-stack: []
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- amxProgModel: ManagedRA
-body: |
- bb.0.entry:
- liveins: $edi, $esi, $edx, $rax, $rbx
-
- ; CHECK-LABEL: name: test_tile_2rpntlvwz0
- ; CHECK: liveins: $edi, $esi, $edx, $rax, $rbx
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET0
- ; CHECK-NEXT: VMOVUPSZmr %stack.0, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.0, align 4)
- ; CHECK-NEXT: MOV8mi %stack.0, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.0, align 4)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
- ; CHECK-NEXT: PLDTILECFGV %stack.0, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.0, align 4)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY $rax
- ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 32
- ; CHECK-NEXT: [[PT2RPNTLVWZ0V:%[0-9]+]]:tilepair = PT2RPNTLVWZ0V [[COPY5]], [[COPY4]], [[COPY3]], killed [[COPY6]], 1, [[MOV32ri64_]], 0, $noreg
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:tile = COPY [[PT2RPNTLVWZ0V]].sub_t1
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:tile = COPY [[PT2RPNTLVWZ0V]].sub_t0
- ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV [[COPY5]], [[COPY4]]
- ; CHECK-NEXT: [[PTDPBSSDV:%[0-9]+]]:tile = PTDPBSSDV [[COPY5]], [[COPY3]], [[COPY4]], [[PTILEZEROV]], killed [[COPY8]], killed [[COPY7]]
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gr64 = COPY $rbx
- ; CHECK-NEXT: PTILESTOREDV [[COPY5]], [[COPY4]], killed [[COPY9]], 1, [[MOV32ri64_]], 0, $noreg, killed [[PTDPBSSDV]]
- ; CHECK-NEXT: RET 0
- %2:gr32 = COPY $edx
- %1:gr32 = COPY $esi
- %0:gr32 = COPY $edi
- %3:gr16 = COPY %2.sub_16bit
- %4:gr16 = COPY %1.sub_16bit
- %5:gr16 = COPY %0.sub_16bit
- %6:gr64 = COPY $rax
- %7:gr64_nosp = MOV32ri64 32
- %8:tilepair = PT2RPNTLVWZ0V %5, %4, %3, killed %6, 1, %7, 0, $noreg
- %9:tile = COPY %8.sub_t1
- %10:tile = COPY %8.sub_t0
- %11:tile = PTILEZEROV %5, %4
- %12:tile = PTDPBSSDV %5, %3, %4, %11, killed %10, killed %9
- %13:gr64 = COPY $rbx
- PTILESTOREDV %5, %4, killed %13, 1, %7, 0, $noreg, killed %12
- RET 0
-
-...
diff --git a/llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll b/llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
deleted file mode 100644
index 4cfd97afe721b..0000000000000
--- a/llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
+++ /dev/null
@@ -1,371 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+amx-bf16,+amx-fp16,+amx-complex,+amx-transpose | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+amx-bf16,+amx-fp16,+amx-complex,+amx-transpose,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
-
-define void @test_amx(i32 %rv32, i64 %stride, i64 %rvalue, i8* %addr1, <4 x float> %xmm) #0 {
-; CHECK-LABEL: test_amx:
-; CHECK: # %bb.0:
-; CHECK-NEXT: t2rpntlvwz0 (%rcx,%rsi), %tmm0
-; CHECK-NEXT: t2rpntlvwz0t1 (%rcx,%rsi), %tmm2
-; CHECK-NEXT: t2rpntlvwz1 (%rcx,%rsi), %tmm0
-; CHECK-NEXT: t2rpntlvwz1t1 (%rcx,%rsi), %tmm2
-; CHECK-NEXT: ttransposed %tmm3, %tmm1
-; CHECK-NEXT: ttdpbf16ps %tmm3, %tmm2, %tmm1
-; CHECK-NEXT: ttdpfp16ps %tmm6, %tmm5, %tmm4
-; CHECK-NEXT: ttcmmimfp16ps %tmm3, %tmm2, %tmm1
-; CHECK-NEXT: ttcmmrlfp16ps %tmm3, %tmm2, %tmm1
-; CHECK-NEXT: tconjtcmmimfp16ps %tmm3, %tmm2, %tmm1
-; CHECK-NEXT: tconjtfp16 %tmm2, %tmm1
-; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_amx:
-; EGPR: # %bb.0:
-; EGPR-NEXT: t2rpntlvwz0 (%rcx,%rsi), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6e,0x04,0x31]
-; EGPR-NEXT: t2rpntlvwz0t1 (%rcx,%rsi), %tmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6f,0x14,0x31]
-; EGPR-NEXT: t2rpntlvwz1 (%rcx,%rsi), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x6e,0x04,0x31]
-; EGPR-NEXT: t2rpntlvwz1t1 (%rcx,%rsi), %tmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x6f,0x14,0x31]
-; EGPR-NEXT: ttransposed %tmm3, %tmm1 # encoding: [0xc4,0xe2,0x7a,0x5f,0xcb]
-; EGPR-NEXT: ttdpbf16ps %tmm3, %tmm2, %tmm1 # encoding: [0xc4,0xe2,0x62,0x6c,0xca]
-; EGPR-NEXT: ttdpfp16ps %tmm6, %tmm5, %tmm4 # encoding: [0xc4,0xe2,0x4b,0x6c,0xe5]
-; EGPR-NEXT: ttcmmimfp16ps %tmm3, %tmm2, %tmm1 # encoding: [0xc4,0xe2,0x63,0x6b,0xca]
-; EGPR-NEXT: ttcmmrlfp16ps %tmm3, %tmm2, %tmm1 # encoding: [0xc4,0xe2,0x62,0x6b,0xca]
-; EGPR-NEXT: tconjtcmmimfp16ps %tmm3, %tmm2, %tmm1 # encoding: [0xc4,0xe2,0x60,0x6b,0xca]
-; EGPR-NEXT: tconjtfp16 %tmm2, %tmm1 # encoding: [0xc4,0xe2,0x79,0x6b,0xca]
-; EGPR-NEXT: retq # encoding: [0xc3]
- call void @llvm.x86.t2rpntlvwz0(i8 1, i8* %addr1, i64 %stride)
- call void @llvm.x86.t2rpntlvwz0t1(i8 2, i8* %addr1, i64 %stride)
- call void @llvm.x86.t2rpntlvwz1(i8 1, i8* %addr1, i64 %stride)
- call void @llvm.x86.t2rpntlvwz1t1(i8 2, i8* %addr1, i64 %stride)
- call void @llvm.x86.ttransposed(i8 1, i8 3)
- call void @llvm.x86.ttdpbf16ps(i8 1, i8 2, i8 3)
- call void @llvm.x86.ttdpfp16ps(i8 4, i8 5, i8 6)
- call void @llvm.x86.ttcmmimfp16ps(i8 1, i8 2, i8 3)
- call void @llvm.x86.ttcmmrlfp16ps(i8 1, i8 2, i8 3)
- call void @llvm.x86.tconjtcmmimfp16ps(i8 1, i8 2, i8 3)
- call void @llvm.x86.tconjtfp16(i8 1, i8 2)
- ret void
-}
-
-declare void @llvm.x86.t2rpntlvwz0(i8 %tile1, i8* %addr1, i64 %stride)
-declare void @llvm.x86.t2rpntlvwz0t1(i8 %tile1, i8* %addr1, i64 %stride)
-declare void @llvm.x86.t2rpntlvwz1(i8 %tile1, i8* %addr1, i64 %stride)
-declare void @llvm.x86.t2rpntlvwz1t1(i8 %tile1, i8* %addr1, i64 %stride)
-declare void @llvm.x86.ttransposed(i8 %tile0, i8 %tile1)
-declare void @llvm.x86.ttdpbf16ps(i8 %tile0, i8 %tile1, i8 %tile2)
-declare void @llvm.x86.ttdpfp16ps(i8 %tile0, i8 %tile1, i8 %tile2)
-declare void @llvm.x86.ttcmmimfp16ps(i8 %A, i8 %B, i8 %C)
-declare void @llvm.x86.ttcmmrlfp16ps(i8 %A, i8 %B, i8 %C)
-declare void @llvm.x86.tconjtcmmimfp16ps(i8 %A, i8 %B, i8 %C)
-declare void @llvm.x86.tconjtfp16(i8 %A, i8 %B)
-
-define void @test_amx2(i8* %pointer, i8* %base, i64 %stride) #0 {
-; CHECK-LABEL: test_amx2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: pushq %rbp
-; CHECK-NEXT: subq $2928, %rsp # imm = 0xB70
-; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, %ax
-; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm0
-; CHECK-NEXT: tilezero %tmm1
-; CHECK-NEXT: tilezero %tmm2
-; CHECK-NEXT: ttdpbf16ps %tmm1, %tmm0, %tmm2
-; CHECK-NEXT: ttdpfp16ps %tmm1, %tmm0, %tmm2
-; CHECK-NEXT: ttcmmimfp16ps %tmm1, %tmm0, %tmm2
-; CHECK-NEXT: ttcmmrlfp16ps %tmm1, %tmm0, %tmm2
-; CHECK-NEXT: movabsq $64, %rbp
-; CHECK-NEXT: tilestored %tmm2, 896(%rsp,%rbp) # 1024-byte Folded Spill
-; CHECK-NEXT: tileloadd 896(%rsp,%rbp), %tmm3 # 1024-byte Folded Reload
-; CHECK-NEXT: tconjtcmmimfp16ps %tmm1, %tmm0, %tmm3
-; CHECK-NEXT: tconjtfp16 %tmm3, %tmm0
-; CHECK-NEXT: tilestored %tmm2, (%rdi,%rdx)
-; CHECK-NEXT: addq $2928, %rsp # imm = 0xB70
-; CHECK-NEXT: popq %rbp
-; CHECK-NEXT: tilerelease
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_amx2:
-; EGPR: # %bb.0:
-; EGPR-NEXT: pushq %rbp # encoding: [0x55]
-; EGPR-NEXT: subq $2928, %rsp # encoding: [0x48,0x81,0xec,0x70,0x0b,0x00,0x00]
-; EGPR-NEXT: # imm = 0xB70
-; EGPR-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
-; EGPR-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp) # encoding: [0x62,0xf1,0x7c,0x48,0x11,0x44,0x24,0x0d]
-; EGPR-NEXT: movb $1, {{[0-9]+}}(%rsp) # encoding: [0xc6,0x84,0x24,0x40,0x03,0x00,0x00,0x01]
-; EGPR-NEXT: movb $8, {{[0-9]+}}(%rsp) # encoding: [0xc6,0x84,0x24,0x70,0x03,0x00,0x00,0x08]
-; EGPR-NEXT: movw $8, {{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x84,0x24,0x50,0x03,0x00,0x00,0x08,0x00]
-; EGPR-NEXT: movb $8, {{[0-9]+}}(%rsp) # encoding: [0xc6,0x84,0x24,0x71,0x03,0x00,0x00,0x08]
-; EGPR-NEXT: movw $8, {{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x84,0x24,0x52,0x03,0x00,0x00,0x08,0x00]
-; EGPR-NEXT: movb $8, {{[0-9]+}}(%rsp) # encoding: [0xc6,0x84,0x24,0x72,0x03,0x00,0x00,0x08]
-; EGPR-NEXT: movw $8, {{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x84,0x24,0x54,0x03,0x00,0x00,0x08,0x00]
-; EGPR-NEXT: movb $8, {{[0-9]+}}(%rsp) # encoding: [0xc6,0x84,0x24,0x73,0x03,0x00,0x00,0x08]
-; EGPR-NEXT: movw $8, {{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x84,0x24,0x56,0x03,0x00,0x00,0x08,0x00]
-; EGPR-NEXT: ldtilecfg {{[0-9]+}}(%rsp) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x84,0x24,0x40,0x03,0x00,0x00]
-; EGPR-NEXT: movw $8, %ax # encoding: [0x66,0xb8,0x08,0x00]
-; EGPR-NEXT: tileloadd (%rsi,%rdx), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x04,0x16]
-; EGPR-NEXT: tilezero %tmm1 # encoding: [0xc4,0xe2,0x7b,0x49,0xc8]
-; EGPR-NEXT: tilezero %tmm2 # encoding: [0xc4,0xe2,0x7b,0x49,0xd0]
-; EGPR-NEXT: ttdpbf16ps %tmm1, %tmm0, %tmm2 # encoding: [0xc4,0xe2,0x72,0x6c,0xd0]
-; EGPR-NEXT: ttdpfp16ps %tmm1, %tmm0, %tmm2 # encoding: [0xc4,0xe2,0x73,0x6c,0xd0]
-; EGPR-NEXT: ttcmmimfp16ps %tmm1, %tmm0, %tmm2 # encoding: [0xc4,0xe2,0x73,0x6b,0xd0]
-; EGPR-NEXT: ttcmmrlfp16ps %tmm1, %tmm0, %tmm2 # encoding: [0xc4,0xe2,0x72,0x6b,0xd0]
-; EGPR-NEXT: movabsq $64, %rbp # encoding: [0x48,0xbd,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm2, 896(%rsp,%rbp) # 1024-byte Folded Spill
-; EGPR-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x94,0x2c,0x80,0x03,0x00,0x00]
-; EGPR-NEXT: tileloadd 896(%rsp,%rbp), %tmm3 # 1024-byte Folded Reload
-; EGPR-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x9c,0x2c,0x80,0x03,0x00,0x00]
-; EGPR-NEXT: tconjtcmmimfp16ps %tmm1, %tmm0, %tmm3 # encoding: [0xc4,0xe2,0x70,0x6b,0xd8]
-; EGPR-NEXT: tconjtfp16 %tmm3, %tmm0 # encoding: [0xc4,0xe2,0x79,0x6b,0xc3]
-; EGPR-NEXT: tilestored %tmm2, (%rdi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x14,0x17]
-; EGPR-NEXT: addq $2928, %rsp # encoding: [0x48,0x81,0xc4,0x70,0x0b,0x00,0x00]
-; EGPR-NEXT: # imm = 0xB70
-; EGPR-NEXT: popq %rbp # encoding: [0x5d]
-; EGPR-NEXT: tilerelease # encoding: [0xc4,0xe2,0x78,0x49,0xc0]
-; EGPR-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
-; EGPR-NEXT: retq # encoding: [0xc3]
-
- %a = call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %base, i64 %stride)
- %b = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 8)
- %c = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 8)
- %c1 = call x86_amx @llvm.x86.ttdpbf16ps.internal(i16 8, i16 8, i16 8, x86_amx %c, x86_amx %a, x86_amx %b)
- %c2 = call x86_amx @llvm.x86.ttdpfp16ps.internal(i16 8, i16 8, i16 8, x86_amx %c1, x86_amx %a, x86_amx %b)
- %c3 = call x86_amx @llvm.x86.ttcmmimfp16ps.internal(i16 8, i16 8, i16 8, x86_amx %c2, x86_amx %a, x86_amx %b)
- %c4 = call x86_amx @llvm.x86.ttcmmrlfp16ps.internal(i16 8, i16 8, i16 8, x86_amx %c3, x86_amx %a, x86_amx %b)
- %c5 = call x86_amx @llvm.x86.tconjtcmmimfp16ps.internal(i16 8, i16 8, i16 8, x86_amx %c4, x86_amx %a, x86_amx %b)
- %c6 = call x86_amx @llvm.x86.tconjtfp16.internal(i16 8, i16 8, x86_amx %c5)
-
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %pointer, i64 %stride, x86_amx %c4)
- ret void
-}
-
-define void @test_amx3(i8* %pointer, i8* %base, i64 %stride) #0 {
-; CHECK-LABEL: test_amx3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movw $8, %cx
-; CHECK-NEXT: t2rpntlvwz0 (%rsi,%rdx), %tmm4
-; CHECK-NEXT: t2rpntlvwz0t1 (%rsi,%rdx), %tmm4
-; CHECK-NEXT: t2rpntlvwz1 (%rsi,%rdx), %tmm4
-; CHECK-NEXT: t2rpntlvwz1t1 (%rsi,%rdx), %tmm4
-; CHECK-NEXT: ttransposed %tmm4, %tmm0
-; CHECK-NEXT: tilestored %tmm0, (%rdi,%rdx)
-; CHECK-NEXT: tilerelease
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_amx3:
-; EGPR: # %bb.0:
-; EGPR-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
-; EGPR-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp) # encoding: [0x62,0xf1,0x7c,0x48,0x11,0x44,0x24,0xff]
-; EGPR-NEXT: movb $1, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xc0,0x01]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xf0,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0xd0,0x08,0x00]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xf4,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0xd8,0x08,0x00]
-; EGPR-NEXT: movb $0, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xf5,0x00]
-; EGPR-NEXT: movw $0, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0xda,0x00,0x00]
-; EGPR-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x44,0x24,0xc0]
-; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: movw $8, %cx # encoding: [0x66,0xb9,0x08,0x00]
-; EGPR-NEXT: t2rpntlvwz0 (%rsi,%rdx), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6e,0x24,0x16]
-; EGPR-NEXT: t2rpntlvwz0t1 (%rsi,%rdx), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6f,0x24,0x16]
-; EGPR-NEXT: t2rpntlvwz1 (%rsi,%rdx), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x6e,0x24,0x16]
-; EGPR-NEXT: t2rpntlvwz1t1 (%rsi,%rdx), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x6f,0x24,0x16]
-; EGPR-NEXT: ttransposed %tmm4, %tmm0 # encoding: [0xc4,0xe2,0x7a,0x5f,0xc4]
-; EGPR-NEXT: tilestored %tmm0, (%rdi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x04,0x17]
-; EGPR-NEXT: tilerelease # encoding: [0xc4,0xe2,0x78,0x49,0xc0]
-; EGPR-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
-; EGPR-NEXT: retq # encoding: [0xc3]
- %1 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 8, i16 8, i16 0, i8* %base, i64 %stride)
- %2 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0t1.internal(i16 8, i16 8, i16 0, i8* %base, i64 %stride)
- %3 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1.internal(i16 8, i16 8, i16 0, i8* %base, i64 %stride)
- %4 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1t1.internal(i16 8, i16 8, i16 0, i8* %base, i64 %stride)
- %5 = extractvalue { x86_amx, x86_amx } %4, 0
- %6 = call x86_amx @llvm.x86.ttransposed.internal(i16 8, i16 8, x86_amx %5)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %pointer, i64 %stride, x86_amx %6)
- ret void
-}
-
-define void @test_amx_spill(i8* %pointer, i8* %base, i64 %stride) #0 {
-; CHECK-LABEL: test_amx_spill:
-; CHECK: # %bb.0:
-; CHECK-NEXT: subq $6088, %rsp # imm = 0x17C8
-; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movw $8, %ax
-; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm0
-; CHECK-NEXT: t2rpntlvwz0 (%rsi,%rdx), %tmm4
-; CHECK-NEXT: t2rpntlvwz0t1 (%rsi,%rdx), %tmm6
-; CHECK-NEXT: movabsq $64, %rcx
-; CHECK-NEXT: tilestored %tmm6, 4032(%rsp,%rcx) # 1024-byte Folded Spill
-; CHECK-NEXT: tilestored %tmm7, 5056(%rsp,%rcx) # 1024-byte Folded Spill
-; CHECK-NEXT: t2rpntlvwz1 (%rsi,%rdx), %tmm6
-; CHECK-NEXT: tilestored %tmm6, 1984(%rsp,%rcx) # 1024-byte Folded Spill
-; CHECK-NEXT: tilestored %tmm7, 3008(%rsp,%rcx) # 1024-byte Folded Spill
-; CHECK-NEXT: t2rpntlvwz1t1 (%rsi,%rdx), %tmm6
-; CHECK-NEXT: tilestored %tmm6, -64(%rsp,%rcx) # 1024-byte Folded Spill
-; CHECK-NEXT: tilestored %tmm7, 960(%rsp,%rcx) # 1024-byte Folded Spill
-; CHECK-NEXT: t2rpntlvwz0 (%rsi,%rdx), %tmm6
-; CHECK-NEXT: tilestored %tmm4, (%rsi,%rdx)
-; CHECK-NEXT: tilestored %tmm5, (%rsi,%rdx)
-; CHECK-NEXT: tileloadd 4032(%rsp,%rcx), %tmm4 # 1024-byte Folded Reload
-; CHECK-NEXT: tileloadd 5056(%rsp,%rcx), %tmm5 # 1024-byte Folded Reload
-; CHECK-NEXT: tilestored %tmm4, (%rsi,%rdx)
-; CHECK-NEXT: tilestored %tmm5, (%rsi,%rdx)
-; CHECK-NEXT: tileloadd 1984(%rsp,%rcx), %tmm4 # 1024-byte Folded Reload
-; CHECK-NEXT: tileloadd 3008(%rsp,%rcx), %tmm5 # 1024-byte Folded Reload
-; CHECK-NEXT: tilestored %tmm4, (%rsi,%rdx)
-; CHECK-NEXT: tilestored %tmm5, (%rsi,%rdx)
-; CHECK-NEXT: tileloadd -64(%rsp,%rcx), %tmm4 # 1024-byte Folded Reload
-; CHECK-NEXT: tileloadd 960(%rsp,%rcx), %tmm5 # 1024-byte Folded Reload
-; CHECK-NEXT: tilestored %tmm4, (%rsi,%rdx)
-; CHECK-NEXT: tilestored %tmm5, (%rsi,%rdx)
-; CHECK-NEXT: tilestored %tmm6, (%rsi,%rdx)
-; CHECK-NEXT: tilestored %tmm7, (%rsi,%rdx)
-; CHECK-NEXT: addq $6088, %rsp # imm = 0x17C8
-; CHECK-NEXT: tilerelease
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_amx_spill:
-; EGPR: # %bb.0:
-; EGPR-NEXT: subq $6088, %rsp # encoding: [0x48,0x81,0xec,0xc8,0x17,0x00,0x00]
-; EGPR-NEXT: # imm = 0x17C8
-; EGPR-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
-; EGPR-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp) # encoding: [0x62,0xf1,0x7c,0x48,0x11,0x44,0x24,0xfe]
-; EGPR-NEXT: movb $1, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0x80,0x01]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xb0,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0x90,0x08,0x00]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xb4,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0x98,0x08,0x00]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xb5,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0x9a,0x08,0x00]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xb6,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0x9c,0x08,0x00]
-; EGPR-NEXT: movb $8, -{{[0-9]+}}(%rsp) # encoding: [0xc6,0x44,0x24,0xb7,0x08]
-; EGPR-NEXT: movw $8, -{{[0-9]+}}(%rsp) # encoding: [0x66,0xc7,0x44,0x24,0x9e,0x08,0x00]
-; EGPR-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x44,0x24,0x80]
-; EGPR-NEXT: movw $8, %ax # encoding: [0x66,0xb8,0x08,0x00]
-; EGPR-NEXT: tileloadd (%rsi,%rdx), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x04,0x16]
-; EGPR-NEXT: t2rpntlvwz0 (%rsi,%rdx), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6e,0x24,0x16]
-; EGPR-NEXT: t2rpntlvwz0t1 (%rsi,%rdx), %tmm6 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6f,0x34,0x16]
-; EGPR-NEXT: movabsq $64, %rcx # encoding: [0x48,0xb9,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm6, 4032(%rsp,%rcx) # 1024-byte Folded Spill
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7a,0x4b,0xb4,0x0c,0xc0,0x0f,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm7, 5056(%rsp,%rcx) # 1024-byte Folded Spill
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7a,0x4b,0xbc,0x0c,0xc0,0x13,0x00,0x00]
-; EGPR-NEXT: t2rpntlvwz1 (%rsi,%rdx), %tmm6 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x6e,0x34,0x16]
-; EGPR-NEXT: tilestored %tmm6, 1984(%rsp,%rcx) # 1024-byte Folded Spill
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7a,0x4b,0xb4,0x0c,0xc0,0x07,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm7, 3008(%rsp,%rcx) # 1024-byte Folded Spill
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7a,0x4b,0xbc,0x0c,0xc0,0x0b,0x00,0x00]
-; EGPR-NEXT: t2rpntlvwz1t1 (%rsi,%rdx), %tmm6 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x6f,0x34,0x16]
-; EGPR-NEXT: tilestored %tmm6, -64(%rsp,%rcx) # 1024-byte Folded Spill
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7a,0x4b,0x74,0x0c,0xc0]
-; EGPR-NEXT: tilestored %tmm7, 960(%rsp,%rcx) # 1024-byte Folded Spill
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7a,0x4b,0xbc,0x0c,0xc0,0x03,0x00,0x00]
-; EGPR-NEXT: t2rpntlvwz0 (%rsi,%rdx), %tmm6 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x6e,0x34,0x16]
-; EGPR-NEXT: tilestored %tmm4, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x24,0x16]
-; EGPR-NEXT: tilestored %tmm5, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x2c,0x16]
-; EGPR-NEXT: tileloadd 4032(%rsp,%rcx), %tmm4 # 1024-byte Folded Reload
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7b,0x4b,0xa4,0x0c,0xc0,0x0f,0x00,0x00]
-; EGPR-NEXT: tileloadd 5056(%rsp,%rcx), %tmm5 # 1024-byte Folded Reload
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7b,0x4b,0xac,0x0c,0xc0,0x13,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm4, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x24,0x16]
-; EGPR-NEXT: tilestored %tmm5, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x2c,0x16]
-; EGPR-NEXT: tileloadd 1984(%rsp,%rcx), %tmm4 # 1024-byte Folded Reload
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7b,0x4b,0xa4,0x0c,0xc0,0x07,0x00,0x00]
-; EGPR-NEXT: tileloadd 3008(%rsp,%rcx), %tmm5 # 1024-byte Folded Reload
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7b,0x4b,0xac,0x0c,0xc0,0x0b,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm4, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x24,0x16]
-; EGPR-NEXT: tilestored %tmm5, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x2c,0x16]
-; EGPR-NEXT: tileloadd -64(%rsp,%rcx), %tmm4 # 1024-byte Folded Reload
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7b,0x4b,0x64,0x0c,0xc0]
-; EGPR-NEXT: tileloadd 960(%rsp,%rcx), %tmm5 # 1024-byte Folded Reload
-; EGPR-NEXT: # encoding: [0xc4,0xe2,0x7b,0x4b,0xac,0x0c,0xc0,0x03,0x00,0x00]
-; EGPR-NEXT: tilestored %tmm4, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x24,0x16]
-; EGPR-NEXT: tilestored %tmm5, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x2c,0x16]
-; EGPR-NEXT: tilestored %tmm6, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x34,0x16]
-; EGPR-NEXT: tilestored %tmm7, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x3c,0x16]
-; EGPR-NEXT: addq $6088, %rsp # encoding: [0x48,0x81,0xc4,0xc8,0x17,0x00,0x00]
-; EGPR-NEXT: # imm = 0x17C8
-; EGPR-NEXT: tilerelease # encoding: [0xc4,0xe2,0x78,0x49,0xc0]
-; EGPR-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
-; EGPR-NEXT: retq # encoding: [0xc3]
- %a = call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %base, i64 %stride)
- %b1 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- %b2 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0t1.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- %b3 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- %b4 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1t1.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- %b5 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 8, i16 8, i16 8, i8* %base, i64 %stride)
- %e11 = extractvalue { x86_amx, x86_amx } %b1, 0
- %e12 = extractvalue { x86_amx, x86_amx } %b1, 1
- %e21 = extractvalue { x86_amx, x86_amx } %b2, 0
- %e22 = extractvalue { x86_amx, x86_amx } %b2, 1
- %e31 = extractvalue { x86_amx, x86_amx } %b3, 0
- %e32 = extractvalue { x86_amx, x86_amx } %b3, 1
- %e41 = extractvalue { x86_amx, x86_amx } %b4, 0
- %e42 = extractvalue { x86_amx, x86_amx } %b4, 1
- %e51 = extractvalue { x86_amx, x86_amx } %b5, 0
- %e52 = extractvalue { x86_amx, x86_amx } %b5, 1
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e11)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e12)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e21)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e22)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e31)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e32)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e41)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e42)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e51)
- call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %base, i64 %stride, x86_amx %e52)
- ret void
-}
-
-declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
-declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16, i16, i16, i8*, i64)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0t1.internal(i16, i16, i16, i8*, i64)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1.internal(i16, i16, i16, i8*, i64)
-declare { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz1t1.internal(i16, i16, i16, i8*, i64)
-declare x86_amx @llvm.x86.ttransposed.internal(i16, i16, x86_amx)
-declare x86_amx @llvm.x86.ttdpbf16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
-declare x86_amx @llvm.x86.ttdpfp16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
-declare x86_amx @llvm.x86.ttcmmimfp16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
-declare x86_amx @llvm.x86.ttcmmrlfp16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
-declare x86_amx @llvm.x86.tconjtcmmimfp16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
-declare x86_amx @llvm.x86.tconjtfp16.internal(i16, i16, x86_amx)
-
-attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/X86/ipra-reg-usage.ll b/llvm/test/CodeGen/X86/ipra-reg-usage.ll
index e73ff791dc423..f270f8fc741aa 100644
--- a/llvm/test/CodeGen/X86/ipra-reg-usage.ll
+++ b/llvm/test/CodeGen/X86/ipra-reg-usage.ll
@@ -7,7 +7,7 @@
target triple = "x86_64-unknown-unknown"
declare void @bar1()
define preserve_allcc void @foo()#0 {
-; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $fs_base $gs $gs_base $hip $hsp $ip $mxcsr $rflags $rip $riz $rsp $sp $sph $spl $ss $ssp $_eflags $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $r11b $r11bh $r11d $r11w $r11wh $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $k0_k1 $k2_k3 $k4_k5 $k6_k7 $tmmcfg $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $tmm0_tmm1 $tmm2_tmm3 $tmm4_tmm5 $tmm6_tmm7 $r16 $r17 $r18 $r19 $r20 $r21 $r22 $r23 $r24 $r25 $r26 $r27 $r28 $r29 $r30 $r31 $r16b $r17b $r18b $r19b $r20b $r21b $r22b $r23b $r24b $r25b $r26b $r27b $r28b $r29b $r30b $r31b $r16bh $r17bh $r18bh $r19bh $r20bh $r21bh $r22bh $r23bh $r24bh $r25bh $r26bh $r27bh $r28bh $r29bh $r30bh $r31bh $r16d $r17d $r18d $r19d $r20d $r21d $r22d $r23d $r24d $r25d $r26d $r27d $r28d $r29d $r30d $r31d $r16w $r17w $r18w $r19w $r20w $r21w $r22w $r23w $r24w $r25w $r26w $r27w $r28w $r29w $r30w $r31w $r16wh $r17wh $r18wh $r19wh $r20wh $r21wh $r22wh $r23wh $r24wh $r25wh $r26wh $r27wh $r28wh $r29wh $r30wh $r31wh
+; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $fs_base $gs $gs_base $hip $hsp $ip $mxcsr $rflags $rip $riz $rsp $sp $sph $spl $ss $ssp $_eflags $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $r11b $r11bh $r11d $r11w $r11wh $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $k0_k1 $k2_k3 $k4_k5 $k6_k7 $tmmcfg $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $r16 $r17 $r18 $r19 $r20 $r21 $r22 $r23 $r24 $r25 $r26 $r27 $r28 $r29 $r30 $r31 $r16b $r17b $r18b $r19b $r20b $r21b $r22b $r23b $r24b $r25b $r26b $r27b $r28b $r29b $r30b $r31b $r16bh $r17bh $r18bh $r19bh $r20bh $r21bh $r22bh $r23bh $r24bh $r25bh $r26bh $r27bh $r28bh $r29bh $r30bh $r31bh $r16d $r17d $r18d $r19d $r20d $r21d $r22d $r23d $r24d $r25d $r26d $r27d $r28d $r29d $r30d $r31d $r16w $r17w $r18w $r19w $r20w $r21w $r22w $r23w $r24w $r25w $r26w $r27w $r28w $r29w $r30w $r31w $r16wh $r17wh $r18wh $r19wh $r20wh $r21wh $r22wh $r23wh $r24wh $r25wh $r26wh $r27wh $r28wh $r29wh $r30wh $r31wh
call void @bar1()
call void @bar2()
ret void
@@ -15,7 +15,7 @@ define preserve_allcc void @foo()#0 {
declare void @bar2()
define preserve_nonecc void @foo2()#0 {
-; CHECK: foo2 Clobbered Registers: $ah $al $ax $ch $cl $cs $cx $df $dh $di $dih $dil $dl $ds $dx $eax $ecx $edi $edx $eflags $eip $eiz $es $esi $esp $fpcw $fpsw $fs $fs_base $gs $gs_base $hax $hcx $hdi $hdx $hip $hsi $hsp $ip $mxcsr $rax $rcx $rdi $rdx $rflags $rip $riz $rsi $rsp $si $sih $sil $sp $sph $spl $ss $ssp $_eflags $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r8 $r9 $r10 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $xmm0 $xmm1 $xmm2 $xmm3 $xmm4 $xmm5 $xmm6 $xmm7 $xmm8 $xmm9 $xmm10 $xmm11 $xmm12 $xmm13 $xmm14 $xmm15 $r8b $r9b $r10b $r11b $r8bh $r9bh $r10bh $r11bh $r8d $r9d $r10d $r11d $r8w $r9w $r10w $r11w $r8wh $r9wh $r10wh $r11wh $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $k0_k1 $k2_k3 $k4_k5 $k6_k7 $tmmcfg $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $tmm0_tmm1 $tmm2_tmm3 $tmm4_tmm5 $tmm6_tmm7 $r16 $r17 $r18 $r19 $r20 $r21 $r22 $r23 $r24 $r25 $r26 $r27 $r28 $r29 $r30 $r31 $r16b $r17b $r18b $r19b $r20b $r21b $r22b $r23b $r24b $r25b $r26b $r27b $r28b $r29b $r30b $r31b $r16bh $r17bh $r18bh $r19bh $r20bh $r21bh $r22bh $r23bh $r24bh $r25bh $r26bh $r27bh $r28bh $r29bh $r30bh $r31bh $r16d $r17d $r18d $r19d $r20d $r21d $r22d $r23d $r24d $r25d $r26d $r27d $r28d $r29d $r30d $r31d $r16w $r17w $r18w $r19w $r20w $r21w $r22w $r23w $r24w $r25w $r26w $r27w $r28w $r29w $r30w $r31w $r16wh $r17wh $r18wh $r19wh $r20wh $r21wh $r22wh $r23wh $r24wh $r25wh $r26wh $r27wh $r28wh $r29wh $r30wh $r31wh
+; CHECK: foo2 Clobbered Registers: $ah $al $ax $ch $cl $cs $cx $df $dh $di $dih $dil $dl $ds $dx $eax $ecx $edi $edx $eflags $eip $eiz $es $esi $esp $fpcw $fpsw $fs $fs_base $gs $gs_base $hax $hcx $hdi $hdx $hip $hsi $hsp $ip $mxcsr $rax $rcx $rdi $rdx $rflags $rip $riz $rsi $rsp $si $sih $sil $sp $sph $spl $ss $ssp $_eflags $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r8 $r9 $r10 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $xmm0 $xmm1 $xmm2 $xmm3 $xmm4 $xmm5 $xmm6 $xmm7 $xmm8 $xmm9 $xmm10 $xmm11 $xmm12 $xmm13 $xmm14 $xmm15 $r8b $r9b $r10b $r11b $r8bh $r9bh $r10bh $r11bh $r8d $r9d $r10d $r11d $r8w $r9w $r10w $r11w $r8wh $r9wh $r10wh $r11wh $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $k0_k1 $k2_k3 $k4_k5 $k6_k7 $tmmcfg $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $r16 $r17 $r18 $r19 $r20 $r21 $r22 $r23 $r24 $r25 $r26 $r27 $r28 $r29 $r30 $r31 $r16b $r17b $r18b $r19b $r20b $r21b $r22b $r23b $r24b $r25b $r26b $r27b $r28b $r29b $r30b $r31b $r16bh $r17bh $r18bh $r19bh $r20bh $r21bh $r22bh $r23bh $r24bh $r25bh $r26bh $r27bh $r28bh $r29bh $r30bh $r31bh $r16d $r17d $r18d $r19d $r20d $r21d $r22d $r23d $r24d $r25d $r26d $r27d $r28d $r29d $r30d $r31d $r16w $r17w $r18w $r19w $r20w $r21w $r22w $r23w $r24w $r25w $r26w $r27w $r28w $r29w $r30w $r31w $r16wh $r17wh $r18wh $r19wh $r20wh $r21wh $r22wh $r23wh $r24wh $r25wh $r26wh $r27wh $r28wh $r29wh $r30wh $r31wh
call void @bar1()
call void @bar2()
ret void
diff --git a/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt b/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
index 57e3153da401b..5c2927afbda4c 100755
--- a/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
+++ b/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
@@ -1,70 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s -check-prefix=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s -check-prefix=INTEL
-# ATT: t2rpntlvwz0rs 268435456(%rbp,%r14,8), %tmm6
-# INTEL: t2rpntlvwz0rs tmm6, [rbp + 8*r14 + 268435456]
-0xc4,0xa5,0x78,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0rs 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz0rs tmm2, [r8 + 4*rax + 291]
-0xc4,0xc5,0x78,0xf8,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0rs 64(%rbx), %tmm6
-# INTEL: t2rpntlvwz0rs tmm6, [rbx + 64]
-0xc4,0xe5,0x78,0xf8,0x74,0x23,0x40
-
-# ATT: t2rpntlvwz0rs -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0rs tmm2, [2*rbp - 32]
-0xc4,0xe5,0x78,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz0rst1 268435456(%rbp,%r14,8), %tmm6
-# INTEL: t2rpntlvwz0rst1 tmm6, [rbp + 8*r14 + 268435456]
-0xc4,0xa5,0x78,0xf9,0xb4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0rst1 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz0rst1 tmm2, [r8 + 4*rax + 291]
-0xc4,0xc5,0x78,0xf9,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0rst1 64(%rbx), %tmm6
-# INTEL: t2rpntlvwz0rst1 tmm6, [rbx + 64]
-0xc4,0xe5,0x78,0xf9,0x74,0x23,0x40
-
-# ATT: t2rpntlvwz0rst1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0rst1 tmm2, [2*rbp - 32]
-0xc4,0xe5,0x78,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1rs 268435456(%rbp,%r14,8), %tmm6
-# INTEL: t2rpntlvwz1rs tmm6, [rbp + 8*r14 + 268435456]
-0xc4,0xa5,0x79,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1rs 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz1rs tmm2, [r8 + 4*rax + 291]
-0xc4,0xc5,0x79,0xf8,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1rs 64(%rbx), %tmm6
-# INTEL: t2rpntlvwz1rs tmm6, [rbx + 64]
-0xc4,0xe5,0x79,0xf8,0x74,0x23,0x40
-
-# ATT: t2rpntlvwz1rs -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1rs tmm2, [2*rbp - 32]
-0xc4,0xe5,0x79,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1rst1 268435456(%rbp,%r14,8), %tmm6
-# INTEL: t2rpntlvwz1rst1 tmm6, [rbp + 8*r14 + 268435456]
-0xc4,0xa5,0x79,0xf9,0xb4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1rst1 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz1rst1 tmm2, [r8 + 4*rax + 291]
-0xc4,0xc5,0x79,0xf9,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1rst1 64(%rbx), %tmm6
-# INTEL: t2rpntlvwz1rst1 tmm6, [rbx + 64]
-0xc4,0xe5,0x79,0xf9,0x74,0x23,0x40
-
-# ATT: t2rpntlvwz1rst1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1rst1 tmm2, [2*rbp - 32]
-0xc4,0xe5,0x79,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff
-
# ATT: tileloaddrs 268435456(%rbp,%r14,8), %tmm6
# INTEL: tileloaddrs tmm6, [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x7b,0x4a,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -97,70 +33,6 @@
# INTEL: tileloaddrst1 tmm3, [2*rbp - 32]
0xc4,0xe2,0x79,0x4a,0x1c,0x6d,0xe0,0xff,0xff,0xff
-# ATT: t2rpntlvwz0rs 268435456(%r16,%r14,8), %tmm6
-# INTEL: t2rpntlvwz0rs tmm6, [r16 + 8*r14 + 268435456]
-0x62,0xbd,0x7c,0x08,0xf8,0xb4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0rs 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz0rs tmm2, [r8 + 4*r17 + 291]
-0x62,0xd5,0x78,0x08,0xf8,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0rs 64(%r18), %tmm6
-# INTEL: t2rpntlvwz0rs tmm6, [r18 + 64]
-0x62,0xfd,0x7c,0x08,0xf8,0x74,0x22,0x40
-
-# ATT: t2rpntlvwz0rs -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0rs tmm2, [2*rbp - 32]
-0x62,0xf5,0x7c,0x08,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz0rst1 268435456(%r16,%r14,8), %tmm6
-# INTEL: t2rpntlvwz0rst1 tmm6, [r16 + 8*r14 + 268435456]
-0x62,0xbd,0x7c,0x08,0xf9,0xb4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0rst1 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz0rst1 tmm2, [r8 + 4*r17 + 291]
-0x62,0xd5,0x78,0x08,0xf9,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0rst1 64(%r18), %tmm6
-# INTEL: t2rpntlvwz0rst1 tmm6, [r18 + 64]
-0x62,0xfd,0x7c,0x08,0xf9,0x74,0x22,0x40
-
-# ATT: t2rpntlvwz0rst1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0rst1 tmm2, [2*rbp - 32]
-0x62,0xf5,0x7c,0x08,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1rs 268435456(%r16,%r14,8), %tmm6
-# INTEL: t2rpntlvwz1rs tmm6, [r16 + 8*r14 + 268435456]
-0x62,0xbd,0x7d,0x08,0xf8,0xb4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1rs 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz1rs tmm2, [r8 + 4*r17 + 291]
-0x62,0xd5,0x79,0x08,0xf8,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1rs 64(%r18), %tmm6
-# INTEL: t2rpntlvwz1rs tmm6, [r18 + 64]
-0x62,0xfd,0x7d,0x08,0xf8,0x74,0x22,0x40
-
-# ATT: t2rpntlvwz1rs -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1rs tmm2, [2*rbp - 32]
-0x62,0xf5,0x7d,0x08,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1rst1 268435456(%r16,%r14,8), %tmm6
-# INTEL: t2rpntlvwz1rst1 tmm6, [r16 + 8*r14 + 268435456]
-0x62,0xbd,0x7d,0x08,0xf9,0xb4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1rst1 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz1rst1 tmm2, [r8 + 4*r17 + 291]
-0x62,0xd5,0x79,0x08,0xf9,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1rst1 64(%r18), %tmm6
-# INTEL: t2rpntlvwz1rst1 tmm6, [r18 + 64]
-0x62,0xfd,0x7d,0x08,0xf9,0x74,0x22,0x40
-
-# ATT: t2rpntlvwz1rst1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1rst1 tmm2, [2*rbp - 32]
-0x62,0xf5,0x7d,0x08,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff
-
# ATT: tileloaddrs 268435456(%r16,%r14,8), %tmm6
# INTEL: tileloaddrs tmm6, [r16 + 8*r14 + 268435456]
0x62,0xba,0x7f,0x08,0x4a,0xb4,0xf0,0x00,0x00,0x00,0x10
diff --git a/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt b/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
index f372c42982b1b..347e61cdfc4b8 100644
--- a/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
+++ b/llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
@@ -9,11 +9,3 @@
# INTEL: tmmultf32ps tmm3, tmm2, tmm1
0xc4,0xe2,0x71,0x48,0xda
-# ATT: ttmmultf32ps %tmm4, %tmm5, %tmm6
-# INTEL: ttmmultf32ps tmm6, tmm5, tmm4
-0xc4,0xe2,0x58,0x48,0xf5
-
-# ATT: ttmmultf32ps %tmm1, %tmm2, %tmm3
-# INTEL: ttmmultf32ps tmm3, tmm2, tmm1
-0xc4,0xe2,0x70,0x48,0xda
-
diff --git a/llvm/test/MC/Disassembler/X86/amx-transpose-att.txt b/llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
deleted file mode 100644
index d768630ac1475..0000000000000
--- a/llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
+++ /dev/null
@@ -1,154 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-# ATT: t2rpntlvwz0 268435456(%rbp,%r14,8), %tmm4
-# INTEL: t2rpntlvwz0 tmm4, [rbp + 8*r14 + 268435456]
-0xc4,0xa2,0x78,0x6e,0xa4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz0 tmm2, [r8 + 4*rax + 291]
-0xc4,0xc2,0x78,0x6e,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0 tmm2, [2*rbp - 32]
-0xc4,0xe2,0x78,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz0t1 268435456(%rbp,%r14,8), %tmm4
-# INTEL: t2rpntlvwz0t1 tmm4, [rbp + 8*r14 + 268435456]
-0xc4,0xa2,0x78,0x6f,0xa4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0t1 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz0t1 tmm2, [r8 + 4*rax + 291]
-0xc4,0xc2,0x78,0x6f,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0t1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0t1 tmm2, [2*rbp - 32]
-0xc4,0xe2,0x78,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1 268435456(%rbp,%r14,8), %tmm4
-# INTEL: t2rpntlvwz1 tmm4, [rbp + 8*r14 + 268435456]
-0xc4,0xa2,0x79,0x6e,0xa4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz1 tmm2, [r8 + 4*rax + 291]
-0xc4,0xc2,0x79,0x6e,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1 tmm2, [2*rbp - 32]
-0xc4,0xe2,0x79,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1t1 268435456(%rbp,%r14,8), %tmm4
-# INTEL: t2rpntlvwz1t1 tmm4, [rbp + 8*r14 + 268435456]
-0xc4,0xa2,0x79,0x6f,0xa4,0xf5,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1t1 291(%r8,%rax,4), %tmm2
-# INTEL: t2rpntlvwz1t1 tmm2, [r8 + 4*rax + 291]
-0xc4,0xc2,0x79,0x6f,0x94,0x80,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1t1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1t1 tmm2, [2*rbp - 32]
-0xc4,0xe2,0x79,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz0 268435456(%r16,%r14,8), %tmm4
-# INTEL: t2rpntlvwz0 tmm4, [r16 + 8*r14 + 268435456]
-0x62,0xba,0x7c,0x08,0x6e,0xa4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz0 tmm2, [r8 + 4*r17 + 291]
-0x62,0xd2,0x78,0x08,0x6e,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0 tmm2, [2*rbp - 32]
-0x62,0xf2,0x7c,0x08,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz0t1 268435456(%r16,%r14,8), %tmm4
-# INTEL: t2rpntlvwz0t1 tmm4, [r16 + 8*r14 + 268435456]
-0x62,0xba,0x7c,0x08,0x6f,0xa4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz0t1 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz0t1 tmm2, [r8 + 4*r17 + 291]
-0x62,0xd2,0x78,0x08,0x6f,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz0t1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz0t1 tmm2, [2*rbp - 32]
-0x62,0xf2,0x7c,0x08,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1 268435456(%r16,%r14,8), %tmm4
-# INTEL: t2rpntlvwz1 tmm4, [r16 + 8*r14 + 268435456]
-0x62,0xba,0x7d,0x08,0x6e,0xa4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz1 tmm2, [r8 + 4*r17 + 291]
-0x62,0xd2,0x79,0x08,0x6e,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1 tmm2, [2*rbp - 32]
-0x62,0xf2,0x7d,0x08,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: t2rpntlvwz1t1 268435456(%r16,%r14,8), %tmm4
-# INTEL: t2rpntlvwz1t1 tmm4, [r16 + 8*r14 + 268435456]
-0x62,0xba,0x7d,0x08,0x6f,0xa4,0xf0,0x00,0x00,0x00,0x10
-
-# ATT: t2rpntlvwz1t1 291(%r8,%r17,4), %tmm2
-# INTEL: t2rpntlvwz1t1 tmm2, [r8 + 4*r17 + 291]
-0x62,0xd2,0x79,0x08,0x6f,0x94,0x88,0x23,0x01,0x00,0x00
-
-# ATT: t2rpntlvwz1t1 -32(,%rbp,2), %tmm2
-# INTEL: t2rpntlvwz1t1 tmm2, [2*rbp - 32]
-0x62,0xf2,0x7d,0x08,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff
-
-# ATT: ttransposed %tmm1, %tmm2
-# INTEL: ttransposed tmm2, tmm1
-0xc4,0xe2,0x7a,0x5f,0xd1
-
-# ATT: ttransposed %tmm2, %tmm3
-# INTEL: ttransposed tmm3, tmm2
-0xc4,0xe2,0x7a,0x5f,0xda
-
-# ATT: ttdpbf16ps %tmm7, %tmm6, %tmm5
-# INTEL: ttdpbf16ps tmm5, tmm6, tmm7
-0xc4,0xe2,0x42,0x6c,0xee
-
-# ATT: ttdpbf16ps %tmm1, %tmm2, %tmm3
-# INTEL: ttdpbf16ps tmm3, tmm2, tmm1
-0xc4,0xe2,0x72,0x6c,0xda
-
-# ATT: ttdpfp16ps %tmm7, %tmm6, %tmm5
-# INTEL: ttdpfp16ps tmm5, tmm6, tmm7
-0xc4,0xe2,0x43,0x6c,0xee
-
-# ATT: ttdpfp16ps %tmm1, %tmm2, %tmm3
-# INTEL: ttdpfp16ps tmm3, tmm2, tmm1
-0xc4,0xe2,0x73,0x6c,0xda
-
-# ATT: ttcmmimfp16ps %tmm4, %tmm5, %tmm6
-# INTEL: ttcmmimfp16ps tmm6, tmm5, tmm4
-0xc4,0xe2,0x5b,0x6b,0xf5
-
-# ATT: ttcmmimfp16ps %tmm1, %tmm2, %tmm3
-# INTEL: ttcmmimfp16ps tmm3, tmm2, tmm1
-0xc4,0xe2,0x73,0x6b,0xda
-
-# ATT: ttcmmrlfp16ps %tmm4, %tmm5, %tmm6
-# INTEL: ttcmmrlfp16ps tmm6, tmm5, tmm4
-0xc4,0xe2,0x5a,0x6b,0xf5
-
-# ATT: ttcmmrlfp16ps %tmm1, %tmm2, %tmm3
-# INTEL: ttcmmrlfp16ps tmm3, tmm2, tmm1
-0xc4,0xe2,0x72,0x6b,0xda
-
-# ATT: tconjtcmmimfp16ps %tmm4, %tmm5, %tmm6
-# INTEL: tconjtcmmimfp16ps tmm6, tmm5, tmm4
-0xc4,0xe2,0x58,0x6b,0xf5
-
-# ATT: tconjtcmmimfp16ps %tmm1, %tmm2, %tmm3
-# INTEL: tconjtcmmimfp16ps tmm3, tmm2, tmm1
-0xc4,0xe2,0x70,0x6b,0xda
-
-# ATT: tconjtfp16 %tmm5, %tmm6
-# INTEL: tconjtfp16 tmm6, tmm5
-0xc4,0xe2,0x79,0x6b,0xf5
-
-# ATT: tconjtfp16 %tmm2, %tmm3
-# INTEL: tconjtfp16 tmm3, tmm2
-0xc4,0xe2,0x79,0x6b,0xda
diff --git a/llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s b/llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
index 92db672e1c82d..497a1c6b7bad5 100755
--- a/llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
+++ b/llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
@@ -1,69 +1,5 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
-// CHECK: t2rpntlvwz0rs 268435456(%rbp,%r14,8), %tmm6
-// CHECK: encoding: [0xc4,0xa5,0x78,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rs 268435456(%rbp,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz0rs 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc5,0x78,0xf8,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rs 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz0rs 64(%rbx), %tmm6
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf8,0x74,0x23,0x40]
- t2rpntlvwz0rs 64(%rbx), %tmm6
-
-// CHECK: t2rpntlvwz0rs -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0rs -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz0rst1 268435456(%rbp,%r14,8), %tmm6
-// CHECK: encoding: [0xc4,0xa5,0x78,0xf9,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rst1 268435456(%rbp,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz0rst1 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc5,0x78,0xf9,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rst1 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz0rst1 64(%rbx), %tmm6
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf9,0x74,0x23,0x40]
- t2rpntlvwz0rst1 64(%rbx), %tmm6
-
-// CHECK: t2rpntlvwz0rst1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0rst1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1rs 268435456(%rbp,%r14,8), %tmm6
-// CHECK: encoding: [0xc4,0xa5,0x79,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rs 268435456(%rbp,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz1rs 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc5,0x79,0xf8,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rs 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz1rs 64(%rbx), %tmm6
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf8,0x74,0x23,0x40]
- t2rpntlvwz1rs 64(%rbx), %tmm6
-
-// CHECK: t2rpntlvwz1rs -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1rs -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1rst1 268435456(%rbp,%r14,8), %tmm6
-// CHECK: encoding: [0xc4,0xa5,0x79,0xf9,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rst1 268435456(%rbp,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz1rst1 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc5,0x79,0xf9,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rst1 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz1rst1 64(%rbx), %tmm6
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf9,0x74,0x23,0x40]
- t2rpntlvwz1rst1 64(%rbx), %tmm6
-
-// CHECK: t2rpntlvwz1rst1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1rst1 -32(,%rbp,2), %tmm2
-
// CHECK: tileloaddrs 268435456(%rbp,%r14,8), %tmm6
// CHECK: encoding: [0xc4,0xa2,0x7b,0x4a,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloaddrs 268435456(%rbp,%r14,8), %tmm6
@@ -88,70 +24,6 @@
// CHECK: encoding: [0xc4,0xe2,0x79,0x4a,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloaddrst1 -32(,%rbp,2), %tmm3
-// CHECK: t2rpntlvwz0rs 268435456(%r16,%r14,8), %tmm6
-// CHECK: encoding: [0x62,0xbd,0x7c,0x08,0xf8,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rs 268435456(%r16,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz0rs 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd5,0x78,0x08,0xf8,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rs 291(%r8,%r17,4), %tmm2
-
-// CHECK: t2rpntlvwz0rs 64(%r18), %tmm6
-// CHECK: encoding: [0x62,0xfd,0x7c,0x08,0xf8,0x74,0x22,0x40]
- t2rpntlvwz0rs 64(%r18), %tmm6
-
-// CHECK: {evex} t2rpntlvwz0rs -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0rs -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz0rst1 268435456(%r16,%r14,8), %tmm6
-// CHECK: encoding: [0x62,0xbd,0x7c,0x08,0xf9,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rst1 268435456(%r16,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz0rst1 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd5,0x78,0x08,0xf9,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rst1 291(%r8,%r17,4), %tmm2
-
-// CHECK: t2rpntlvwz0rst1 64(%r18), %tmm6
-// CHECK: encoding: [0x62,0xfd,0x7c,0x08,0xf9,0x74,0x22,0x40]
- t2rpntlvwz0rst1 64(%r18), %tmm6
-
-// CHECK: {evex} t2rpntlvwz0rst1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0rst1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1rs 268435456(%r16,%r14,8), %tmm6
-// CHECK: encoding: [0x62,0xbd,0x7d,0x08,0xf8,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rs 268435456(%r16,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz1rs 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd5,0x79,0x08,0xf8,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rs 291(%r8,%r17,4), %tmm2
-
-// CHECK: t2rpntlvwz1rs 64(%r18), %tmm6
-// CHECK: encoding: [0x62,0xfd,0x7d,0x08,0xf8,0x74,0x22,0x40]
- t2rpntlvwz1rs 64(%r18), %tmm6
-
-// CHECK: {evex} t2rpntlvwz1rs -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1rs -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1rst1 268435456(%r16,%r14,8), %tmm6
-// CHECK: encoding: [0x62,0xbd,0x7d,0x08,0xf9,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rst1 268435456(%r16,%r14,8), %tmm6
-
-// CHECK: t2rpntlvwz1rst1 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd5,0x79,0x08,0xf9,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rst1 291(%r8,%r17,4), %tmm2
-
-// CHECK: t2rpntlvwz1rst1 64(%r18), %tmm6
-// CHECK: encoding: [0x62,0xfd,0x7d,0x08,0xf9,0x74,0x22,0x40]
- t2rpntlvwz1rst1 64(%r18), %tmm6
-
-// CHECK: {evex} t2rpntlvwz1rst1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1rst1 -32(,%rbp,2), %tmm2
-
// CHECK: tileloaddrs 291(%r16,%rax,4), %tmm3
// CHECK: encoding: [0x62,0xfa,0x7f,0x08,0x4a,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloaddrs 291(%r16,%rax,4), %tmm3
diff --git a/llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s b/llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
index 140d1aa6b198e..0e030ca415a16 100755
--- a/llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
+++ b/llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
@@ -1,69 +1,5 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
-// CHECK: t2rpntlvwz0rs tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa5,0x78,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rs tmm6, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0rs tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc5,0x78,0xf8,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rs tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz0rs tmm6, [rbx + 64]
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf8,0x74,0x23,0x40]
- t2rpntlvwz0rs tmm6, [rbx + 64]
-
-// CHECK: t2rpntlvwz0rs tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0rs tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz0rst1 tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa5,0x78,0xf9,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rst1 tmm6, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0rst1 tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc5,0x78,0xf9,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rst1 tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz0rst1 tmm6, [rbx + 64]
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf9,0x74,0x23,0x40]
- t2rpntlvwz0rst1 tmm6, [rbx + 64]
-
-// CHECK: t2rpntlvwz0rst1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe5,0x78,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0rst1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1rs tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa5,0x79,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rs tmm6, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1rs tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc5,0x79,0xf8,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rs tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz1rs tmm6, [rbx + 64]
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf8,0x74,0x23,0x40]
- t2rpntlvwz1rs tmm6, [rbx + 64]
-
-// CHECK: t2rpntlvwz1rs tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1rs tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1rst1 tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa5,0x79,0xf9,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rst1 tmm6, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1rst1 tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc5,0x79,0xf9,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rst1 tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz1rst1 tmm6, [rbx + 64]
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf9,0x74,0x23,0x40]
- t2rpntlvwz1rst1 tmm6, [rbx + 64]
-
-// CHECK: t2rpntlvwz1rst1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe5,0x79,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1rst1 tmm2, [2*rbp - 32]
-
// CHECK: tileloaddrs tmm6, [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x7b,0x4a,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloaddrs tmm6, [rbp + 8*r14 + 268435456]
@@ -96,70 +32,6 @@
// CHECK: encoding: [0xc4,0xe2,0x79,0x4a,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloaddrst1 tmm3, [2*rbp - 32]
-// CHECK: t2rpntlvwz0rs tmm6, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xbd,0x7c,0x08,0xf8,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rs tmm6, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0rs tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd5,0x78,0x08,0xf8,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rs tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: t2rpntlvwz0rs tmm6, [r18 + 64]
-// CHECK: encoding: [0x62,0xfd,0x7c,0x08,0xf8,0x74,0x22,0x40]
- t2rpntlvwz0rs tmm6, [r18 + 64]
-
-// CHECK: {evex} t2rpntlvwz0rs tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0rs tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz0rst1 tmm6, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xbd,0x7c,0x08,0xf9,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0rst1 tmm6, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0rst1 tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd5,0x78,0x08,0xf9,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0rst1 tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: t2rpntlvwz0rst1 tmm6, [r18 + 64]
-// CHECK: encoding: [0x62,0xfd,0x7c,0x08,0xf9,0x74,0x22,0x40]
- t2rpntlvwz0rst1 tmm6, [r18 + 64]
-
-// CHECK: {evex} t2rpntlvwz0rst1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0rst1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1rs tmm6, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xbd,0x7d,0x08,0xf8,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rs tmm6, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1rs tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd5,0x79,0x08,0xf8,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rs tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: t2rpntlvwz1rs tmm6, [r18 + 64]
-// CHECK: encoding: [0x62,0xfd,0x7d,0x08,0xf8,0x74,0x22,0x40]
- t2rpntlvwz1rs tmm6, [r18 + 64]
-
-// CHECK: {evex} t2rpntlvwz1rs tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0xf8,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1rs tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1rst1 tmm6, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xbd,0x7d,0x08,0xf9,0xb4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1rst1 tmm6, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1rst1 tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd5,0x79,0x08,0xf9,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1rst1 tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: t2rpntlvwz1rst1 tmm6, [r18 + 64]
-// CHECK: encoding: [0x62,0xfd,0x7d,0x08,0xf9,0x74,0x22,0x40]
- t2rpntlvwz1rst1 tmm6, [r18 + 64]
-
-// CHECK: {evex} t2rpntlvwz1rst1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0xf9,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1rst1 tmm2, [2*rbp - 32]
-
// CHECK: tileloaddrs tmm6, [r16 + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xba,0x7f,0x08,0x4a,0xb4,0xf0,0x00,0x00,0x00,0x10]
tileloaddrs tmm6, [r16 + 8*r14 + 268435456]
diff --git a/llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s b/llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
index b413597cd9da7..d1d0997b7eec0 100644
--- a/llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
+++ b/llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
@@ -8,10 +8,3 @@
// CHECK: encoding: [0xc4,0xe2,0x71,0x48,0xda]
tmmultf32ps %tmm1, %tmm2, %tmm3
-// CHECK: ttmmultf32ps %tmm4, %tmm5, %tmm6
-// CHECK: encoding: [0xc4,0xe2,0x58,0x48,0xf5]
- ttmmultf32ps %tmm4, %tmm5, %tmm6
-
-// CHECK: ttmmultf32ps %tmm1, %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x70,0x48,0xda]
- ttmmultf32ps %tmm1, %tmm2, %tmm3
diff --git a/llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s b/llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
index 98f55275716eb..b6c0947ee750c 100644
--- a/llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
+++ b/llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
@@ -8,10 +8,3 @@
// CHECK: encoding: [0xc4,0xe2,0x71,0x48,0xda]
tmmultf32ps tmm3, tmm2, tmm1
-// CHECK: ttmmultf32ps tmm6, tmm5, tmm4
-// CHECK: encoding: [0xc4,0xe2,0x58,0x48,0xf5]
- ttmmultf32ps tmm6, tmm5, tmm4
-
-// CHECK: ttmmultf32ps tmm3, tmm2, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x70,0x48,0xda]
- ttmmultf32ps tmm3, tmm2, tmm1
diff --git a/llvm/test/MC/X86/amx-transpose-att.s b/llvm/test/MC/X86/amx-transpose-att.s
deleted file mode 100644
index 5158470f8c905..0000000000000
--- a/llvm/test/MC/X86/amx-transpose-att.s
+++ /dev/null
@@ -1,153 +0,0 @@
-// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
-
-// CHECK: t2rpntlvwz0 268435456(%rbp,%r14,8), %tmm4
-// CHECK: encoding: [0xc4,0xa2,0x78,0x6e,0xa4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0 268435456(%rbp,%r14,8), %tmm4
-
-// CHECK: t2rpntlvwz0 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc2,0x78,0x6e,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz0 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe2,0x78,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz0t1 268435456(%rbp,%r14,8), %tmm4
-// CHECK: encoding: [0xc4,0xa2,0x78,0x6f,0xa4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0t1 268435456(%rbp,%r14,8), %tmm5
-
-// CHECK: t2rpntlvwz0t1 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc2,0x78,0x6f,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0t1 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz0t1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe2,0x78,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0t1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1 268435456(%rbp,%r14,8), %tmm4
-// CHECK: encoding: [0xc4,0xa2,0x79,0x6e,0xa4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1 268435456(%rbp,%r14,8), %tmm5
-
-// CHECK: t2rpntlvwz1 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc2,0x79,0x6e,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1t1 268435456(%rbp,%r14,8), %tmm2
-// CHECK: encoding: [0xc4,0xa2,0x79,0x6f,0x94,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1t1 268435456(%rbp,%r14,8), %tmm3
-
-// CHECK: t2rpntlvwz1t1 291(%r8,%rax,4), %tmm2
-// CHECK: encoding: [0xc4,0xc2,0x79,0x6f,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1t1 291(%r8,%rax,4), %tmm2
-
-// CHECK: t2rpntlvwz1t1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1t1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz0 268435456(%r16,%r14,8), %tmm4
-// CHECK: encoding: [0x62,0xba,0x7c,0x08,0x6e,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0 268435456(%r16,%r14,8), %tmm4
-
-// CHECK: t2rpntlvwz0 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd2,0x78,0x08,0x6e,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0 291(%r8,%r17,4), %tmm2
-
-// CHECK: {evex} t2rpntlvwz0 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf2,0x7c,0x08,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz0t1 268435456(%r16,%r14,8), %tmm4
-// CHECK: encoding: [0x62,0xba,0x7c,0x08,0x6f,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0t1 268435456(%r16,%r14,8), %tmm4
-
-// CHECK: t2rpntlvwz0t1 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd2,0x78,0x08,0x6f,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0t1 291(%r8,%r17,4), %tmm2
-
-// CHECK: {evex} t2rpntlvwz0t1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf2,0x7c,0x08,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0t1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1 268435456(%r16,%r14,8), %tmm4
-// CHECK: encoding: [0x62,0xba,0x7d,0x08,0x6e,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1 268435456(%r16,%r14,8), %tmm4
-
-// CHECK: t2rpntlvwz1 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd2,0x79,0x08,0x6e,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1 291(%r8,%r17,4), %tmm2
-
-// CHECK: {evex} t2rpntlvwz1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1 -32(,%rbp,2), %tmm2
-
-// CHECK: t2rpntlvwz1t1 268435456(%r16,%r14,8), %tmm4
-// CHECK: encoding: [0x62,0xba,0x7d,0x08,0x6f,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1t1 268435456(%r16,%r14,8), %tmm4
-
-// CHECK: t2rpntlvwz1t1 291(%r8,%r17,4), %tmm2
-// CHECK: encoding: [0x62,0xd2,0x79,0x08,0x6f,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1t1 291(%r8,%r17,4), %tmm2
-
-// CHECK: {evex} t2rpntlvwz1t1 -32(,%rbp,2), %tmm2
-// CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1t1 -32(,%rbp,2), %tmm2
-
-// CHECK: ttransposed %tmm1, %tmm5
-// CHECK: encoding: [0xc4,0xe2,0x7a,0x5f,0xe9]
- ttransposed %tmm1, %tmm5
-
-// CHECK: ttransposed %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x7a,0x5f,0xda]
- ttransposed %tmm2, %tmm3
-
-// CHECK: ttdpbf16ps %tmm1, %tmm2, %tmm5
-// CHECK: encoding: [0xc4,0xe2,0x72,0x6c,0xea]
- ttdpbf16ps %tmm1, %tmm2, %tmm5
-
-// CHECK: ttdpbf16ps %tmm1, %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x72,0x6c,0xda]
- ttdpbf16ps %tmm1, %tmm2, %tmm3
-
-// CHECK: ttdpfp16ps %tmm3, %tmm4, %tmm5
-// CHECK: encoding: [0xc4,0xe2,0x63,0x6c,0xec]
- ttdpfp16ps %tmm3, %tmm4, %tmm5
-
-// CHECK: ttdpfp16ps %tmm1, %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x73,0x6c,0xda]
- ttdpfp16ps %tmm1, %tmm2, %tmm3
-
-// CHECK: ttcmmimfp16ps %tmm4, %tmm5, %tmm6
-// CHECK: encoding: [0xc4,0xe2,0x5b,0x6b,0xf5]
- ttcmmimfp16ps %tmm4, %tmm5, %tmm6
-
-// CHECK: ttcmmimfp16ps %tmm1, %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x73,0x6b,0xda]
- ttcmmimfp16ps %tmm1, %tmm2, %tmm3
-
-// CHECK: ttcmmrlfp16ps %tmm4, %tmm5, %tmm6
-// CHECK: encoding: [0xc4,0xe2,0x5a,0x6b,0xf5]
- ttcmmrlfp16ps %tmm4, %tmm5, %tmm6
-
-// CHECK: ttcmmrlfp16ps %tmm1, %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x72,0x6b,0xda]
- ttcmmrlfp16ps %tmm1, %tmm2, %tmm3
-
-// CHECK: tconjtcmmimfp16ps %tmm4, %tmm5, %tmm6
-// CHECK: encoding: [0xc4,0xe2,0x58,0x6b,0xf5]
- tconjtcmmimfp16ps %tmm4, %tmm5, %tmm6
-
-// CHECK: tconjtcmmimfp16ps %tmm1, %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x70,0x6b,0xda]
- tconjtcmmimfp16ps %tmm1, %tmm2, %tmm3
-
-// CHECK: tconjtfp16 %tmm5, %tmm6
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6b,0xf5]
- tconjtfp16 %tmm5, %tmm6
-
-// CHECK: tconjtfp16 %tmm2, %tmm3
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6b,0xda]
- tconjtfp16 %tmm2, %tmm3
diff --git a/llvm/test/MC/X86/amx-transpose-intel.s b/llvm/test/MC/X86/amx-transpose-intel.s
deleted file mode 100644
index 0d2c22f67a173..0000000000000
--- a/llvm/test/MC/X86/amx-transpose-intel.s
+++ /dev/null
@@ -1,153 +0,0 @@
-// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
-
-// CHECK: t2rpntlvwz0 tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa2,0x78,0x6e,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0 tmm6, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0 tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc2,0x78,0x6e,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0 tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz0 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe2,0x78,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz0t1 tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa2,0x78,0x6f,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz0t1 tmm7, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0t1 tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc2,0x78,0x6f,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz0t1 tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz0t1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe2,0x78,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz0t1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1 tmm0, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa2,0x79,0x6e,0x84,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1 tmm1, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1 tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc2,0x79,0x6e,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1 tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1t1 tmm6, [rbp + 8*r14 + 268435456]
-// CHECK: encoding: [0xc4,0xa2,0x79,0x6f,0xb4,0xf5,0x00,0x00,0x00,0x10]
- t2rpntlvwz1t1 tmm6, [rbp + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1t1 tmm2, [r8 + 4*rax + 291]
-// CHECK: encoding: [0xc4,0xc2,0x79,0x6f,0x94,0x80,0x23,0x01,0x00,0x00]
- t2rpntlvwz1t1 tmm2, [r8 + 4*rax + 291]
-
-// CHECK: t2rpntlvwz1t1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- t2rpntlvwz1t1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz0 tmm4, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xba,0x7c,0x08,0x6e,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0 tmm4, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0 tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd2,0x78,0x08,0x6e,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0 tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: {evex} t2rpntlvwz0 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf2,0x7c,0x08,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz0t1 tmm4, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xba,0x7c,0x08,0x6f,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz0t1 tmm4, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz0t1 tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd2,0x78,0x08,0x6f,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz0t1 tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: {evex} t2rpntlvwz0t1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf2,0x7c,0x08,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz0t1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1 tmm4, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xba,0x7d,0x08,0x6e,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1 tmm4, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1 tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd2,0x79,0x08,0x6e,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1 tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: {evex} t2rpntlvwz1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x6e,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1 tmm2, [2*rbp - 32]
-
-// CHECK: t2rpntlvwz1t1 tmm4, [r16 + 8*r14 + 268435456]
-// CHECK: encoding: [0x62,0xba,0x7d,0x08,0x6f,0xa4,0xf0,0x00,0x00,0x00,0x10]
- t2rpntlvwz1t1 tmm4, [r16 + 8*r14 + 268435456]
-
-// CHECK: t2rpntlvwz1t1 tmm2, [r8 + 4*r17 + 291]
-// CHECK: encoding: [0x62,0xd2,0x79,0x08,0x6f,0x94,0x88,0x23,0x01,0x00,0x00]
- t2rpntlvwz1t1 tmm2, [r8 + 4*r17 + 291]
-
-// CHECK: {evex} t2rpntlvwz1t1 tmm2, [2*rbp - 32]
-// CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x6f,0x14,0x6d,0xe0,0xff,0xff,0xff]
- {evex} t2rpntlvwz1t1 tmm2, [2*rbp - 32]
-
-// CHECK: ttransposed tmm5, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x7a,0x5f,0xe9]
- ttransposed tmm5, tmm1
-
-// CHECK: ttransposed tmm3, tmm2
-// CHECK: encoding: [0xc4,0xe2,0x7a,0x5f,0xda]
- ttransposed tmm3, tmm2
-
-// CHECK: ttdpbf16ps tmm5, tmm0, tmm4
-// CHECK: encoding: [0xc4,0xe2,0x5a,0x6c,0xe8]
- ttdpbf16ps tmm5, tmm0, tmm4
-
-// CHECK: ttdpbf16ps tmm3, tmm2, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x72,0x6c,0xda]
- ttdpbf16ps tmm3, tmm2, tmm1
-
-// CHECK: ttdpfp16ps tmm1, tmm0, tmm4
-// CHECK: encoding: [0xc4,0xe2,0x5b,0x6c,0xc8]
- ttdpfp16ps tmm1, tmm0, tmm4
-
-// CHECK: ttdpfp16ps tmm3, tmm2, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x73,0x6c,0xda]
- ttdpfp16ps tmm3, tmm2, tmm1
-
-// CHECK: ttcmmimfp16ps tmm6, tmm5, tmm4
-// CHECK: encoding: [0xc4,0xe2,0x5b,0x6b,0xf5]
- ttcmmimfp16ps tmm6, tmm5, tmm4
-
-// CHECK: ttcmmimfp16ps tmm3, tmm2, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x73,0x6b,0xda]
- ttcmmimfp16ps tmm3, tmm2, tmm1
-
-// CHECK: ttcmmrlfp16ps tmm6, tmm5, tmm4
-// CHECK: encoding: [0xc4,0xe2,0x5a,0x6b,0xf5]
- ttcmmrlfp16ps tmm6, tmm5, tmm4
-
-// CHECK: ttcmmrlfp16ps tmm3, tmm2, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x72,0x6b,0xda]
- ttcmmrlfp16ps tmm3, tmm2, tmm1
-
-// CHECK: tconjtcmmimfp16ps tmm6, tmm5, tmm4
-// CHECK: encoding: [0xc4,0xe2,0x58,0x6b,0xf5]
- tconjtcmmimfp16ps tmm6, tmm5, tmm4
-
-// CHECK: tconjtcmmimfp16ps tmm3, tmm2, tmm1
-// CHECK: encoding: [0xc4,0xe2,0x70,0x6b,0xda]
- tconjtcmmimfp16ps tmm3, tmm2, tmm1
-
-// CHECK: tconjtfp16 tmm6, tmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6b,0xf5]
- tconjtfp16 tmm6, tmm5
-
-// CHECK: tconjtfp16 tmm3, tmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x6b,0xda]
- tconjtfp16 tmm3, tmm2
diff --git a/llvm/test/TableGen/x86-instr-mapping.inc b/llvm/test/TableGen/x86-instr-mapping.inc
index f621979b2af95..6d2873ed4e749 100644
--- a/llvm/test/TableGen/x86-instr-mapping.inc
+++ b/llvm/test/TableGen/x86-instr-mapping.inc
@@ -167,14 +167,6 @@ static const X86TableEntry X86CompressEVEXTable[] = {
{ X86::SHRX64rm_EVEX, X86::SHRX64rm },
{ X86::SHRX64rr_EVEX, X86::SHRX64rr },
{ X86::STTILECFG_EVEX, X86::STTILECFG },
- { X86::T2RPNTLVWZ0RST1_EVEX, X86::T2RPNTLVWZ0RST1 },
- { X86::T2RPNTLVWZ0RS_EVEX, X86::T2RPNTLVWZ0RS },
- { X86::T2RPNTLVWZ0T1_EVEX, X86::T2RPNTLVWZ0T1 },
- { X86::T2RPNTLVWZ0_EVEX, X86::T2RPNTLVWZ0 },
- { X86::T2RPNTLVWZ1RST1_EVEX, X86::T2RPNTLVWZ1RST1 },
- { X86::T2RPNTLVWZ1RS_EVEX, X86::T2RPNTLVWZ1RS },
- { X86::T2RPNTLVWZ1T1_EVEX, X86::T2RPNTLVWZ1T1 },
- { X86::T2RPNTLVWZ1_EVEX, X86::T2RPNTLVWZ1 },
{ X86::TILELOADDRST1_EVEX, X86::TILELOADDRST1 },
{ X86::TILELOADDRS_EVEX, X86::TILELOADDRS },
{ X86::TILELOADDT1_EVEX, X86::TILELOADDT1 },
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
index dfbac4ce0c4d3..141a56ad10903 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
@@ -1,33 +1,33 @@
MAX_RELATION=4
-187 7072 1
-187 6968 2
+187 7051 1
+187 6948 2
187 187 0
-187 7072 1
-187 6969 2
+187 7051 1
+187 6949 2
187 10 0
-10 7072 1
-10 7072 2
-10 7072 3
-10 6961 4
+10 7051 1
+10 7051 2
+10 7051 3
+10 6941 4
10 187 0
-187 6952 1
-187 7072 2
-187 1555 0
-1555 6882 1
-1555 6952 2
-187 7072 1
-187 6968 2
+187 6932 1
+187 7051 2
+187 1543 0
+1543 6862 1
+1543 6932 2
+187 7051 1
+187 6948 2
187 187 0
-187 7072 1
-187 6969 2
+187 7051 1
+187 6949 2
187 601 0
-601 7072 1
-601 7072 2
-601 7072 3
-601 6961 4
+601 7051 1
+601 7051 2
+601 7051 3
+601 6941 4
601 187 0
-187 6952 1
-187 7072 2
-187 1555 0
-1555 6882 1
-1555 6952 2
+187 6932 1
+187 7051 2
+187 1543 0
+1543 6862 1
+1543 6932 2
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
index dc436d123fd35..dbbbbc746a769 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
@@ -1,4 +1,4 @@
-7173
+7151
AAA 0
AAD 1
AADD 2
@@ -1440,5735 +1440,5713 @@ PSUBWrm 1437
PSUBWrr 1438
PSWAPDrm 1439
PSWAPDrr 1440
-PT 1441
-PTCMMIMFP 1442
-PTCMMRLFP 1443
-PTCONJTCMMIMFP 1444
-PTCONJTFP 1445
-PTCVTROWD 1446
-PTCVTROWPS 1447
-PTDPBF 1448
-PTDPBHF 1449
-PTDPBSSD 1450
-PTDPBSSDV 1451
-PTDPBSUD 1452
-PTDPBSUDV 1453
-PTDPBUSD 1454
-PTDPBUSDV 1455
-PTDPBUUD 1456
-PTDPBUUDV 1457
-PTDPFP 1458
-PTDPHBF 1459
-PTDPHF 1460
-PTESTrm 1461
-PTESTrr 1462
-PTILELOADD 1463
-PTILELOADDRS 1464
-PTILELOADDRST 1465
-PTILELOADDRSV 1466
-PTILELOADDT 1467
-PTILELOADDV 1468
-PTILEMOVROWrre 1469
-PTILEMOVROWrreV 1470
-PTILEMOVROWrri 1471
-PTILEMOVROWrriV 1472
-PTILEPAIRLOAD 1473
-PTILEPAIRSTORE 1474
-PTILESTORED 1475
-PTILESTOREDV 1476
-PTILEZERO 1477
-PTILEZEROV 1478
-PTMMULTF 1479
-PTTCMMIMFP 1480
-PTTCMMRLFP 1481
-PTTDPBF 1482
-PTTDPFP 1483
-PTTMMULTF 1484
-PTTRANSPOSED 1485
-PTTRANSPOSEDV 1486
-PTWRITE 1487
-PTWRITEm 1488
-PTWRITEr 1489
-PUNPCKHBWrm 1490
-PUNPCKHBWrr 1491
-PUNPCKHDQrm 1492
-PUNPCKHDQrr 1493
-PUNPCKHQDQrm 1494
-PUNPCKHQDQrr 1495
-PUNPCKHWDrm 1496
-PUNPCKHWDrr 1497
-PUNPCKLBWrm 1498
-PUNPCKLBWrr 1499
-PUNPCKLDQrm 1500
-PUNPCKLDQrr 1501
-PUNPCKLQDQrm 1502
-PUNPCKLQDQrr 1503
-PUNPCKLWDrm 1504
-PUNPCKLWDrr 1505
-PUSH 1506
-PUSHA 1507
-PUSHCS 1508
-PUSHDS 1509
-PUSHES 1510
-PUSHF 1511
-PUSHFS 1512
-PUSHGS 1513
-PUSHP 1514
-PUSHSS 1515
-PVALIDATE 1516
-PXORrm 1517
-PXORrr 1518
-RCL 1519
-RCPPSm 1520
-RCPPSr 1521
-RCPSSm 1522
-RCPSSm_Int 1523
-RCPSSr 1524
-RCPSSr_Int 1525
-RCR 1526
-RDFLAGS 1527
-RDFSBASE 1528
-RDGSBASE 1529
-RDMSR 1530
-RDMSRLIST 1531
-RDMSRri 1532
-RDMSRri_EVEX 1533
-RDPID 1534
-RDPKRUr 1535
-RDPMC 1536
-RDPRU 1537
-RDRAND 1538
-RDSEED 1539
-RDSSPD 1540
-RDSSPQ 1541
-RDTSC 1542
-RDTSCP 1543
-REG_SEQUENCE 1544
-REPNE_PREFIX 1545
-REP_MOVSB 1546
-REP_MOVSD 1547
-REP_MOVSQ 1548
-REP_MOVSW 1549
-REP_PREFIX 1550
-REP_STOSB 1551
-REP_STOSD 1552
-REP_STOSQ 1553
-REP_STOSW 1554
-RET 1555
-RETI 1556
-REX 1557
-RMPADJUST 1558
-RMPQUERY 1559
-RMPUPDATE 1560
-ROL 1561
-ROR 1562
-RORX 1563
-ROUNDPDmi 1564
-ROUNDPDri 1565
-ROUNDPSmi 1566
-ROUNDPSri 1567
-ROUNDSDmi 1568
-ROUNDSDmi_Int 1569
-ROUNDSDri 1570
-ROUNDSDri_Int 1571
-ROUNDSSmi 1572
-ROUNDSSmi_Int 1573
-ROUNDSSri 1574
-ROUNDSSri_Int 1575
-RSM 1576
-RSQRTPSm 1577
-RSQRTPSr 1578
-RSQRTSSm 1579
-RSQRTSSm_Int 1580
-RSQRTSSr 1581
-RSQRTSSr_Int 1582
-RSTORSSP 1583
-SAHF 1584
-SALC 1585
-SAR 1586
-SARX 1587
-SAVEPREVSSP 1588
-SBB 1589
-SCASB 1590
-SCASL 1591
-SCASQ 1592
-SCASW 1593
-SEAMCALL 1594
-SEAMOPS 1595
-SEAMRET 1596
-SEG_ALLOCA 1597
-SEH_BeginEpilogue 1598
-SEH_EndEpilogue 1599
-SEH_EndPrologue 1600
-SEH_PushFrame 1601
-SEH_PushReg 1602
-SEH_SaveReg 1603
-SEH_SaveXMM 1604
-SEH_SetFrame 1605
-SEH_StackAlign 1606
-SEH_StackAlloc 1607
-SEH_UnwindV 1608
-SEH_UnwindVersion 1609
-SENDUIPI 1610
-SERIALIZE 1611
-SETB_C 1612
-SETCCm 1613
-SETCCm_EVEX 1614
-SETCCr 1615
-SETCCr_EVEX 1616
-SETSSBSY 1617
-SETZUCCm 1618
-SETZUCCr 1619
-SFENCE 1620
-SGDT 1621
-SHA 1622
-SHL 1623
-SHLD 1624
-SHLDROT 1625
-SHLX 1626
-SHR 1627
-SHRD 1628
-SHRDROT 1629
-SHRX 1630
-SHUFPDrmi 1631
-SHUFPDrri 1632
-SHUFPSrmi 1633
-SHUFPSrri 1634
-SIDT 1635
-SKINIT 1636
-SLDT 1637
-SLWPCB 1638
-SMSW 1639
-SQRTPDm 1640
-SQRTPDr 1641
-SQRTPSm 1642
-SQRTPSr 1643
-SQRTSDm 1644
-SQRTSDm_Int 1645
-SQRTSDr 1646
-SQRTSDr_Int 1647
-SQRTSSm 1648
-SQRTSSm_Int 1649
-SQRTSSr 1650
-SQRTSSr_Int 1651
-SQRT_F 1652
-SQRT_Fp 1653
-SS_PREFIX 1654
-STAC 1655
-STACKALLOC_W_PROBING 1656
-STACKMAP 1657
-STATEPOINT 1658
-STC 1659
-STD 1660
-STGI 1661
-STI 1662
-STMXCSR 1663
-STOSB 1664
-STOSL 1665
-STOSQ 1666
-STOSW 1667
-STR 1668
-STRm 1669
-STTILECFG 1670
-STTILECFG_EVEX 1671
-STUI 1672
-ST_F 1673
-ST_FP 1674
-ST_FPrr 1675
-ST_Fp 1676
-ST_FpP 1677
-ST_Frr 1678
-SUB 1679
-SUBPDrm 1680
-SUBPDrr 1681
-SUBPSrm 1682
-SUBPSrr 1683
-SUBREG_TO_REG 1684
-SUBR_F 1685
-SUBR_FI 1686
-SUBR_FPrST 1687
-SUBR_FST 1688
-SUBR_Fp 1689
-SUBR_FpI 1690
-SUBR_FrST 1691
-SUBSDrm 1692
-SUBSDrm_Int 1693
-SUBSDrr 1694
-SUBSDrr_Int 1695
-SUBSSrm 1696
-SUBSSrm_Int 1697
-SUBSSrr 1698
-SUBSSrr_Int 1699
-SUB_F 1700
-SUB_FI 1701
-SUB_FPrST 1702
-SUB_FST 1703
-SUB_Fp 1704
-SUB_FpI 1705
-SUB_FrST 1706
-SWAPGS 1707
-SYSCALL 1708
-SYSENTER 1709
-SYSEXIT 1710
-SYSRET 1711
-T 1712
-TAILJMPd 1713
-TAILJMPd_CC 1714
-TAILJMPm 1715
-TAILJMPr 1716
-TCMMIMFP 1717
-TCMMRLFP 1718
-TCONJTCMMIMFP 1719
-TCONJTFP 1720
-TCRETURN_HIPE 1721
-TCRETURN_WIN 1722
-TCRETURN_WINmi 1723
-TCRETURNdi 1724
-TCRETURNdicc 1725
-TCRETURNmi 1726
-TCRETURNri 1727
-TCVTROWD 1728
-TCVTROWPS 1729
-TDCALL 1730
-TDPBF 1731
-TDPBHF 1732
-TDPBSSD 1733
-TDPBSUD 1734
-TDPBUSD 1735
-TDPBUUD 1736
-TDPFP 1737
-TDPHBF 1738
-TDPHF 1739
-TEST 1740
-TESTUI 1741
-TILELOADD 1742
-TILELOADDRS 1743
-TILELOADDRST 1744
-TILELOADDRS_EVEX 1745
-TILELOADDT 1746
-TILELOADD_EVEX 1747
-TILEMOVROWrre 1748
-TILEMOVROWrri 1749
-TILERELEASE 1750
-TILESTORED 1751
-TILESTORED_EVEX 1752
-TILEZERO 1753
-TLBSYNC 1754
-TLSCall 1755
-TLS_addr 1756
-TLS_addrX 1757
-TLS_base_addr 1758
-TLS_base_addrX 1759
-TLS_desc 1760
-TMMULTF 1761
-TPAUSE 1762
-TRAP 1763
-TST_F 1764
-TST_Fp 1765
-TTCMMIMFP 1766
-TTCMMRLFP 1767
-TTDPBF 1768
-TTDPFP 1769
-TTMMULTF 1770
-TTRANSPOSED 1771
-TZCNT 1772
-TZMSK 1773
-UBSAN_UD 1774
-UCOMISDrm 1775
-UCOMISDrm_Int 1776
-UCOMISDrr 1777
-UCOMISDrr_Int 1778
-UCOMISSrm 1779
-UCOMISSrm_Int 1780
-UCOMISSrr 1781
-UCOMISSrr_Int 1782
-UCOM_FIPr 1783
-UCOM_FIr 1784
-UCOM_FPPr 1785
-UCOM_FPr 1786
-UCOM_FpIr 1787
-UCOM_Fpr 1788
-UCOM_Fr 1789
-UD 1790
-UIRET 1791
-UMONITOR 1792
-UMWAIT 1793
-UNPCKHPDrm 1794
-UNPCKHPDrr 1795
-UNPCKHPSrm 1796
-UNPCKHPSrr 1797
-UNPCKLPDrm 1798
-UNPCKLPDrr 1799
-UNPCKLPSrm 1800
-UNPCKLPSrr 1801
-URDMSRri 1802
-URDMSRri_EVEX 1803
-URDMSRrr 1804
-URDMSRrr_EVEX 1805
-UWRMSRir 1806
-UWRMSRir_EVEX 1807
-UWRMSRrr 1808
-UWRMSRrr_EVEX 1809
-V 1810
-VAARG 1811
-VAARG_X 1812
-VADDBF 1813
-VADDPDYrm 1814
-VADDPDYrr 1815
-VADDPDZ 1816
-VADDPDZrm 1817
-VADDPDZrmb 1818
-VADDPDZrmbk 1819
-VADDPDZrmbkz 1820
-VADDPDZrmk 1821
-VADDPDZrmkz 1822
-VADDPDZrr 1823
-VADDPDZrrb 1824
-VADDPDZrrbk 1825
-VADDPDZrrbkz 1826
-VADDPDZrrk 1827
-VADDPDZrrkz 1828
-VADDPDrm 1829
-VADDPDrr 1830
-VADDPHZ 1831
-VADDPHZrm 1832
-VADDPHZrmb 1833
-VADDPHZrmbk 1834
-VADDPHZrmbkz 1835
-VADDPHZrmk 1836
-VADDPHZrmkz 1837
-VADDPHZrr 1838
-VADDPHZrrb 1839
-VADDPHZrrbk 1840
-VADDPHZrrbkz 1841
-VADDPHZrrk 1842
-VADDPHZrrkz 1843
-VADDPSYrm 1844
-VADDPSYrr 1845
-VADDPSZ 1846
-VADDPSZrm 1847
-VADDPSZrmb 1848
-VADDPSZrmbk 1849
-VADDPSZrmbkz 1850
-VADDPSZrmk 1851
-VADDPSZrmkz 1852
-VADDPSZrr 1853
-VADDPSZrrb 1854
-VADDPSZrrbk 1855
-VADDPSZrrbkz 1856
-VADDPSZrrk 1857
-VADDPSZrrkz 1858
-VADDPSrm 1859
-VADDPSrr 1860
-VADDSDZrm 1861
-VADDSDZrm_Int 1862
-VADDSDZrmk_Int 1863
-VADDSDZrmkz_Int 1864
-VADDSDZrr 1865
-VADDSDZrr_Int 1866
-VADDSDZrrb_Int 1867
-VADDSDZrrbk_Int 1868
-VADDSDZrrbkz_Int 1869
-VADDSDZrrk_Int 1870
-VADDSDZrrkz_Int 1871
-VADDSDrm 1872
-VADDSDrm_Int 1873
-VADDSDrr 1874
-VADDSDrr_Int 1875
-VADDSHZrm 1876
-VADDSHZrm_Int 1877
-VADDSHZrmk_Int 1878
-VADDSHZrmkz_Int 1879
-VADDSHZrr 1880
-VADDSHZrr_Int 1881
-VADDSHZrrb_Int 1882
-VADDSHZrrbk_Int 1883
-VADDSHZrrbkz_Int 1884
-VADDSHZrrk_Int 1885
-VADDSHZrrkz_Int 1886
-VADDSSZrm 1887
-VADDSSZrm_Int 1888
-VADDSSZrmk_Int 1889
-VADDSSZrmkz_Int 1890
-VADDSSZrr 1891
-VADDSSZrr_Int 1892
-VADDSSZrrb_Int 1893
-VADDSSZrrbk_Int 1894
-VADDSSZrrbkz_Int 1895
-VADDSSZrrk_Int 1896
-VADDSSZrrkz_Int 1897
-VADDSSrm 1898
-VADDSSrm_Int 1899
-VADDSSrr 1900
-VADDSSrr_Int 1901
-VADDSUBPDYrm 1902
-VADDSUBPDYrr 1903
-VADDSUBPDrm 1904
-VADDSUBPDrr 1905
-VADDSUBPSYrm 1906
-VADDSUBPSYrr 1907
-VADDSUBPSrm 1908
-VADDSUBPSrr 1909
-VAESDECLASTYrm 1910
-VAESDECLASTYrr 1911
-VAESDECLASTZ 1912
-VAESDECLASTZrm 1913
-VAESDECLASTZrr 1914
-VAESDECLASTrm 1915
-VAESDECLASTrr 1916
-VAESDECYrm 1917
-VAESDECYrr 1918
-VAESDECZ 1919
-VAESDECZrm 1920
-VAESDECZrr 1921
-VAESDECrm 1922
-VAESDECrr 1923
-VAESENCLASTYrm 1924
-VAESENCLASTYrr 1925
-VAESENCLASTZ 1926
-VAESENCLASTZrm 1927
-VAESENCLASTZrr 1928
-VAESENCLASTrm 1929
-VAESENCLASTrr 1930
-VAESENCYrm 1931
-VAESENCYrr 1932
-VAESENCZ 1933
-VAESENCZrm 1934
-VAESENCZrr 1935
-VAESENCrm 1936
-VAESENCrr 1937
-VAESIMCrm 1938
-VAESIMCrr 1939
-VAESKEYGENASSISTrmi 1940
-VAESKEYGENASSISTrri 1941
-VALIGNDZ 1942
-VALIGNDZrmbi 1943
-VALIGNDZrmbik 1944
-VALIGNDZrmbikz 1945
-VALIGNDZrmi 1946
-VALIGNDZrmik 1947
-VALIGNDZrmikz 1948
-VALIGNDZrri 1949
-VALIGNDZrrik 1950
-VALIGNDZrrikz 1951
-VALIGNQZ 1952
-VALIGNQZrmbi 1953
-VALIGNQZrmbik 1954
-VALIGNQZrmbikz 1955
-VALIGNQZrmi 1956
-VALIGNQZrmik 1957
-VALIGNQZrmikz 1958
-VALIGNQZrri 1959
-VALIGNQZrrik 1960
-VALIGNQZrrikz 1961
-VANDNPDYrm 1962
-VANDNPDYrr 1963
-VANDNPDZ 1964
-VANDNPDZrm 1965
-VANDNPDZrmb 1966
-VANDNPDZrmbk 1967
-VANDNPDZrmbkz 1968
-VANDNPDZrmk 1969
-VANDNPDZrmkz 1970
-VANDNPDZrr 1971
-VANDNPDZrrk 1972
-VANDNPDZrrkz 1973
-VANDNPDrm 1974
-VANDNPDrr 1975
-VANDNPSYrm 1976
-VANDNPSYrr 1977
-VANDNPSZ 1978
-VANDNPSZrm 1979
-VANDNPSZrmb 1980
-VANDNPSZrmbk 1981
-VANDNPSZrmbkz 1982
-VANDNPSZrmk 1983
-VANDNPSZrmkz 1984
-VANDNPSZrr 1985
-VANDNPSZrrk 1986
-VANDNPSZrrkz 1987
-VANDNPSrm 1988
-VANDNPSrr 1989
-VANDPDYrm 1990
-VANDPDYrr 1991
-VANDPDZ 1992
-VANDPDZrm 1993
-VANDPDZrmb 1994
-VANDPDZrmbk 1995
-VANDPDZrmbkz 1996
-VANDPDZrmk 1997
-VANDPDZrmkz 1998
-VANDPDZrr 1999
-VANDPDZrrk 2000
-VANDPDZrrkz 2001
-VANDPDrm 2002
-VANDPDrr 2003
-VANDPSYrm 2004
-VANDPSYrr 2005
-VANDPSZ 2006
-VANDPSZrm 2007
-VANDPSZrmb 2008
-VANDPSZrmbk 2009
-VANDPSZrmbkz 2010
-VANDPSZrmk 2011
-VANDPSZrmkz 2012
-VANDPSZrr 2013
-VANDPSZrrk 2014
-VANDPSZrrkz 2015
-VANDPSrm 2016
-VANDPSrr 2017
-VASTART_SAVE_XMM_REGS 2018
-VBCSTNEBF 2019
-VBCSTNESH 2020
-VBLENDMPDZ 2021
-VBLENDMPDZrm 2022
-VBLENDMPDZrmb 2023
-VBLENDMPDZrmbk 2024
-VBLENDMPDZrmbkz 2025
-VBLENDMPDZrmk 2026
-VBLENDMPDZrmkz 2027
-VBLENDMPDZrr 2028
-VBLENDMPDZrrk 2029
-VBLENDMPDZrrkz 2030
-VBLENDMPSZ 2031
-VBLENDMPSZrm 2032
-VBLENDMPSZrmb 2033
-VBLENDMPSZrmbk 2034
-VBLENDMPSZrmbkz 2035
-VBLENDMPSZrmk 2036
-VBLENDMPSZrmkz 2037
-VBLENDMPSZrr 2038
-VBLENDMPSZrrk 2039
-VBLENDMPSZrrkz 2040
-VBLENDPDYrmi 2041
-VBLENDPDYrri 2042
-VBLENDPDrmi 2043
-VBLENDPDrri 2044
-VBLENDPSYrmi 2045
-VBLENDPSYrri 2046
-VBLENDPSrmi 2047
-VBLENDPSrri 2048
-VBLENDVPDYrmr 2049
-VBLENDVPDYrrr 2050
-VBLENDVPDrmr 2051
-VBLENDVPDrrr 2052
-VBLENDVPSYrmr 2053
-VBLENDVPSYrrr 2054
-VBLENDVPSrmr 2055
-VBLENDVPSrrr 2056
-VBROADCASTF 2057
-VBROADCASTI 2058
-VBROADCASTSDYrm 2059
-VBROADCASTSDYrr 2060
-VBROADCASTSDZ 2061
-VBROADCASTSDZrm 2062
-VBROADCASTSDZrmk 2063
-VBROADCASTSDZrmkz 2064
-VBROADCASTSDZrr 2065
-VBROADCASTSDZrrk 2066
-VBROADCASTSDZrrkz 2067
-VBROADCASTSSYrm 2068
-VBROADCASTSSYrr 2069
-VBROADCASTSSZ 2070
-VBROADCASTSSZrm 2071
-VBROADCASTSSZrmk 2072
-VBROADCASTSSZrmkz 2073
-VBROADCASTSSZrr 2074
-VBROADCASTSSZrrk 2075
-VBROADCASTSSZrrkz 2076
-VBROADCASTSSrm 2077
-VBROADCASTSSrr 2078
-VCMPBF 2079
-VCMPPDYrmi 2080
-VCMPPDYrri 2081
-VCMPPDZ 2082
-VCMPPDZrmbi 2083
-VCMPPDZrmbik 2084
-VCMPPDZrmi 2085
-VCMPPDZrmik 2086
-VCMPPDZrri 2087
-VCMPPDZrrib 2088
-VCMPPDZrribk 2089
-VCMPPDZrrik 2090
-VCMPPDrmi 2091
-VCMPPDrri 2092
-VCMPPHZ 2093
-VCMPPHZrmbi 2094
-VCMPPHZrmbik 2095
-VCMPPHZrmi 2096
-VCMPPHZrmik 2097
-VCMPPHZrri 2098
-VCMPPHZrrib 2099
-VCMPPHZrribk 2100
-VCMPPHZrrik 2101
-VCMPPSYrmi 2102
-VCMPPSYrri 2103
-VCMPPSZ 2104
-VCMPPSZrmbi 2105
-VCMPPSZrmbik 2106
-VCMPPSZrmi 2107
-VCMPPSZrmik 2108
-VCMPPSZrri 2109
-VCMPPSZrrib 2110
-VCMPPSZrribk 2111
-VCMPPSZrrik 2112
-VCMPPSrmi 2113
-VCMPPSrri 2114
-VCMPSDZrmi 2115
-VCMPSDZrmi_Int 2116
-VCMPSDZrmik_Int 2117
-VCMPSDZrri 2118
-VCMPSDZrri_Int 2119
-VCMPSDZrrib_Int 2120
-VCMPSDZrribk_Int 2121
-VCMPSDZrrik_Int 2122
-VCMPSDrmi 2123
-VCMPSDrmi_Int 2124
-VCMPSDrri 2125
-VCMPSDrri_Int 2126
-VCMPSHZrmi 2127
-VCMPSHZrmi_Int 2128
-VCMPSHZrmik_Int 2129
-VCMPSHZrri 2130
-VCMPSHZrri_Int 2131
-VCMPSHZrrib_Int 2132
-VCMPSHZrribk_Int 2133
-VCMPSHZrrik_Int 2134
-VCMPSSZrmi 2135
-VCMPSSZrmi_Int 2136
-VCMPSSZrmik_Int 2137
-VCMPSSZrri 2138
-VCMPSSZrri_Int 2139
-VCMPSSZrrib_Int 2140
-VCMPSSZrribk_Int 2141
-VCMPSSZrrik_Int 2142
-VCMPSSrmi 2143
-VCMPSSrmi_Int 2144
-VCMPSSrri 2145
-VCMPSSrri_Int 2146
-VCOMISBF 2147
-VCOMISDZrm 2148
-VCOMISDZrm_Int 2149
-VCOMISDZrr 2150
-VCOMISDZrr_Int 2151
-VCOMISDZrrb 2152
-VCOMISDrm 2153
-VCOMISDrm_Int 2154
-VCOMISDrr 2155
-VCOMISDrr_Int 2156
-VCOMISHZrm 2157
-VCOMISHZrm_Int 2158
-VCOMISHZrr 2159
-VCOMISHZrr_Int 2160
-VCOMISHZrrb 2161
-VCOMISSZrm 2162
-VCOMISSZrm_Int 2163
-VCOMISSZrr 2164
-VCOMISSZrr_Int 2165
-VCOMISSZrrb 2166
-VCOMISSrm 2167
-VCOMISSrm_Int 2168
-VCOMISSrr 2169
-VCOMISSrr_Int 2170
-VCOMPRESSPDZ 2171
-VCOMPRESSPDZmr 2172
-VCOMPRESSPDZmrk 2173
-VCOMPRESSPDZrr 2174
-VCOMPRESSPDZrrk 2175
-VCOMPRESSPDZrrkz 2176
-VCOMPRESSPSZ 2177
-VCOMPRESSPSZmr 2178
-VCOMPRESSPSZmrk 2179
-VCOMPRESSPSZrr 2180
-VCOMPRESSPSZrrk 2181
-VCOMPRESSPSZrrkz 2182
-VCOMXSDZrm_Int 2183
-VCOMXSDZrr_Int 2184
-VCOMXSDZrrb_Int 2185
-VCOMXSHZrm_Int 2186
-VCOMXSHZrr_Int 2187
-VCOMXSHZrrb_Int 2188
-VCOMXSSZrm_Int 2189
-VCOMXSSZrr_Int 2190
-VCOMXSSZrrb_Int 2191
-VCVT 2192
-VCVTBF 2193
-VCVTBIASPH 2194
-VCVTDQ 2195
-VCVTHF 2196
-VCVTNE 2197
-VCVTNEEBF 2198
-VCVTNEEPH 2199
-VCVTNEOBF 2200
-VCVTNEOPH 2201
-VCVTNEPS 2202
-VCVTPD 2203
-VCVTPH 2204
-VCVTPS 2205
-VCVTQQ 2206
-VCVTSD 2207
-VCVTSH 2208
-VCVTSI 2209
-VCVTSS 2210
-VCVTTBF 2211
-VCVTTPD 2212
-VCVTTPH 2213
-VCVTTPS 2214
-VCVTTSD 2215
-VCVTTSH 2216
-VCVTTSS 2217
-VCVTUDQ 2218
-VCVTUQQ 2219
-VCVTUSI 2220
-VCVTUW 2221
-VCVTW 2222
-VDBPSADBWZ 2223
-VDBPSADBWZrmi 2224
-VDBPSADBWZrmik 2225
-VDBPSADBWZrmikz 2226
-VDBPSADBWZrri 2227
-VDBPSADBWZrrik 2228
-VDBPSADBWZrrikz 2229
-VDIVBF 2230
-VDIVPDYrm 2231
-VDIVPDYrr 2232
-VDIVPDZ 2233
-VDIVPDZrm 2234
-VDIVPDZrmb 2235
-VDIVPDZrmbk 2236
-VDIVPDZrmbkz 2237
-VDIVPDZrmk 2238
-VDIVPDZrmkz 2239
-VDIVPDZrr 2240
-VDIVPDZrrb 2241
-VDIVPDZrrbk 2242
-VDIVPDZrrbkz 2243
-VDIVPDZrrk 2244
-VDIVPDZrrkz 2245
-VDIVPDrm 2246
-VDIVPDrr 2247
-VDIVPHZ 2248
-VDIVPHZrm 2249
-VDIVPHZrmb 2250
-VDIVPHZrmbk 2251
-VDIVPHZrmbkz 2252
-VDIVPHZrmk 2253
-VDIVPHZrmkz 2254
-VDIVPHZrr 2255
-VDIVPHZrrb 2256
-VDIVPHZrrbk 2257
-VDIVPHZrrbkz 2258
-VDIVPHZrrk 2259
-VDIVPHZrrkz 2260
-VDIVPSYrm 2261
-VDIVPSYrr 2262
-VDIVPSZ 2263
-VDIVPSZrm 2264
-VDIVPSZrmb 2265
-VDIVPSZrmbk 2266
-VDIVPSZrmbkz 2267
-VDIVPSZrmk 2268
-VDIVPSZrmkz 2269
-VDIVPSZrr 2270
-VDIVPSZrrb 2271
-VDIVPSZrrbk 2272
-VDIVPSZrrbkz 2273
-VDIVPSZrrk 2274
-VDIVPSZrrkz 2275
-VDIVPSrm 2276
-VDIVPSrr 2277
-VDIVSDZrm 2278
-VDIVSDZrm_Int 2279
-VDIVSDZrmk_Int 2280
-VDIVSDZrmkz_Int 2281
-VDIVSDZrr 2282
-VDIVSDZrr_Int 2283
-VDIVSDZrrb_Int 2284
-VDIVSDZrrbk_Int 2285
-VDIVSDZrrbkz_Int 2286
-VDIVSDZrrk_Int 2287
-VDIVSDZrrkz_Int 2288
-VDIVSDrm 2289
-VDIVSDrm_Int 2290
-VDIVSDrr 2291
-VDIVSDrr_Int 2292
-VDIVSHZrm 2293
-VDIVSHZrm_Int 2294
-VDIVSHZrmk_Int 2295
-VDIVSHZrmkz_Int 2296
-VDIVSHZrr 2297
-VDIVSHZrr_Int 2298
-VDIVSHZrrb_Int 2299
-VDIVSHZrrbk_Int 2300
-VDIVSHZrrbkz_Int 2301
-VDIVSHZrrk_Int 2302
-VDIVSHZrrkz_Int 2303
-VDIVSSZrm 2304
-VDIVSSZrm_Int 2305
-VDIVSSZrmk_Int 2306
-VDIVSSZrmkz_Int 2307
-VDIVSSZrr 2308
-VDIVSSZrr_Int 2309
-VDIVSSZrrb_Int 2310
-VDIVSSZrrbk_Int 2311
-VDIVSSZrrbkz_Int 2312
-VDIVSSZrrk_Int 2313
-VDIVSSZrrkz_Int 2314
-VDIVSSrm 2315
-VDIVSSrm_Int 2316
-VDIVSSrr 2317
-VDIVSSrr_Int 2318
-VDPBF 2319
-VDPPDrmi 2320
-VDPPDrri 2321
-VDPPHPSZ 2322
-VDPPHPSZm 2323
-VDPPHPSZmb 2324
-VDPPHPSZmbk 2325
-VDPPHPSZmbkz 2326
-VDPPHPSZmk 2327
-VDPPHPSZmkz 2328
-VDPPHPSZr 2329
-VDPPHPSZrk 2330
-VDPPHPSZrkz 2331
-VDPPSYrmi 2332
-VDPPSYrri 2333
-VDPPSrmi 2334
-VDPPSrri 2335
-VERRm 2336
-VERRr 2337
-VERWm 2338
-VERWr 2339
-VEXP 2340
-VEXPANDPDZ 2341
-VEXPANDPDZrm 2342
-VEXPANDPDZrmk 2343
-VEXPANDPDZrmkz 2344
-VEXPANDPDZrr 2345
-VEXPANDPDZrrk 2346
-VEXPANDPDZrrkz 2347
-VEXPANDPSZ 2348
-VEXPANDPSZrm 2349
-VEXPANDPSZrmk 2350
-VEXPANDPSZrmkz 2351
-VEXPANDPSZrr 2352
-VEXPANDPSZrrk 2353
-VEXPANDPSZrrkz 2354
-VEXTRACTF 2355
-VEXTRACTI 2356
-VEXTRACTPSZmri 2357
-VEXTRACTPSZrri 2358
-VEXTRACTPSmri 2359
-VEXTRACTPSrri 2360
-VFCMADDCPHZ 2361
-VFCMADDCPHZm 2362
-VFCMADDCPHZmb 2363
-VFCMADDCPHZmbk 2364
-VFCMADDCPHZmbkz 2365
-VFCMADDCPHZmk 2366
-VFCMADDCPHZmkz 2367
-VFCMADDCPHZr 2368
-VFCMADDCPHZrb 2369
-VFCMADDCPHZrbk 2370
-VFCMADDCPHZrbkz 2371
-VFCMADDCPHZrk 2372
-VFCMADDCPHZrkz 2373
-VFCMADDCSHZm 2374
-VFCMADDCSHZmk 2375
-VFCMADDCSHZmkz 2376
-VFCMADDCSHZr 2377
-VFCMADDCSHZrb 2378
-VFCMADDCSHZrbk 2379
-VFCMADDCSHZrbkz 2380
-VFCMADDCSHZrk 2381
-VFCMADDCSHZrkz 2382
-VFCMULCPHZ 2383
-VFCMULCPHZrm 2384
-VFCMULCPHZrmb 2385
-VFCMULCPHZrmbk 2386
-VFCMULCPHZrmbkz 2387
-VFCMULCPHZrmk 2388
-VFCMULCPHZrmkz 2389
-VFCMULCPHZrr 2390
-VFCMULCPHZrrb 2391
-VFCMULCPHZrrbk 2392
-VFCMULCPHZrrbkz 2393
-VFCMULCPHZrrk 2394
-VFCMULCPHZrrkz 2395
-VFCMULCSHZrm 2396
-VFCMULCSHZrmk 2397
-VFCMULCSHZrmkz 2398
-VFCMULCSHZrr 2399
-VFCMULCSHZrrb 2400
-VFCMULCSHZrrbk 2401
-VFCMULCSHZrrbkz 2402
-VFCMULCSHZrrk 2403
-VFCMULCSHZrrkz 2404
-VFIXUPIMMPDZ 2405
-VFIXUPIMMPDZrmbi 2406
-VFIXUPIMMPDZrmbik 2407
-VFIXUPIMMPDZrmbikz 2408
-VFIXUPIMMPDZrmi 2409
-VFIXUPIMMPDZrmik 2410
-VFIXUPIMMPDZrmikz 2411
-VFIXUPIMMPDZrri 2412
-VFIXUPIMMPDZrrib 2413
-VFIXUPIMMPDZrribk 2414
-VFIXUPIMMPDZrribkz 2415
-VFIXUPIMMPDZrrik 2416
-VFIXUPIMMPDZrrikz 2417
-VFIXUPIMMPSZ 2418
-VFIXUPIMMPSZrmbi 2419
-VFIXUPIMMPSZrmbik 2420
-VFIXUPIMMPSZrmbikz 2421
-VFIXUPIMMPSZrmi 2422
-VFIXUPIMMPSZrmik 2423
-VFIXUPIMMPSZrmikz 2424
-VFIXUPIMMPSZrri 2425
-VFIXUPIMMPSZrrib 2426
-VFIXUPIMMPSZrribk 2427
-VFIXUPIMMPSZrribkz 2428
-VFIXUPIMMPSZrrik 2429
-VFIXUPIMMPSZrrikz 2430
-VFIXUPIMMSDZrmi 2431
-VFIXUPIMMSDZrmik 2432
-VFIXUPIMMSDZrmikz 2433
-VFIXUPIMMSDZrri 2434
-VFIXUPIMMSDZrrib 2435
-VFIXUPIMMSDZrribk 2436
-VFIXUPIMMSDZrribkz 2437
-VFIXUPIMMSDZrrik 2438
-VFIXUPIMMSDZrrikz 2439
-VFIXUPIMMSSZrmi 2440
-VFIXUPIMMSSZrmik 2441
-VFIXUPIMMSSZrmikz 2442
-VFIXUPIMMSSZrri 2443
-VFIXUPIMMSSZrrib 2444
-VFIXUPIMMSSZrribk 2445
-VFIXUPIMMSSZrribkz 2446
-VFIXUPIMMSSZrrik 2447
-VFIXUPIMMSSZrrikz 2448
-VFMADD 2449
-VFMADDCPHZ 2450
-VFMADDCPHZm 2451
-VFMADDCPHZmb 2452
-VFMADDCPHZmbk 2453
-VFMADDCPHZmbkz 2454
-VFMADDCPHZmk 2455
-VFMADDCPHZmkz 2456
-VFMADDCPHZr 2457
-VFMADDCPHZrb 2458
-VFMADDCPHZrbk 2459
-VFMADDCPHZrbkz 2460
-VFMADDCPHZrk 2461
-VFMADDCPHZrkz 2462
-VFMADDCSHZm 2463
-VFMADDCSHZmk 2464
-VFMADDCSHZmkz 2465
-VFMADDCSHZr 2466
-VFMADDCSHZrb 2467
-VFMADDCSHZrbk 2468
-VFMADDCSHZrbkz 2469
-VFMADDCSHZrk 2470
-VFMADDCSHZrkz 2471
-VFMADDPD 2472
-VFMADDPS 2473
-VFMADDSD 2474
-VFMADDSS 2475
-VFMADDSUB 2476
-VFMADDSUBPD 2477
-VFMADDSUBPS 2478
-VFMSUB 2479
-VFMSUBADD 2480
-VFMSUBADDPD 2481
-VFMSUBADDPS 2482
-VFMSUBPD 2483
-VFMSUBPS 2484
-VFMSUBSD 2485
-VFMSUBSS 2486
-VFMULCPHZ 2487
-VFMULCPHZrm 2488
-VFMULCPHZrmb 2489
-VFMULCPHZrmbk 2490
-VFMULCPHZrmbkz 2491
-VFMULCPHZrmk 2492
-VFMULCPHZrmkz 2493
-VFMULCPHZrr 2494
-VFMULCPHZrrb 2495
-VFMULCPHZrrbk 2496
-VFMULCPHZrrbkz 2497
-VFMULCPHZrrk 2498
-VFMULCPHZrrkz 2499
-VFMULCSHZrm 2500
-VFMULCSHZrmk 2501
-VFMULCSHZrmkz 2502
-VFMULCSHZrr 2503
-VFMULCSHZrrb 2504
-VFMULCSHZrrbk 2505
-VFMULCSHZrrbkz 2506
-VFMULCSHZrrk 2507
-VFMULCSHZrrkz 2508
-VFNMADD 2509
-VFNMADDPD 2510
-VFNMADDPS 2511
-VFNMADDSD 2512
-VFNMADDSS 2513
-VFNMSUB 2514
-VFNMSUBPD 2515
-VFNMSUBPS 2516
-VFNMSUBSD 2517
-VFNMSUBSS 2518
-VFPCLASSBF 2519
-VFPCLASSPDZ 2520
-VFPCLASSPDZmbi 2521
-VFPCLASSPDZmbik 2522
-VFPCLASSPDZmi 2523
-VFPCLASSPDZmik 2524
-VFPCLASSPDZri 2525
-VFPCLASSPDZrik 2526
-VFPCLASSPHZ 2527
-VFPCLASSPHZmbi 2528
-VFPCLASSPHZmbik 2529
-VFPCLASSPHZmi 2530
-VFPCLASSPHZmik 2531
-VFPCLASSPHZri 2532
-VFPCLASSPHZrik 2533
-VFPCLASSPSZ 2534
-VFPCLASSPSZmbi 2535
-VFPCLASSPSZmbik 2536
-VFPCLASSPSZmi 2537
-VFPCLASSPSZmik 2538
-VFPCLASSPSZri 2539
-VFPCLASSPSZrik 2540
-VFPCLASSSDZmi 2541
-VFPCLASSSDZmik 2542
-VFPCLASSSDZri 2543
-VFPCLASSSDZrik 2544
-VFPCLASSSHZmi 2545
-VFPCLASSSHZmik 2546
-VFPCLASSSHZri 2547
-VFPCLASSSHZrik 2548
-VFPCLASSSSZmi 2549
-VFPCLASSSSZmik 2550
-VFPCLASSSSZri 2551
-VFPCLASSSSZrik 2552
-VFRCZPDYrm 2553
-VFRCZPDYrr 2554
-VFRCZPDrm 2555
-VFRCZPDrr 2556
-VFRCZPSYrm 2557
-VFRCZPSYrr 2558
-VFRCZPSrm 2559
-VFRCZPSrr 2560
-VFRCZSDrm 2561
-VFRCZSDrr 2562
-VFRCZSSrm 2563
-VFRCZSSrr 2564
-VGATHERDPDYrm 2565
-VGATHERDPDZ 2566
-VGATHERDPDZrm 2567
-VGATHERDPDrm 2568
-VGATHERDPSYrm 2569
-VGATHERDPSZ 2570
-VGATHERDPSZrm 2571
-VGATHERDPSrm 2572
-VGATHERPF 2573
-VGATHERQPDYrm 2574
-VGATHERQPDZ 2575
-VGATHERQPDZrm 2576
-VGATHERQPDrm 2577
-VGATHERQPSYrm 2578
-VGATHERQPSZ 2579
-VGATHERQPSZrm 2580
-VGATHERQPSrm 2581
-VGETEXPBF 2582
-VGETEXPPDZ 2583
-VGETEXPPDZm 2584
-VGETEXPPDZmb 2585
-VGETEXPPDZmbk 2586
-VGETEXPPDZmbkz 2587
-VGETEXPPDZmk 2588
-VGETEXPPDZmkz 2589
-VGETEXPPDZr 2590
-VGETEXPPDZrb 2591
-VGETEXPPDZrbk 2592
-VGETEXPPDZrbkz 2593
-VGETEXPPDZrk 2594
-VGETEXPPDZrkz 2595
-VGETEXPPHZ 2596
-VGETEXPPHZm 2597
-VGETEXPPHZmb 2598
-VGETEXPPHZmbk 2599
-VGETEXPPHZmbkz 2600
-VGETEXPPHZmk 2601
-VGETEXPPHZmkz 2602
-VGETEXPPHZr 2603
-VGETEXPPHZrb 2604
-VGETEXPPHZrbk 2605
-VGETEXPPHZrbkz 2606
-VGETEXPPHZrk 2607
-VGETEXPPHZrkz 2608
-VGETEXPPSZ 2609
-VGETEXPPSZm 2610
-VGETEXPPSZmb 2611
-VGETEXPPSZmbk 2612
-VGETEXPPSZmbkz 2613
-VGETEXPPSZmk 2614
-VGETEXPPSZmkz 2615
-VGETEXPPSZr 2616
-VGETEXPPSZrb 2617
-VGETEXPPSZrbk 2618
-VGETEXPPSZrbkz 2619
-VGETEXPPSZrk 2620
-VGETEXPPSZrkz 2621
-VGETEXPSDZm 2622
-VGETEXPSDZmk 2623
-VGETEXPSDZmkz 2624
-VGETEXPSDZr 2625
-VGETEXPSDZrb 2626
-VGETEXPSDZrbk 2627
-VGETEXPSDZrbkz 2628
-VGETEXPSDZrk 2629
-VGETEXPSDZrkz 2630
-VGETEXPSHZm 2631
-VGETEXPSHZmk 2632
-VGETEXPSHZmkz 2633
-VGETEXPSHZr 2634
-VGETEXPSHZrb 2635
-VGETEXPSHZrbk 2636
-VGETEXPSHZrbkz 2637
-VGETEXPSHZrk 2638
-VGETEXPSHZrkz 2639
-VGETEXPSSZm 2640
-VGETEXPSSZmk 2641
-VGETEXPSSZmkz 2642
-VGETEXPSSZr 2643
-VGETEXPSSZrb 2644
-VGETEXPSSZrbk 2645
-VGETEXPSSZrbkz 2646
-VGETEXPSSZrk 2647
-VGETEXPSSZrkz 2648
-VGETMANTBF 2649
-VGETMANTPDZ 2650
-VGETMANTPDZrmbi 2651
-VGETMANTPDZrmbik 2652
-VGETMANTPDZrmbikz 2653
-VGETMANTPDZrmi 2654
-VGETMANTPDZrmik 2655
-VGETMANTPDZrmikz 2656
-VGETMANTPDZrri 2657
-VGETMANTPDZrrib 2658
-VGETMANTPDZrribk 2659
-VGETMANTPDZrribkz 2660
-VGETMANTPDZrrik 2661
-VGETMANTPDZrrikz 2662
-VGETMANTPHZ 2663
-VGETMANTPHZrmbi 2664
-VGETMANTPHZrmbik 2665
-VGETMANTPHZrmbikz 2666
-VGETMANTPHZrmi 2667
-VGETMANTPHZrmik 2668
-VGETMANTPHZrmikz 2669
-VGETMANTPHZrri 2670
-VGETMANTPHZrrib 2671
-VGETMANTPHZrribk 2672
-VGETMANTPHZrribkz 2673
-VGETMANTPHZrrik 2674
-VGETMANTPHZrrikz 2675
-VGETMANTPSZ 2676
-VGETMANTPSZrmbi 2677
-VGETMANTPSZrmbik 2678
-VGETMANTPSZrmbikz 2679
-VGETMANTPSZrmi 2680
-VGETMANTPSZrmik 2681
-VGETMANTPSZrmikz 2682
-VGETMANTPSZrri 2683
-VGETMANTPSZrrib 2684
-VGETMANTPSZrribk 2685
-VGETMANTPSZrribkz 2686
-VGETMANTPSZrrik 2687
-VGETMANTPSZrrikz 2688
-VGETMANTSDZrmi 2689
-VGETMANTSDZrmik 2690
-VGETMANTSDZrmikz 2691
-VGETMANTSDZrri 2692
-VGETMANTSDZrrib 2693
-VGETMANTSDZrribk 2694
-VGETMANTSDZrribkz 2695
-VGETMANTSDZrrik 2696
-VGETMANTSDZrrikz 2697
-VGETMANTSHZrmi 2698
-VGETMANTSHZrmik 2699
-VGETMANTSHZrmikz 2700
-VGETMANTSHZrri 2701
-VGETMANTSHZrrib 2702
-VGETMANTSHZrribk 2703
-VGETMANTSHZrribkz 2704
-VGETMANTSHZrrik 2705
-VGETMANTSHZrrikz 2706
-VGETMANTSSZrmi 2707
-VGETMANTSSZrmik 2708
-VGETMANTSSZrmikz 2709
-VGETMANTSSZrri 2710
-VGETMANTSSZrrib 2711
-VGETMANTSSZrribk 2712
-VGETMANTSSZrribkz 2713
-VGETMANTSSZrrik 2714
-VGETMANTSSZrrikz 2715
-VGF 2716
-VHADDPDYrm 2717
-VHADDPDYrr 2718
-VHADDPDrm 2719
-VHADDPDrr 2720
-VHADDPSYrm 2721
-VHADDPSYrr 2722
-VHADDPSrm 2723
-VHADDPSrr 2724
-VHSUBPDYrm 2725
-VHSUBPDYrr 2726
-VHSUBPDrm 2727
-VHSUBPDrr 2728
-VHSUBPSYrm 2729
-VHSUBPSYrr 2730
-VHSUBPSrm 2731
-VHSUBPSrr 2732
-VINSERTF 2733
-VINSERTI 2734
-VINSERTPSZrmi 2735
-VINSERTPSZrri 2736
-VINSERTPSrmi 2737
-VINSERTPSrri 2738
-VLDDQUYrm 2739
-VLDDQUrm 2740
-VLDMXCSR 2741
-VMASKMOVDQU 2742
-VMASKMOVPDYmr 2743
-VMASKMOVPDYrm 2744
-VMASKMOVPDmr 2745
-VMASKMOVPDrm 2746
-VMASKMOVPSYmr 2747
-VMASKMOVPSYrm 2748
-VMASKMOVPSmr 2749
-VMASKMOVPSrm 2750
-VMAXBF 2751
-VMAXCPDYrm 2752
-VMAXCPDYrr 2753
-VMAXCPDZ 2754
-VMAXCPDZrm 2755
-VMAXCPDZrmb 2756
-VMAXCPDZrmbk 2757
-VMAXCPDZrmbkz 2758
-VMAXCPDZrmk 2759
-VMAXCPDZrmkz 2760
-VMAXCPDZrr 2761
-VMAXCPDZrrk 2762
-VMAXCPDZrrkz 2763
-VMAXCPDrm 2764
-VMAXCPDrr 2765
-VMAXCPHZ 2766
-VMAXCPHZrm 2767
-VMAXCPHZrmb 2768
-VMAXCPHZrmbk 2769
-VMAXCPHZrmbkz 2770
-VMAXCPHZrmk 2771
-VMAXCPHZrmkz 2772
-VMAXCPHZrr 2773
-VMAXCPHZrrk 2774
-VMAXCPHZrrkz 2775
-VMAXCPSYrm 2776
-VMAXCPSYrr 2777
-VMAXCPSZ 2778
-VMAXCPSZrm 2779
-VMAXCPSZrmb 2780
-VMAXCPSZrmbk 2781
-VMAXCPSZrmbkz 2782
-VMAXCPSZrmk 2783
-VMAXCPSZrmkz 2784
-VMAXCPSZrr 2785
-VMAXCPSZrrk 2786
-VMAXCPSZrrkz 2787
-VMAXCPSrm 2788
-VMAXCPSrr 2789
-VMAXCSDZrm 2790
-VMAXCSDZrr 2791
-VMAXCSDrm 2792
-VMAXCSDrr 2793
-VMAXCSHZrm 2794
-VMAXCSHZrr 2795
-VMAXCSSZrm 2796
-VMAXCSSZrr 2797
-VMAXCSSrm 2798
-VMAXCSSrr 2799
-VMAXPDYrm 2800
-VMAXPDYrr 2801
-VMAXPDZ 2802
-VMAXPDZrm 2803
-VMAXPDZrmb 2804
-VMAXPDZrmbk 2805
-VMAXPDZrmbkz 2806
-VMAXPDZrmk 2807
-VMAXPDZrmkz 2808
-VMAXPDZrr 2809
-VMAXPDZrrb 2810
-VMAXPDZrrbk 2811
-VMAXPDZrrbkz 2812
-VMAXPDZrrk 2813
-VMAXPDZrrkz 2814
-VMAXPDrm 2815
-VMAXPDrr 2816
-VMAXPHZ 2817
-VMAXPHZrm 2818
-VMAXPHZrmb 2819
-VMAXPHZrmbk 2820
-VMAXPHZrmbkz 2821
-VMAXPHZrmk 2822
-VMAXPHZrmkz 2823
-VMAXPHZrr 2824
-VMAXPHZrrb 2825
-VMAXPHZrrbk 2826
-VMAXPHZrrbkz 2827
-VMAXPHZrrk 2828
-VMAXPHZrrkz 2829
-VMAXPSYrm 2830
-VMAXPSYrr 2831
-VMAXPSZ 2832
-VMAXPSZrm 2833
-VMAXPSZrmb 2834
-VMAXPSZrmbk 2835
-VMAXPSZrmbkz 2836
-VMAXPSZrmk 2837
-VMAXPSZrmkz 2838
-VMAXPSZrr 2839
-VMAXPSZrrb 2840
-VMAXPSZrrbk 2841
-VMAXPSZrrbkz 2842
-VMAXPSZrrk 2843
-VMAXPSZrrkz 2844
-VMAXPSrm 2845
-VMAXPSrr 2846
-VMAXSDZrm 2847
-VMAXSDZrm_Int 2848
-VMAXSDZrmk_Int 2849
-VMAXSDZrmkz_Int 2850
-VMAXSDZrr 2851
-VMAXSDZrr_Int 2852
-VMAXSDZrrb_Int 2853
-VMAXSDZrrbk_Int 2854
-VMAXSDZrrbkz_Int 2855
-VMAXSDZrrk_Int 2856
-VMAXSDZrrkz_Int 2857
-VMAXSDrm 2858
-VMAXSDrm_Int 2859
-VMAXSDrr 2860
-VMAXSDrr_Int 2861
-VMAXSHZrm 2862
-VMAXSHZrm_Int 2863
-VMAXSHZrmk_Int 2864
-VMAXSHZrmkz_Int 2865
-VMAXSHZrr 2866
-VMAXSHZrr_Int 2867
-VMAXSHZrrb_Int 2868
-VMAXSHZrrbk_Int 2869
-VMAXSHZrrbkz_Int 2870
-VMAXSHZrrk_Int 2871
-VMAXSHZrrkz_Int 2872
-VMAXSSZrm 2873
-VMAXSSZrm_Int 2874
-VMAXSSZrmk_Int 2875
-VMAXSSZrmkz_Int 2876
-VMAXSSZrr 2877
-VMAXSSZrr_Int 2878
-VMAXSSZrrb_Int 2879
-VMAXSSZrrbk_Int 2880
-VMAXSSZrrbkz_Int 2881
-VMAXSSZrrk_Int 2882
-VMAXSSZrrkz_Int 2883
-VMAXSSrm 2884
-VMAXSSrm_Int 2885
-VMAXSSrr 2886
-VMAXSSrr_Int 2887
-VMCALL 2888
-VMCLEARm 2889
-VMFUNC 2890
-VMINBF 2891
-VMINCPDYrm 2892
-VMINCPDYrr 2893
-VMINCPDZ 2894
-VMINCPDZrm 2895
-VMINCPDZrmb 2896
-VMINCPDZrmbk 2897
-VMINCPDZrmbkz 2898
-VMINCPDZrmk 2899
-VMINCPDZrmkz 2900
-VMINCPDZrr 2901
-VMINCPDZrrk 2902
-VMINCPDZrrkz 2903
-VMINCPDrm 2904
-VMINCPDrr 2905
-VMINCPHZ 2906
-VMINCPHZrm 2907
-VMINCPHZrmb 2908
-VMINCPHZrmbk 2909
-VMINCPHZrmbkz 2910
-VMINCPHZrmk 2911
-VMINCPHZrmkz 2912
-VMINCPHZrr 2913
-VMINCPHZrrk 2914
-VMINCPHZrrkz 2915
-VMINCPSYrm 2916
-VMINCPSYrr 2917
-VMINCPSZ 2918
-VMINCPSZrm 2919
-VMINCPSZrmb 2920
-VMINCPSZrmbk 2921
-VMINCPSZrmbkz 2922
-VMINCPSZrmk 2923
-VMINCPSZrmkz 2924
-VMINCPSZrr 2925
-VMINCPSZrrk 2926
-VMINCPSZrrkz 2927
-VMINCPSrm 2928
-VMINCPSrr 2929
-VMINCSDZrm 2930
-VMINCSDZrr 2931
-VMINCSDrm 2932
-VMINCSDrr 2933
-VMINCSHZrm 2934
-VMINCSHZrr 2935
-VMINCSSZrm 2936
-VMINCSSZrr 2937
-VMINCSSrm 2938
-VMINCSSrr 2939
-VMINMAXBF 2940
-VMINMAXPDZ 2941
-VMINMAXPDZrmbi 2942
-VMINMAXPDZrmbik 2943
-VMINMAXPDZrmbikz 2944
-VMINMAXPDZrmi 2945
-VMINMAXPDZrmik 2946
-VMINMAXPDZrmikz 2947
-VMINMAXPDZrri 2948
-VMINMAXPDZrrib 2949
-VMINMAXPDZrribk 2950
-VMINMAXPDZrribkz 2951
-VMINMAXPDZrrik 2952
-VMINMAXPDZrrikz 2953
-VMINMAXPHZ 2954
-VMINMAXPHZrmbi 2955
-VMINMAXPHZrmbik 2956
-VMINMAXPHZrmbikz 2957
-VMINMAXPHZrmi 2958
-VMINMAXPHZrmik 2959
-VMINMAXPHZrmikz 2960
-VMINMAXPHZrri 2961
-VMINMAXPHZrrib 2962
-VMINMAXPHZrribk 2963
-VMINMAXPHZrribkz 2964
-VMINMAXPHZrrik 2965
-VMINMAXPHZrrikz 2966
-VMINMAXPSZ 2967
-VMINMAXPSZrmbi 2968
-VMINMAXPSZrmbik 2969
-VMINMAXPSZrmbikz 2970
-VMINMAXPSZrmi 2971
-VMINMAXPSZrmik 2972
-VMINMAXPSZrmikz 2973
-VMINMAXPSZrri 2974
-VMINMAXPSZrrib 2975
-VMINMAXPSZrribk 2976
-VMINMAXPSZrribkz 2977
-VMINMAXPSZrrik 2978
-VMINMAXPSZrrikz 2979
-VMINMAXSDrmi 2980
-VMINMAXSDrmi_Int 2981
-VMINMAXSDrmik_Int 2982
-VMINMAXSDrmikz_Int 2983
-VMINMAXSDrri 2984
-VMINMAXSDrri_Int 2985
-VMINMAXSDrrib_Int 2986
-VMINMAXSDrribk_Int 2987
-VMINMAXSDrribkz_Int 2988
-VMINMAXSDrrik_Int 2989
-VMINMAXSDrrikz_Int 2990
-VMINMAXSHrmi 2991
-VMINMAXSHrmi_Int 2992
-VMINMAXSHrmik_Int 2993
-VMINMAXSHrmikz_Int 2994
-VMINMAXSHrri 2995
-VMINMAXSHrri_Int 2996
-VMINMAXSHrrib_Int 2997
-VMINMAXSHrribk_Int 2998
-VMINMAXSHrribkz_Int 2999
-VMINMAXSHrrik_Int 3000
-VMINMAXSHrrikz_Int 3001
-VMINMAXSSrmi 3002
-VMINMAXSSrmi_Int 3003
-VMINMAXSSrmik_Int 3004
-VMINMAXSSrmikz_Int 3005
-VMINMAXSSrri 3006
-VMINMAXSSrri_Int 3007
-VMINMAXSSrrib_Int 3008
-VMINMAXSSrribk_Int 3009
-VMINMAXSSrribkz_Int 3010
-VMINMAXSSrrik_Int 3011
-VMINMAXSSrrikz_Int 3012
-VMINPDYrm 3013
-VMINPDYrr 3014
-VMINPDZ 3015
-VMINPDZrm 3016
-VMINPDZrmb 3017
-VMINPDZrmbk 3018
-VMINPDZrmbkz 3019
-VMINPDZrmk 3020
-VMINPDZrmkz 3021
-VMINPDZrr 3022
-VMINPDZrrb 3023
-VMINPDZrrbk 3024
-VMINPDZrrbkz 3025
-VMINPDZrrk 3026
-VMINPDZrrkz 3027
-VMINPDrm 3028
-VMINPDrr 3029
-VMINPHZ 3030
-VMINPHZrm 3031
-VMINPHZrmb 3032
-VMINPHZrmbk 3033
-VMINPHZrmbkz 3034
-VMINPHZrmk 3035
-VMINPHZrmkz 3036
-VMINPHZrr 3037
-VMINPHZrrb 3038
-VMINPHZrrbk 3039
-VMINPHZrrbkz 3040
-VMINPHZrrk 3041
-VMINPHZrrkz 3042
-VMINPSYrm 3043
-VMINPSYrr 3044
-VMINPSZ 3045
-VMINPSZrm 3046
-VMINPSZrmb 3047
-VMINPSZrmbk 3048
-VMINPSZrmbkz 3049
-VMINPSZrmk 3050
-VMINPSZrmkz 3051
-VMINPSZrr 3052
-VMINPSZrrb 3053
-VMINPSZrrbk 3054
-VMINPSZrrbkz 3055
-VMINPSZrrk 3056
-VMINPSZrrkz 3057
-VMINPSrm 3058
-VMINPSrr 3059
-VMINSDZrm 3060
-VMINSDZrm_Int 3061
-VMINSDZrmk_Int 3062
-VMINSDZrmkz_Int 3063
-VMINSDZrr 3064
-VMINSDZrr_Int 3065
-VMINSDZrrb_Int 3066
-VMINSDZrrbk_Int 3067
-VMINSDZrrbkz_Int 3068
-VMINSDZrrk_Int 3069
-VMINSDZrrkz_Int 3070
-VMINSDrm 3071
-VMINSDrm_Int 3072
-VMINSDrr 3073
-VMINSDrr_Int 3074
-VMINSHZrm 3075
-VMINSHZrm_Int 3076
-VMINSHZrmk_Int 3077
-VMINSHZrmkz_Int 3078
-VMINSHZrr 3079
-VMINSHZrr_Int 3080
-VMINSHZrrb_Int 3081
-VMINSHZrrbk_Int 3082
-VMINSHZrrbkz_Int 3083
-VMINSHZrrk_Int 3084
-VMINSHZrrkz_Int 3085
-VMINSSZrm 3086
-VMINSSZrm_Int 3087
-VMINSSZrmk_Int 3088
-VMINSSZrmkz_Int 3089
-VMINSSZrr 3090
-VMINSSZrr_Int 3091
-VMINSSZrrb_Int 3092
-VMINSSZrrbk_Int 3093
-VMINSSZrrbkz_Int 3094
-VMINSSZrrk_Int 3095
-VMINSSZrrkz_Int 3096
-VMINSSrm 3097
-VMINSSrm_Int 3098
-VMINSSrr 3099
-VMINSSrr_Int 3100
-VMLAUNCH 3101
-VMLOAD 3102
-VMMCALL 3103
-VMOV 3104
-VMOVAPDYmr 3105
-VMOVAPDYrm 3106
-VMOVAPDYrr 3107
-VMOVAPDYrr_REV 3108
-VMOVAPDZ 3109
-VMOVAPDZmr 3110
-VMOVAPDZmrk 3111
-VMOVAPDZrm 3112
-VMOVAPDZrmk 3113
-VMOVAPDZrmkz 3114
-VMOVAPDZrr 3115
-VMOVAPDZrr_REV 3116
-VMOVAPDZrrk 3117
-VMOVAPDZrrk_REV 3118
-VMOVAPDZrrkz 3119
-VMOVAPDZrrkz_REV 3120
-VMOVAPDmr 3121
-VMOVAPDrm 3122
-VMOVAPDrr 3123
-VMOVAPDrr_REV 3124
-VMOVAPSYmr 3125
-VMOVAPSYrm 3126
-VMOVAPSYrr 3127
-VMOVAPSYrr_REV 3128
-VMOVAPSZ 3129
-VMOVAPSZmr 3130
-VMOVAPSZmrk 3131
-VMOVAPSZrm 3132
-VMOVAPSZrmk 3133
-VMOVAPSZrmkz 3134
-VMOVAPSZrr 3135
-VMOVAPSZrr_REV 3136
-VMOVAPSZrrk 3137
-VMOVAPSZrrk_REV 3138
-VMOVAPSZrrkz 3139
-VMOVAPSZrrkz_REV 3140
-VMOVAPSmr 3141
-VMOVAPSrm 3142
-VMOVAPSrr 3143
-VMOVAPSrr_REV 3144
-VMOVDDUPYrm 3145
-VMOVDDUPYrr 3146
-VMOVDDUPZ 3147
-VMOVDDUPZrm 3148
-VMOVDDUPZrmk 3149
-VMOVDDUPZrmkz 3150
-VMOVDDUPZrr 3151
-VMOVDDUPZrrk 3152
-VMOVDDUPZrrkz 3153
-VMOVDDUPrm 3154
-VMOVDDUPrr 3155
-VMOVDI 3156
-VMOVDQA 3157
-VMOVDQAYmr 3158
-VMOVDQAYrm 3159
-VMOVDQAYrr 3160
-VMOVDQAYrr_REV 3161
-VMOVDQAmr 3162
-VMOVDQArm 3163
-VMOVDQArr 3164
-VMOVDQArr_REV 3165
-VMOVDQU 3166
-VMOVDQUYmr 3167
-VMOVDQUYrm 3168
-VMOVDQUYrr 3169
-VMOVDQUYrr_REV 3170
-VMOVDQUmr 3171
-VMOVDQUrm 3172
-VMOVDQUrr 3173
-VMOVDQUrr_REV 3174
-VMOVHLPSZrr 3175
-VMOVHLPSrr 3176
-VMOVHPDZ 3177
-VMOVHPDmr 3178
-VMOVHPDrm 3179
-VMOVHPSZ 3180
-VMOVHPSmr 3181
-VMOVHPSrm 3182
-VMOVLHPSZrr 3183
-VMOVLHPSrr 3184
-VMOVLPDZ 3185
-VMOVLPDmr 3186
-VMOVLPDrm 3187
-VMOVLPSZ 3188
-VMOVLPSmr 3189
-VMOVLPSrm 3190
-VMOVMSKPDYrr 3191
-VMOVMSKPDrr 3192
-VMOVMSKPSYrr 3193
-VMOVMSKPSrr 3194
-VMOVNTDQAYrm 3195
-VMOVNTDQAZ 3196
-VMOVNTDQAZrm 3197
-VMOVNTDQArm 3198
-VMOVNTDQYmr 3199
-VMOVNTDQZ 3200
-VMOVNTDQZmr 3201
-VMOVNTDQmr 3202
-VMOVNTPDYmr 3203
-VMOVNTPDZ 3204
-VMOVNTPDZmr 3205
-VMOVNTPDmr 3206
-VMOVNTPSYmr 3207
-VMOVNTPSZ 3208
-VMOVNTPSZmr 3209
-VMOVNTPSmr 3210
-VMOVPDI 3211
-VMOVPQI 3212
-VMOVPQIto 3213
-VMOVQI 3214
-VMOVRSBZ 3215
-VMOVRSBZm 3216
-VMOVRSBZmk 3217
-VMOVRSBZmkz 3218
-VMOVRSDZ 3219
-VMOVRSDZm 3220
-VMOVRSDZmk 3221
-VMOVRSDZmkz 3222
-VMOVRSQZ 3223
-VMOVRSQZm 3224
-VMOVRSQZmk 3225
-VMOVRSQZmkz 3226
-VMOVRSWZ 3227
-VMOVRSWZm 3228
-VMOVRSWZmk 3229
-VMOVRSWZmkz 3230
-VMOVSDZmr 3231
-VMOVSDZmrk 3232
-VMOVSDZrm 3233
-VMOVSDZrm_alt 3234
-VMOVSDZrmk 3235
-VMOVSDZrmkz 3236
-VMOVSDZrr 3237
-VMOVSDZrr_REV 3238
-VMOVSDZrrk 3239
-VMOVSDZrrk_REV 3240
-VMOVSDZrrkz 3241
-VMOVSDZrrkz_REV 3242
-VMOVSDmr 3243
-VMOVSDrm 3244
-VMOVSDrm_alt 3245
-VMOVSDrr 3246
-VMOVSDrr_REV 3247
-VMOVSDto 3248
-VMOVSH 3249
-VMOVSHDUPYrm 3250
-VMOVSHDUPYrr 3251
-VMOVSHDUPZ 3252
-VMOVSHDUPZrm 3253
-VMOVSHDUPZrmk 3254
-VMOVSHDUPZrmkz 3255
-VMOVSHDUPZrr 3256
-VMOVSHDUPZrrk 3257
-VMOVSHDUPZrrkz 3258
-VMOVSHDUPrm 3259
-VMOVSHDUPrr 3260
-VMOVSHZmr 3261
-VMOVSHZmrk 3262
-VMOVSHZrm 3263
-VMOVSHZrm_alt 3264
-VMOVSHZrmk 3265
-VMOVSHZrmkz 3266
-VMOVSHZrr 3267
-VMOVSHZrr_REV 3268
-VMOVSHZrrk 3269
-VMOVSHZrrk_REV 3270
-VMOVSHZrrkz 3271
-VMOVSHZrrkz_REV 3272
-VMOVSHtoW 3273
-VMOVSLDUPYrm 3274
-VMOVSLDUPYrr 3275
-VMOVSLDUPZ 3276
-VMOVSLDUPZrm 3277
-VMOVSLDUPZrmk 3278
-VMOVSLDUPZrmkz 3279
-VMOVSLDUPZrr 3280
-VMOVSLDUPZrrk 3281
-VMOVSLDUPZrrkz 3282
-VMOVSLDUPrm 3283
-VMOVSLDUPrr 3284
-VMOVSS 3285
-VMOVSSZmr 3286
-VMOVSSZmrk 3287
-VMOVSSZrm 3288
-VMOVSSZrm_alt 3289
-VMOVSSZrmk 3290
-VMOVSSZrmkz 3291
-VMOVSSZrr 3292
-VMOVSSZrr_REV 3293
-VMOVSSZrrk 3294
-VMOVSSZrrk_REV 3295
-VMOVSSZrrkz 3296
-VMOVSSZrrkz_REV 3297
-VMOVSSmr 3298
-VMOVSSrm 3299
-VMOVSSrm_alt 3300
-VMOVSSrr 3301
-VMOVSSrr_REV 3302
-VMOVUPDYmr 3303
-VMOVUPDYrm 3304
-VMOVUPDYrr 3305
-VMOVUPDYrr_REV 3306
-VMOVUPDZ 3307
-VMOVUPDZmr 3308
-VMOVUPDZmrk 3309
-VMOVUPDZrm 3310
-VMOVUPDZrmk 3311
-VMOVUPDZrmkz 3312
-VMOVUPDZrr 3313
-VMOVUPDZrr_REV 3314
-VMOVUPDZrrk 3315
-VMOVUPDZrrk_REV 3316
-VMOVUPDZrrkz 3317
-VMOVUPDZrrkz_REV 3318
-VMOVUPDmr 3319
-VMOVUPDrm 3320
-VMOVUPDrr 3321
-VMOVUPDrr_REV 3322
-VMOVUPSYmr 3323
-VMOVUPSYrm 3324
-VMOVUPSYrr 3325
-VMOVUPSYrr_REV 3326
-VMOVUPSZ 3327
-VMOVUPSZmr 3328
-VMOVUPSZmrk 3329
-VMOVUPSZrm 3330
-VMOVUPSZrmk 3331
-VMOVUPSZrmkz 3332
-VMOVUPSZrr 3333
-VMOVUPSZrr_REV 3334
-VMOVUPSZrrk 3335
-VMOVUPSZrrk_REV 3336
-VMOVUPSZrrkz 3337
-VMOVUPSZrrkz_REV 3338
-VMOVUPSmr 3339
-VMOVUPSrm 3340
-VMOVUPSrr 3341
-VMOVUPSrr_REV 3342
-VMOVW 3343
-VMOVWmr 3344
-VMOVWrm 3345
-VMOVZPDILo 3346
-VMOVZPQILo 3347
-VMOVZPWILo 3348
-VMPSADBWYrmi 3349
-VMPSADBWYrri 3350
-VMPSADBWZ 3351
-VMPSADBWZrmi 3352
-VMPSADBWZrmik 3353
-VMPSADBWZrmikz 3354
-VMPSADBWZrri 3355
-VMPSADBWZrrik 3356
-VMPSADBWZrrikz 3357
-VMPSADBWrmi 3358
-VMPSADBWrri 3359
-VMPTRLDm 3360
-VMPTRSTm 3361
-VMREAD 3362
-VMRESUME 3363
-VMRUN 3364
-VMSAVE 3365
-VMULBF 3366
-VMULPDYrm 3367
-VMULPDYrr 3368
-VMULPDZ 3369
-VMULPDZrm 3370
-VMULPDZrmb 3371
-VMULPDZrmbk 3372
-VMULPDZrmbkz 3373
-VMULPDZrmk 3374
-VMULPDZrmkz 3375
-VMULPDZrr 3376
-VMULPDZrrb 3377
-VMULPDZrrbk 3378
-VMULPDZrrbkz 3379
-VMULPDZrrk 3380
-VMULPDZrrkz 3381
-VMULPDrm 3382
-VMULPDrr 3383
-VMULPHZ 3384
-VMULPHZrm 3385
-VMULPHZrmb 3386
-VMULPHZrmbk 3387
-VMULPHZrmbkz 3388
-VMULPHZrmk 3389
-VMULPHZrmkz 3390
-VMULPHZrr 3391
-VMULPHZrrb 3392
-VMULPHZrrbk 3393
-VMULPHZrrbkz 3394
-VMULPHZrrk 3395
-VMULPHZrrkz 3396
-VMULPSYrm 3397
-VMULPSYrr 3398
-VMULPSZ 3399
-VMULPSZrm 3400
-VMULPSZrmb 3401
-VMULPSZrmbk 3402
-VMULPSZrmbkz 3403
-VMULPSZrmk 3404
-VMULPSZrmkz 3405
-VMULPSZrr 3406
-VMULPSZrrb 3407
-VMULPSZrrbk 3408
-VMULPSZrrbkz 3409
-VMULPSZrrk 3410
-VMULPSZrrkz 3411
-VMULPSrm 3412
-VMULPSrr 3413
-VMULSDZrm 3414
-VMULSDZrm_Int 3415
-VMULSDZrmk_Int 3416
-VMULSDZrmkz_Int 3417
-VMULSDZrr 3418
-VMULSDZrr_Int 3419
-VMULSDZrrb_Int 3420
-VMULSDZrrbk_Int 3421
-VMULSDZrrbkz_Int 3422
-VMULSDZrrk_Int 3423
-VMULSDZrrkz_Int 3424
-VMULSDrm 3425
-VMULSDrm_Int 3426
-VMULSDrr 3427
-VMULSDrr_Int 3428
-VMULSHZrm 3429
-VMULSHZrm_Int 3430
-VMULSHZrmk_Int 3431
-VMULSHZrmkz_Int 3432
-VMULSHZrr 3433
-VMULSHZrr_Int 3434
-VMULSHZrrb_Int 3435
-VMULSHZrrbk_Int 3436
-VMULSHZrrbkz_Int 3437
-VMULSHZrrk_Int 3438
-VMULSHZrrkz_Int 3439
-VMULSSZrm 3440
-VMULSSZrm_Int 3441
-VMULSSZrmk_Int 3442
-VMULSSZrmkz_Int 3443
-VMULSSZrr 3444
-VMULSSZrr_Int 3445
-VMULSSZrrb_Int 3446
-VMULSSZrrbk_Int 3447
-VMULSSZrrbkz_Int 3448
-VMULSSZrrk_Int 3449
-VMULSSZrrkz_Int 3450
-VMULSSrm 3451
-VMULSSrm_Int 3452
-VMULSSrr 3453
-VMULSSrr_Int 3454
-VMWRITE 3455
-VMXOFF 3456
-VMXON 3457
-VORPDYrm 3458
-VORPDYrr 3459
-VORPDZ 3460
-VORPDZrm 3461
-VORPDZrmb 3462
-VORPDZrmbk 3463
-VORPDZrmbkz 3464
-VORPDZrmk 3465
-VORPDZrmkz 3466
-VORPDZrr 3467
-VORPDZrrk 3468
-VORPDZrrkz 3469
-VORPDrm 3470
-VORPDrr 3471
-VORPSYrm 3472
-VORPSYrr 3473
-VORPSZ 3474
-VORPSZrm 3475
-VORPSZrmb 3476
-VORPSZrmbk 3477
-VORPSZrmbkz 3478
-VORPSZrmk 3479
-VORPSZrmkz 3480
-VORPSZrr 3481
-VORPSZrrk 3482
-VORPSZrrkz 3483
-VORPSrm 3484
-VORPSrr 3485
-VP 3486
-VPABSBYrm 3487
-VPABSBYrr 3488
-VPABSBZ 3489
-VPABSBZrm 3490
-VPABSBZrmk 3491
-VPABSBZrmkz 3492
-VPABSBZrr 3493
-VPABSBZrrk 3494
-VPABSBZrrkz 3495
-VPABSBrm 3496
-VPABSBrr 3497
-VPABSDYrm 3498
-VPABSDYrr 3499
-VPABSDZ 3500
-VPABSDZrm 3501
-VPABSDZrmb 3502
-VPABSDZrmbk 3503
-VPABSDZrmbkz 3504
-VPABSDZrmk 3505
-VPABSDZrmkz 3506
-VPABSDZrr 3507
-VPABSDZrrk 3508
-VPABSDZrrkz 3509
-VPABSDrm 3510
-VPABSDrr 3511
-VPABSQZ 3512
-VPABSQZrm 3513
-VPABSQZrmb 3514
-VPABSQZrmbk 3515
-VPABSQZrmbkz 3516
-VPABSQZrmk 3517
-VPABSQZrmkz 3518
-VPABSQZrr 3519
-VPABSQZrrk 3520
-VPABSQZrrkz 3521
-VPABSWYrm 3522
-VPABSWYrr 3523
-VPABSWZ 3524
-VPABSWZrm 3525
-VPABSWZrmk 3526
-VPABSWZrmkz 3527
-VPABSWZrr 3528
-VPABSWZrrk 3529
-VPABSWZrrkz 3530
-VPABSWrm 3531
-VPABSWrr 3532
-VPACKSSDWYrm 3533
-VPACKSSDWYrr 3534
-VPACKSSDWZ 3535
-VPACKSSDWZrm 3536
-VPACKSSDWZrmb 3537
-VPACKSSDWZrmbk 3538
-VPACKSSDWZrmbkz 3539
-VPACKSSDWZrmk 3540
-VPACKSSDWZrmkz 3541
-VPACKSSDWZrr 3542
-VPACKSSDWZrrk 3543
-VPACKSSDWZrrkz 3544
-VPACKSSDWrm 3545
-VPACKSSDWrr 3546
-VPACKSSWBYrm 3547
-VPACKSSWBYrr 3548
-VPACKSSWBZ 3549
-VPACKSSWBZrm 3550
-VPACKSSWBZrmk 3551
-VPACKSSWBZrmkz 3552
-VPACKSSWBZrr 3553
-VPACKSSWBZrrk 3554
-VPACKSSWBZrrkz 3555
-VPACKSSWBrm 3556
-VPACKSSWBrr 3557
-VPACKUSDWYrm 3558
-VPACKUSDWYrr 3559
-VPACKUSDWZ 3560
-VPACKUSDWZrm 3561
-VPACKUSDWZrmb 3562
-VPACKUSDWZrmbk 3563
-VPACKUSDWZrmbkz 3564
-VPACKUSDWZrmk 3565
-VPACKUSDWZrmkz 3566
-VPACKUSDWZrr 3567
-VPACKUSDWZrrk 3568
-VPACKUSDWZrrkz 3569
-VPACKUSDWrm 3570
-VPACKUSDWrr 3571
-VPACKUSWBYrm 3572
-VPACKUSWBYrr 3573
-VPACKUSWBZ 3574
-VPACKUSWBZrm 3575
-VPACKUSWBZrmk 3576
-VPACKUSWBZrmkz 3577
-VPACKUSWBZrr 3578
-VPACKUSWBZrrk 3579
-VPACKUSWBZrrkz 3580
-VPACKUSWBrm 3581
-VPACKUSWBrr 3582
-VPADDBYrm 3583
-VPADDBYrr 3584
-VPADDBZ 3585
-VPADDBZrm 3586
-VPADDBZrmk 3587
-VPADDBZrmkz 3588
-VPADDBZrr 3589
-VPADDBZrrk 3590
-VPADDBZrrkz 3591
-VPADDBrm 3592
-VPADDBrr 3593
-VPADDDYrm 3594
-VPADDDYrr 3595
-VPADDDZ 3596
-VPADDDZrm 3597
-VPADDDZrmb 3598
-VPADDDZrmbk 3599
-VPADDDZrmbkz 3600
-VPADDDZrmk 3601
-VPADDDZrmkz 3602
-VPADDDZrr 3603
-VPADDDZrrk 3604
-VPADDDZrrkz 3605
-VPADDDrm 3606
-VPADDDrr 3607
-VPADDQYrm 3608
-VPADDQYrr 3609
-VPADDQZ 3610
-VPADDQZrm 3611
-VPADDQZrmb 3612
-VPADDQZrmbk 3613
-VPADDQZrmbkz 3614
-VPADDQZrmk 3615
-VPADDQZrmkz 3616
-VPADDQZrr 3617
-VPADDQZrrk 3618
-VPADDQZrrkz 3619
-VPADDQrm 3620
-VPADDQrr 3621
-VPADDSBYrm 3622
-VPADDSBYrr 3623
-VPADDSBZ 3624
-VPADDSBZrm 3625
-VPADDSBZrmk 3626
-VPADDSBZrmkz 3627
-VPADDSBZrr 3628
-VPADDSBZrrk 3629
-VPADDSBZrrkz 3630
-VPADDSBrm 3631
-VPADDSBrr 3632
-VPADDSWYrm 3633
-VPADDSWYrr 3634
-VPADDSWZ 3635
-VPADDSWZrm 3636
-VPADDSWZrmk 3637
-VPADDSWZrmkz 3638
-VPADDSWZrr 3639
-VPADDSWZrrk 3640
-VPADDSWZrrkz 3641
-VPADDSWrm 3642
-VPADDSWrr 3643
-VPADDUSBYrm 3644
-VPADDUSBYrr 3645
-VPADDUSBZ 3646
-VPADDUSBZrm 3647
-VPADDUSBZrmk 3648
-VPADDUSBZrmkz 3649
-VPADDUSBZrr 3650
-VPADDUSBZrrk 3651
-VPADDUSBZrrkz 3652
-VPADDUSBrm 3653
-VPADDUSBrr 3654
-VPADDUSWYrm 3655
-VPADDUSWYrr 3656
-VPADDUSWZ 3657
-VPADDUSWZrm 3658
-VPADDUSWZrmk 3659
-VPADDUSWZrmkz 3660
-VPADDUSWZrr 3661
-VPADDUSWZrrk 3662
-VPADDUSWZrrkz 3663
-VPADDUSWrm 3664
-VPADDUSWrr 3665
-VPADDWYrm 3666
-VPADDWYrr 3667
-VPADDWZ 3668
-VPADDWZrm 3669
-VPADDWZrmk 3670
-VPADDWZrmkz 3671
-VPADDWZrr 3672
-VPADDWZrrk 3673
-VPADDWZrrkz 3674
-VPADDWrm 3675
-VPADDWrr 3676
-VPALIGNRYrmi 3677
-VPALIGNRYrri 3678
-VPALIGNRZ 3679
-VPALIGNRZrmi 3680
-VPALIGNRZrmik 3681
-VPALIGNRZrmikz 3682
-VPALIGNRZrri 3683
-VPALIGNRZrrik 3684
-VPALIGNRZrrikz 3685
-VPALIGNRrmi 3686
-VPALIGNRrri 3687
-VPANDDZ 3688
-VPANDDZrm 3689
-VPANDDZrmb 3690
-VPANDDZrmbk 3691
-VPANDDZrmbkz 3692
-VPANDDZrmk 3693
-VPANDDZrmkz 3694
-VPANDDZrr 3695
-VPANDDZrrk 3696
-VPANDDZrrkz 3697
-VPANDNDZ 3698
-VPANDNDZrm 3699
-VPANDNDZrmb 3700
-VPANDNDZrmbk 3701
-VPANDNDZrmbkz 3702
-VPANDNDZrmk 3703
-VPANDNDZrmkz 3704
-VPANDNDZrr 3705
-VPANDNDZrrk 3706
-VPANDNDZrrkz 3707
-VPANDNQZ 3708
-VPANDNQZrm 3709
-VPANDNQZrmb 3710
-VPANDNQZrmbk 3711
-VPANDNQZrmbkz 3712
-VPANDNQZrmk 3713
-VPANDNQZrmkz 3714
-VPANDNQZrr 3715
-VPANDNQZrrk 3716
-VPANDNQZrrkz 3717
-VPANDNYrm 3718
-VPANDNYrr 3719
-VPANDNrm 3720
-VPANDNrr 3721
-VPANDQZ 3722
-VPANDQZrm 3723
-VPANDQZrmb 3724
-VPANDQZrmbk 3725
-VPANDQZrmbkz 3726
-VPANDQZrmk 3727
-VPANDQZrmkz 3728
-VPANDQZrr 3729
-VPANDQZrrk 3730
-VPANDQZrrkz 3731
-VPANDYrm 3732
-VPANDYrr 3733
-VPANDrm 3734
-VPANDrr 3735
-VPAVGBYrm 3736
-VPAVGBYrr 3737
-VPAVGBZ 3738
-VPAVGBZrm 3739
-VPAVGBZrmk 3740
-VPAVGBZrmkz 3741
-VPAVGBZrr 3742
-VPAVGBZrrk 3743
-VPAVGBZrrkz 3744
-VPAVGBrm 3745
-VPAVGBrr 3746
-VPAVGWYrm 3747
-VPAVGWYrr 3748
-VPAVGWZ 3749
-VPAVGWZrm 3750
-VPAVGWZrmk 3751
-VPAVGWZrmkz 3752
-VPAVGWZrr 3753
-VPAVGWZrrk 3754
-VPAVGWZrrkz 3755
-VPAVGWrm 3756
-VPAVGWrr 3757
-VPBLENDDYrmi 3758
-VPBLENDDYrri 3759
-VPBLENDDrmi 3760
-VPBLENDDrri 3761
-VPBLENDMBZ 3762
-VPBLENDMBZrm 3763
-VPBLENDMBZrmk 3764
-VPBLENDMBZrmkz 3765
-VPBLENDMBZrr 3766
-VPBLENDMBZrrk 3767
-VPBLENDMBZrrkz 3768
-VPBLENDMDZ 3769
-VPBLENDMDZrm 3770
-VPBLENDMDZrmb 3771
-VPBLENDMDZrmbk 3772
-VPBLENDMDZrmbkz 3773
-VPBLENDMDZrmk 3774
-VPBLENDMDZrmkz 3775
-VPBLENDMDZrr 3776
-VPBLENDMDZrrk 3777
-VPBLENDMDZrrkz 3778
-VPBLENDMQZ 3779
-VPBLENDMQZrm 3780
-VPBLENDMQZrmb 3781
-VPBLENDMQZrmbk 3782
-VPBLENDMQZrmbkz 3783
-VPBLENDMQZrmk 3784
-VPBLENDMQZrmkz 3785
-VPBLENDMQZrr 3786
-VPBLENDMQZrrk 3787
-VPBLENDMQZrrkz 3788
-VPBLENDMWZ 3789
-VPBLENDMWZrm 3790
-VPBLENDMWZrmk 3791
-VPBLENDMWZrmkz 3792
-VPBLENDMWZrr 3793
-VPBLENDMWZrrk 3794
-VPBLENDMWZrrkz 3795
-VPBLENDVBYrmr 3796
-VPBLENDVBYrrr 3797
-VPBLENDVBrmr 3798
-VPBLENDVBrrr 3799
-VPBLENDWYrmi 3800
-VPBLENDWYrri 3801
-VPBLENDWrmi 3802
-VPBLENDWrri 3803
-VPBROADCASTBYrm 3804
-VPBROADCASTBYrr 3805
-VPBROADCASTBZ 3806
-VPBROADCASTBZrm 3807
-VPBROADCASTBZrmk 3808
-VPBROADCASTBZrmkz 3809
-VPBROADCASTBZrr 3810
-VPBROADCASTBZrrk 3811
-VPBROADCASTBZrrkz 3812
-VPBROADCASTBrZ 3813
-VPBROADCASTBrZrr 3814
-VPBROADCASTBrZrrk 3815
-VPBROADCASTBrZrrkz 3816
-VPBROADCASTBrm 3817
-VPBROADCASTBrr 3818
-VPBROADCASTDYrm 3819
-VPBROADCASTDYrr 3820
-VPBROADCASTDZ 3821
-VPBROADCASTDZrm 3822
-VPBROADCASTDZrmk 3823
-VPBROADCASTDZrmkz 3824
-VPBROADCASTDZrr 3825
-VPBROADCASTDZrrk 3826
-VPBROADCASTDZrrkz 3827
-VPBROADCASTDrZ 3828
-VPBROADCASTDrZrr 3829
-VPBROADCASTDrZrrk 3830
-VPBROADCASTDrZrrkz 3831
-VPBROADCASTDrm 3832
-VPBROADCASTDrr 3833
-VPBROADCASTMB 3834
-VPBROADCASTMW 3835
-VPBROADCASTQYrm 3836
-VPBROADCASTQYrr 3837
-VPBROADCASTQZ 3838
-VPBROADCASTQZrm 3839
-VPBROADCASTQZrmk 3840
-VPBROADCASTQZrmkz 3841
-VPBROADCASTQZrr 3842
-VPBROADCASTQZrrk 3843
-VPBROADCASTQZrrkz 3844
-VPBROADCASTQrZ 3845
-VPBROADCASTQrZrr 3846
-VPBROADCASTQrZrrk 3847
-VPBROADCASTQrZrrkz 3848
-VPBROADCASTQrm 3849
-VPBROADCASTQrr 3850
-VPBROADCASTWYrm 3851
-VPBROADCASTWYrr 3852
-VPBROADCASTWZ 3853
-VPBROADCASTWZrm 3854
-VPBROADCASTWZrmk 3855
-VPBROADCASTWZrmkz 3856
-VPBROADCASTWZrr 3857
-VPBROADCASTWZrrk 3858
-VPBROADCASTWZrrkz 3859
-VPBROADCASTWrZ 3860
-VPBROADCASTWrZrr 3861
-VPBROADCASTWrZrrk 3862
-VPBROADCASTWrZrrkz 3863
-VPBROADCASTWrm 3864
-VPBROADCASTWrr 3865
-VPCLMULQDQYrmi 3866
-VPCLMULQDQYrri 3867
-VPCLMULQDQZ 3868
-VPCLMULQDQZrmi 3869
-VPCLMULQDQZrri 3870
-VPCLMULQDQrmi 3871
-VPCLMULQDQrri 3872
-VPCMOVYrmr 3873
-VPCMOVYrrm 3874
-VPCMOVYrrr 3875
-VPCMOVYrrr_REV 3876
-VPCMOVrmr 3877
-VPCMOVrrm 3878
-VPCMOVrrr 3879
-VPCMOVrrr_REV 3880
-VPCMPBZ 3881
-VPCMPBZrmi 3882
-VPCMPBZrmik 3883
-VPCMPBZrri 3884
-VPCMPBZrrik 3885
-VPCMPDZ 3886
-VPCMPDZrmbi 3887
-VPCMPDZrmbik 3888
-VPCMPDZrmi 3889
-VPCMPDZrmik 3890
-VPCMPDZrri 3891
-VPCMPDZrrik 3892
-VPCMPEQBYrm 3893
-VPCMPEQBYrr 3894
-VPCMPEQBZ 3895
-VPCMPEQBZrm 3896
-VPCMPEQBZrmk 3897
-VPCMPEQBZrr 3898
-VPCMPEQBZrrk 3899
-VPCMPEQBrm 3900
-VPCMPEQBrr 3901
-VPCMPEQDYrm 3902
-VPCMPEQDYrr 3903
-VPCMPEQDZ 3904
-VPCMPEQDZrm 3905
-VPCMPEQDZrmb 3906
-VPCMPEQDZrmbk 3907
-VPCMPEQDZrmk 3908
-VPCMPEQDZrr 3909
-VPCMPEQDZrrk 3910
-VPCMPEQDrm 3911
-VPCMPEQDrr 3912
-VPCMPEQQYrm 3913
-VPCMPEQQYrr 3914
-VPCMPEQQZ 3915
-VPCMPEQQZrm 3916
-VPCMPEQQZrmb 3917
-VPCMPEQQZrmbk 3918
-VPCMPEQQZrmk 3919
-VPCMPEQQZrr 3920
-VPCMPEQQZrrk 3921
-VPCMPEQQrm 3922
-VPCMPEQQrr 3923
-VPCMPEQWYrm 3924
-VPCMPEQWYrr 3925
-VPCMPEQWZ 3926
-VPCMPEQWZrm 3927
-VPCMPEQWZrmk 3928
-VPCMPEQWZrr 3929
-VPCMPEQWZrrk 3930
-VPCMPEQWrm 3931
-VPCMPEQWrr 3932
-VPCMPESTRIrmi 3933
-VPCMPESTRIrri 3934
-VPCMPESTRMrmi 3935
-VPCMPESTRMrri 3936
-VPCMPGTBYrm 3937
-VPCMPGTBYrr 3938
-VPCMPGTBZ 3939
-VPCMPGTBZrm 3940
-VPCMPGTBZrmk 3941
-VPCMPGTBZrr 3942
-VPCMPGTBZrrk 3943
-VPCMPGTBrm 3944
-VPCMPGTBrr 3945
-VPCMPGTDYrm 3946
-VPCMPGTDYrr 3947
-VPCMPGTDZ 3948
-VPCMPGTDZrm 3949
-VPCMPGTDZrmb 3950
-VPCMPGTDZrmbk 3951
-VPCMPGTDZrmk 3952
-VPCMPGTDZrr 3953
-VPCMPGTDZrrk 3954
-VPCMPGTDrm 3955
-VPCMPGTDrr 3956
-VPCMPGTQYrm 3957
-VPCMPGTQYrr 3958
-VPCMPGTQZ 3959
-VPCMPGTQZrm 3960
-VPCMPGTQZrmb 3961
-VPCMPGTQZrmbk 3962
-VPCMPGTQZrmk 3963
-VPCMPGTQZrr 3964
-VPCMPGTQZrrk 3965
-VPCMPGTQrm 3966
-VPCMPGTQrr 3967
-VPCMPGTWYrm 3968
-VPCMPGTWYrr 3969
-VPCMPGTWZ 3970
-VPCMPGTWZrm 3971
-VPCMPGTWZrmk 3972
-VPCMPGTWZrr 3973
-VPCMPGTWZrrk 3974
-VPCMPGTWrm 3975
-VPCMPGTWrr 3976
-VPCMPISTRIrmi 3977
-VPCMPISTRIrri 3978
-VPCMPISTRMrmi 3979
-VPCMPISTRMrri 3980
-VPCMPQZ 3981
-VPCMPQZrmbi 3982
-VPCMPQZrmbik 3983
-VPCMPQZrmi 3984
-VPCMPQZrmik 3985
-VPCMPQZrri 3986
-VPCMPQZrrik 3987
-VPCMPUBZ 3988
-VPCMPUBZrmi 3989
-VPCMPUBZrmik 3990
-VPCMPUBZrri 3991
-VPCMPUBZrrik 3992
-VPCMPUDZ 3993
-VPCMPUDZrmbi 3994
-VPCMPUDZrmbik 3995
-VPCMPUDZrmi 3996
-VPCMPUDZrmik 3997
-VPCMPUDZrri 3998
-VPCMPUDZrrik 3999
-VPCMPUQZ 4000
-VPCMPUQZrmbi 4001
-VPCMPUQZrmbik 4002
-VPCMPUQZrmi 4003
-VPCMPUQZrmik 4004
-VPCMPUQZrri 4005
-VPCMPUQZrrik 4006
-VPCMPUWZ 4007
-VPCMPUWZrmi 4008
-VPCMPUWZrmik 4009
-VPCMPUWZrri 4010
-VPCMPUWZrrik 4011
-VPCMPWZ 4012
-VPCMPWZrmi 4013
-VPCMPWZrmik 4014
-VPCMPWZrri 4015
-VPCMPWZrrik 4016
-VPCOMBmi 4017
-VPCOMBri 4018
-VPCOMDmi 4019
-VPCOMDri 4020
-VPCOMPRESSBZ 4021
-VPCOMPRESSBZmr 4022
-VPCOMPRESSBZmrk 4023
-VPCOMPRESSBZrr 4024
-VPCOMPRESSBZrrk 4025
-VPCOMPRESSBZrrkz 4026
-VPCOMPRESSDZ 4027
-VPCOMPRESSDZmr 4028
-VPCOMPRESSDZmrk 4029
-VPCOMPRESSDZrr 4030
-VPCOMPRESSDZrrk 4031
-VPCOMPRESSDZrrkz 4032
-VPCOMPRESSQZ 4033
-VPCOMPRESSQZmr 4034
-VPCOMPRESSQZmrk 4035
-VPCOMPRESSQZrr 4036
-VPCOMPRESSQZrrk 4037
-VPCOMPRESSQZrrkz 4038
-VPCOMPRESSWZ 4039
-VPCOMPRESSWZmr 4040
-VPCOMPRESSWZmrk 4041
-VPCOMPRESSWZrr 4042
-VPCOMPRESSWZrrk 4043
-VPCOMPRESSWZrrkz 4044
-VPCOMQmi 4045
-VPCOMQri 4046
-VPCOMUBmi 4047
-VPCOMUBri 4048
-VPCOMUDmi 4049
-VPCOMUDri 4050
-VPCOMUQmi 4051
-VPCOMUQri 4052
-VPCOMUWmi 4053
-VPCOMUWri 4054
-VPCOMWmi 4055
-VPCOMWri 4056
-VPCONFLICTDZ 4057
-VPCONFLICTDZrm 4058
-VPCONFLICTDZrmb 4059
-VPCONFLICTDZrmbk 4060
-VPCONFLICTDZrmbkz 4061
-VPCONFLICTDZrmk 4062
-VPCONFLICTDZrmkz 4063
-VPCONFLICTDZrr 4064
-VPCONFLICTDZrrk 4065
-VPCONFLICTDZrrkz 4066
-VPCONFLICTQZ 4067
-VPCONFLICTQZrm 4068
-VPCONFLICTQZrmb 4069
-VPCONFLICTQZrmbk 4070
-VPCONFLICTQZrmbkz 4071
-VPCONFLICTQZrmk 4072
-VPCONFLICTQZrmkz 4073
-VPCONFLICTQZrr 4074
-VPCONFLICTQZrrk 4075
-VPCONFLICTQZrrkz 4076
-VPDPBSSDSYrm 4077
-VPDPBSSDSYrr 4078
-VPDPBSSDSZ 4079
-VPDPBSSDSZrm 4080
-VPDPBSSDSZrmb 4081
-VPDPBSSDSZrmbk 4082
-VPDPBSSDSZrmbkz 4083
-VPDPBSSDSZrmk 4084
-VPDPBSSDSZrmkz 4085
-VPDPBSSDSZrr 4086
-VPDPBSSDSZrrk 4087
-VPDPBSSDSZrrkz 4088
-VPDPBSSDSrm 4089
-VPDPBSSDSrr 4090
-VPDPBSSDYrm 4091
-VPDPBSSDYrr 4092
-VPDPBSSDZ 4093
-VPDPBSSDZrm 4094
-VPDPBSSDZrmb 4095
-VPDPBSSDZrmbk 4096
-VPDPBSSDZrmbkz 4097
-VPDPBSSDZrmk 4098
-VPDPBSSDZrmkz 4099
-VPDPBSSDZrr 4100
-VPDPBSSDZrrk 4101
-VPDPBSSDZrrkz 4102
-VPDPBSSDrm 4103
-VPDPBSSDrr 4104
-VPDPBSUDSYrm 4105
-VPDPBSUDSYrr 4106
-VPDPBSUDSZ 4107
-VPDPBSUDSZrm 4108
-VPDPBSUDSZrmb 4109
-VPDPBSUDSZrmbk 4110
-VPDPBSUDSZrmbkz 4111
-VPDPBSUDSZrmk 4112
-VPDPBSUDSZrmkz 4113
-VPDPBSUDSZrr 4114
-VPDPBSUDSZrrk 4115
-VPDPBSUDSZrrkz 4116
-VPDPBSUDSrm 4117
-VPDPBSUDSrr 4118
-VPDPBSUDYrm 4119
-VPDPBSUDYrr 4120
-VPDPBSUDZ 4121
-VPDPBSUDZrm 4122
-VPDPBSUDZrmb 4123
-VPDPBSUDZrmbk 4124
-VPDPBSUDZrmbkz 4125
-VPDPBSUDZrmk 4126
-VPDPBSUDZrmkz 4127
-VPDPBSUDZrr 4128
-VPDPBSUDZrrk 4129
-VPDPBSUDZrrkz 4130
-VPDPBSUDrm 4131
-VPDPBSUDrr 4132
-VPDPBUSDSYrm 4133
-VPDPBUSDSYrr 4134
-VPDPBUSDSZ 4135
-VPDPBUSDSZrm 4136
-VPDPBUSDSZrmb 4137
-VPDPBUSDSZrmbk 4138
-VPDPBUSDSZrmbkz 4139
-VPDPBUSDSZrmk 4140
-VPDPBUSDSZrmkz 4141
-VPDPBUSDSZrr 4142
-VPDPBUSDSZrrk 4143
-VPDPBUSDSZrrkz 4144
-VPDPBUSDSrm 4145
-VPDPBUSDSrr 4146
-VPDPBUSDYrm 4147
-VPDPBUSDYrr 4148
-VPDPBUSDZ 4149
-VPDPBUSDZrm 4150
-VPDPBUSDZrmb 4151
-VPDPBUSDZrmbk 4152
-VPDPBUSDZrmbkz 4153
-VPDPBUSDZrmk 4154
-VPDPBUSDZrmkz 4155
-VPDPBUSDZrr 4156
-VPDPBUSDZrrk 4157
-VPDPBUSDZrrkz 4158
-VPDPBUSDrm 4159
-VPDPBUSDrr 4160
-VPDPBUUDSYrm 4161
-VPDPBUUDSYrr 4162
-VPDPBUUDSZ 4163
-VPDPBUUDSZrm 4164
-VPDPBUUDSZrmb 4165
-VPDPBUUDSZrmbk 4166
-VPDPBUUDSZrmbkz 4167
-VPDPBUUDSZrmk 4168
-VPDPBUUDSZrmkz 4169
-VPDPBUUDSZrr 4170
-VPDPBUUDSZrrk 4171
-VPDPBUUDSZrrkz 4172
-VPDPBUUDSrm 4173
-VPDPBUUDSrr 4174
-VPDPBUUDYrm 4175
-VPDPBUUDYrr 4176
-VPDPBUUDZ 4177
-VPDPBUUDZrm 4178
-VPDPBUUDZrmb 4179
-VPDPBUUDZrmbk 4180
-VPDPBUUDZrmbkz 4181
-VPDPBUUDZrmk 4182
-VPDPBUUDZrmkz 4183
-VPDPBUUDZrr 4184
-VPDPBUUDZrrk 4185
-VPDPBUUDZrrkz 4186
-VPDPBUUDrm 4187
-VPDPBUUDrr 4188
-VPDPWSSDSYrm 4189
-VPDPWSSDSYrr 4190
-VPDPWSSDSZ 4191
-VPDPWSSDSZrm 4192
-VPDPWSSDSZrmb 4193
-VPDPWSSDSZrmbk 4194
-VPDPWSSDSZrmbkz 4195
-VPDPWSSDSZrmk 4196
-VPDPWSSDSZrmkz 4197
-VPDPWSSDSZrr 4198
-VPDPWSSDSZrrk 4199
-VPDPWSSDSZrrkz 4200
-VPDPWSSDSrm 4201
-VPDPWSSDSrr 4202
-VPDPWSSDYrm 4203
-VPDPWSSDYrr 4204
-VPDPWSSDZ 4205
-VPDPWSSDZrm 4206
-VPDPWSSDZrmb 4207
-VPDPWSSDZrmbk 4208
-VPDPWSSDZrmbkz 4209
-VPDPWSSDZrmk 4210
-VPDPWSSDZrmkz 4211
-VPDPWSSDZrr 4212
-VPDPWSSDZrrk 4213
-VPDPWSSDZrrkz 4214
-VPDPWSSDrm 4215
-VPDPWSSDrr 4216
-VPDPWSUDSYrm 4217
-VPDPWSUDSYrr 4218
-VPDPWSUDSZ 4219
-VPDPWSUDSZrm 4220
-VPDPWSUDSZrmb 4221
-VPDPWSUDSZrmbk 4222
-VPDPWSUDSZrmbkz 4223
-VPDPWSUDSZrmk 4224
-VPDPWSUDSZrmkz 4225
-VPDPWSUDSZrr 4226
-VPDPWSUDSZrrk 4227
-VPDPWSUDSZrrkz 4228
-VPDPWSUDSrm 4229
-VPDPWSUDSrr 4230
-VPDPWSUDYrm 4231
-VPDPWSUDYrr 4232
-VPDPWSUDZ 4233
-VPDPWSUDZrm 4234
-VPDPWSUDZrmb 4235
-VPDPWSUDZrmbk 4236
-VPDPWSUDZrmbkz 4237
-VPDPWSUDZrmk 4238
-VPDPWSUDZrmkz 4239
-VPDPWSUDZrr 4240
-VPDPWSUDZrrk 4241
-VPDPWSUDZrrkz 4242
-VPDPWSUDrm 4243
-VPDPWSUDrr 4244
-VPDPWUSDSYrm 4245
-VPDPWUSDSYrr 4246
-VPDPWUSDSZ 4247
-VPDPWUSDSZrm 4248
-VPDPWUSDSZrmb 4249
-VPDPWUSDSZrmbk 4250
-VPDPWUSDSZrmbkz 4251
-VPDPWUSDSZrmk 4252
-VPDPWUSDSZrmkz 4253
-VPDPWUSDSZrr 4254
-VPDPWUSDSZrrk 4255
-VPDPWUSDSZrrkz 4256
-VPDPWUSDSrm 4257
-VPDPWUSDSrr 4258
-VPDPWUSDYrm 4259
-VPDPWUSDYrr 4260
-VPDPWUSDZ 4261
-VPDPWUSDZrm 4262
-VPDPWUSDZrmb 4263
-VPDPWUSDZrmbk 4264
-VPDPWUSDZrmbkz 4265
-VPDPWUSDZrmk 4266
-VPDPWUSDZrmkz 4267
-VPDPWUSDZrr 4268
-VPDPWUSDZrrk 4269
-VPDPWUSDZrrkz 4270
-VPDPWUSDrm 4271
-VPDPWUSDrr 4272
-VPDPWUUDSYrm 4273
-VPDPWUUDSYrr 4274
-VPDPWUUDSZ 4275
-VPDPWUUDSZrm 4276
-VPDPWUUDSZrmb 4277
-VPDPWUUDSZrmbk 4278
-VPDPWUUDSZrmbkz 4279
-VPDPWUUDSZrmk 4280
-VPDPWUUDSZrmkz 4281
-VPDPWUUDSZrr 4282
-VPDPWUUDSZrrk 4283
-VPDPWUUDSZrrkz 4284
-VPDPWUUDSrm 4285
-VPDPWUUDSrr 4286
-VPDPWUUDYrm 4287
-VPDPWUUDYrr 4288
-VPDPWUUDZ 4289
-VPDPWUUDZrm 4290
-VPDPWUUDZrmb 4291
-VPDPWUUDZrmbk 4292
-VPDPWUUDZrmbkz 4293
-VPDPWUUDZrmk 4294
-VPDPWUUDZrmkz 4295
-VPDPWUUDZrr 4296
-VPDPWUUDZrrk 4297
-VPDPWUUDZrrkz 4298
-VPDPWUUDrm 4299
-VPDPWUUDrr 4300
-VPERM 4301
-VPERMBZ 4302
-VPERMBZrm 4303
-VPERMBZrmk 4304
-VPERMBZrmkz 4305
-VPERMBZrr 4306
-VPERMBZrrk 4307
-VPERMBZrrkz 4308
-VPERMDYrm 4309
-VPERMDYrr 4310
-VPERMDZ 4311
-VPERMDZrm 4312
-VPERMDZrmb 4313
-VPERMDZrmbk 4314
-VPERMDZrmbkz 4315
-VPERMDZrmk 4316
-VPERMDZrmkz 4317
-VPERMDZrr 4318
-VPERMDZrrk 4319
-VPERMDZrrkz 4320
-VPERMI 4321
-VPERMIL 4322
-VPERMILPDYmi 4323
-VPERMILPDYri 4324
-VPERMILPDYrm 4325
-VPERMILPDYrr 4326
-VPERMILPDZ 4327
-VPERMILPDZmbi 4328
-VPERMILPDZmbik 4329
-VPERMILPDZmbikz 4330
-VPERMILPDZmi 4331
-VPERMILPDZmik 4332
-VPERMILPDZmikz 4333
-VPERMILPDZri 4334
-VPERMILPDZrik 4335
-VPERMILPDZrikz 4336
-VPERMILPDZrm 4337
-VPERMILPDZrmb 4338
-VPERMILPDZrmbk 4339
-VPERMILPDZrmbkz 4340
-VPERMILPDZrmk 4341
-VPERMILPDZrmkz 4342
-VPERMILPDZrr 4343
-VPERMILPDZrrk 4344
-VPERMILPDZrrkz 4345
-VPERMILPDmi 4346
-VPERMILPDri 4347
-VPERMILPDrm 4348
-VPERMILPDrr 4349
-VPERMILPSYmi 4350
-VPERMILPSYri 4351
-VPERMILPSYrm 4352
-VPERMILPSYrr 4353
-VPERMILPSZ 4354
-VPERMILPSZmbi 4355
-VPERMILPSZmbik 4356
-VPERMILPSZmbikz 4357
-VPERMILPSZmi 4358
-VPERMILPSZmik 4359
-VPERMILPSZmikz 4360
-VPERMILPSZri 4361
-VPERMILPSZrik 4362
-VPERMILPSZrikz 4363
-VPERMILPSZrm 4364
-VPERMILPSZrmb 4365
-VPERMILPSZrmbk 4366
-VPERMILPSZrmbkz 4367
-VPERMILPSZrmk 4368
-VPERMILPSZrmkz 4369
-VPERMILPSZrr 4370
-VPERMILPSZrrk 4371
-VPERMILPSZrrkz 4372
-VPERMILPSmi 4373
-VPERMILPSri 4374
-VPERMILPSrm 4375
-VPERMILPSrr 4376
-VPERMPDYmi 4377
-VPERMPDYri 4378
-VPERMPDZ 4379
-VPERMPDZmbi 4380
-VPERMPDZmbik 4381
-VPERMPDZmbikz 4382
-VPERMPDZmi 4383
-VPERMPDZmik 4384
-VPERMPDZmikz 4385
-VPERMPDZri 4386
-VPERMPDZrik 4387
-VPERMPDZrikz 4388
-VPERMPDZrm 4389
-VPERMPDZrmb 4390
-VPERMPDZrmbk 4391
-VPERMPDZrmbkz 4392
-VPERMPDZrmk 4393
-VPERMPDZrmkz 4394
-VPERMPDZrr 4395
-VPERMPDZrrk 4396
-VPERMPDZrrkz 4397
-VPERMPSYrm 4398
-VPERMPSYrr 4399
-VPERMPSZ 4400
-VPERMPSZrm 4401
-VPERMPSZrmb 4402
-VPERMPSZrmbk 4403
-VPERMPSZrmbkz 4404
-VPERMPSZrmk 4405
-VPERMPSZrmkz 4406
-VPERMPSZrr 4407
-VPERMPSZrrk 4408
-VPERMPSZrrkz 4409
-VPERMQYmi 4410
-VPERMQYri 4411
-VPERMQZ 4412
-VPERMQZmbi 4413
-VPERMQZmbik 4414
-VPERMQZmbikz 4415
-VPERMQZmi 4416
-VPERMQZmik 4417
-VPERMQZmikz 4418
-VPERMQZri 4419
-VPERMQZrik 4420
-VPERMQZrikz 4421
-VPERMQZrm 4422
-VPERMQZrmb 4423
-VPERMQZrmbk 4424
-VPERMQZrmbkz 4425
-VPERMQZrmk 4426
-VPERMQZrmkz 4427
-VPERMQZrr 4428
-VPERMQZrrk 4429
-VPERMQZrrkz 4430
-VPERMT 4431
-VPERMWZ 4432
-VPERMWZrm 4433
-VPERMWZrmk 4434
-VPERMWZrmkz 4435
-VPERMWZrr 4436
-VPERMWZrrk 4437
-VPERMWZrrkz 4438
-VPEXPANDBZ 4439
-VPEXPANDBZrm 4440
-VPEXPANDBZrmk 4441
-VPEXPANDBZrmkz 4442
-VPEXPANDBZrr 4443
-VPEXPANDBZrrk 4444
-VPEXPANDBZrrkz 4445
-VPEXPANDDZ 4446
-VPEXPANDDZrm 4447
-VPEXPANDDZrmk 4448
-VPEXPANDDZrmkz 4449
-VPEXPANDDZrr 4450
-VPEXPANDDZrrk 4451
-VPEXPANDDZrrkz 4452
-VPEXPANDQZ 4453
-VPEXPANDQZrm 4454
-VPEXPANDQZrmk 4455
-VPEXPANDQZrmkz 4456
-VPEXPANDQZrr 4457
-VPEXPANDQZrrk 4458
-VPEXPANDQZrrkz 4459
-VPEXPANDWZ 4460
-VPEXPANDWZrm 4461
-VPEXPANDWZrmk 4462
-VPEXPANDWZrmkz 4463
-VPEXPANDWZrr 4464
-VPEXPANDWZrrk 4465
-VPEXPANDWZrrkz 4466
-VPEXTRBZmri 4467
-VPEXTRBZrri 4468
-VPEXTRBmri 4469
-VPEXTRBrri 4470
-VPEXTRDZmri 4471
-VPEXTRDZrri 4472
-VPEXTRDmri 4473
-VPEXTRDrri 4474
-VPEXTRQZmri 4475
-VPEXTRQZrri 4476
-VPEXTRQmri 4477
-VPEXTRQrri 4478
-VPEXTRWZmri 4479
-VPEXTRWZrri 4480
-VPEXTRWZrri_REV 4481
-VPEXTRWmri 4482
-VPEXTRWrri 4483
-VPEXTRWrri_REV 4484
-VPGATHERDDYrm 4485
-VPGATHERDDZ 4486
-VPGATHERDDZrm 4487
-VPGATHERDDrm 4488
-VPGATHERDQYrm 4489
-VPGATHERDQZ 4490
-VPGATHERDQZrm 4491
-VPGATHERDQrm 4492
-VPGATHERQDYrm 4493
-VPGATHERQDZ 4494
-VPGATHERQDZrm 4495
-VPGATHERQDrm 4496
-VPGATHERQQYrm 4497
-VPGATHERQQZ 4498
-VPGATHERQQZrm 4499
-VPGATHERQQrm 4500
-VPHADDBDrm 4501
-VPHADDBDrr 4502
-VPHADDBQrm 4503
-VPHADDBQrr 4504
-VPHADDBWrm 4505
-VPHADDBWrr 4506
-VPHADDDQrm 4507
-VPHADDDQrr 4508
-VPHADDDYrm 4509
-VPHADDDYrr 4510
-VPHADDDrm 4511
-VPHADDDrr 4512
-VPHADDSWYrm 4513
-VPHADDSWYrr 4514
-VPHADDSWrm 4515
-VPHADDSWrr 4516
-VPHADDUBDrm 4517
-VPHADDUBDrr 4518
-VPHADDUBQrm 4519
-VPHADDUBQrr 4520
-VPHADDUBWrm 4521
-VPHADDUBWrr 4522
-VPHADDUDQrm 4523
-VPHADDUDQrr 4524
-VPHADDUWDrm 4525
-VPHADDUWDrr 4526
-VPHADDUWQrm 4527
-VPHADDUWQrr 4528
-VPHADDWDrm 4529
-VPHADDWDrr 4530
-VPHADDWQrm 4531
-VPHADDWQrr 4532
-VPHADDWYrm 4533
-VPHADDWYrr 4534
-VPHADDWrm 4535
-VPHADDWrr 4536
-VPHMINPOSUWrm 4537
-VPHMINPOSUWrr 4538
-VPHSUBBWrm 4539
-VPHSUBBWrr 4540
-VPHSUBDQrm 4541
-VPHSUBDQrr 4542
-VPHSUBDYrm 4543
-VPHSUBDYrr 4544
-VPHSUBDrm 4545
-VPHSUBDrr 4546
-VPHSUBSWYrm 4547
-VPHSUBSWYrr 4548
-VPHSUBSWrm 4549
-VPHSUBSWrr 4550
-VPHSUBWDrm 4551
-VPHSUBWDrr 4552
-VPHSUBWYrm 4553
-VPHSUBWYrr 4554
-VPHSUBWrm 4555
-VPHSUBWrr 4556
-VPINSRBZrmi 4557
-VPINSRBZrri 4558
-VPINSRBrmi 4559
-VPINSRBrri 4560
-VPINSRDZrmi 4561
-VPINSRDZrri 4562
-VPINSRDrmi 4563
-VPINSRDrri 4564
-VPINSRQZrmi 4565
-VPINSRQZrri 4566
-VPINSRQrmi 4567
-VPINSRQrri 4568
-VPINSRWZrmi 4569
-VPINSRWZrri 4570
-VPINSRWrmi 4571
-VPINSRWrri 4572
-VPLZCNTDZ 4573
-VPLZCNTDZrm 4574
-VPLZCNTDZrmb 4575
-VPLZCNTDZrmbk 4576
-VPLZCNTDZrmbkz 4577
-VPLZCNTDZrmk 4578
-VPLZCNTDZrmkz 4579
-VPLZCNTDZrr 4580
-VPLZCNTDZrrk 4581
-VPLZCNTDZrrkz 4582
-VPLZCNTQZ 4583
-VPLZCNTQZrm 4584
-VPLZCNTQZrmb 4585
-VPLZCNTQZrmbk 4586
-VPLZCNTQZrmbkz 4587
-VPLZCNTQZrmk 4588
-VPLZCNTQZrmkz 4589
-VPLZCNTQZrr 4590
-VPLZCNTQZrrk 4591
-VPLZCNTQZrrkz 4592
-VPMACSDDrm 4593
-VPMACSDDrr 4594
-VPMACSDQHrm 4595
-VPMACSDQHrr 4596
-VPMACSDQLrm 4597
-VPMACSDQLrr 4598
-VPMACSSDDrm 4599
-VPMACSSDDrr 4600
-VPMACSSDQHrm 4601
-VPMACSSDQHrr 4602
-VPMACSSDQLrm 4603
-VPMACSSDQLrr 4604
-VPMACSSWDrm 4605
-VPMACSSWDrr 4606
-VPMACSSWWrm 4607
-VPMACSSWWrr 4608
-VPMACSWDrm 4609
-VPMACSWDrr 4610
-VPMACSWWrm 4611
-VPMACSWWrr 4612
-VPMADCSSWDrm 4613
-VPMADCSSWDrr 4614
-VPMADCSWDrm 4615
-VPMADCSWDrr 4616
-VPMADD 4617
-VPMADDUBSWYrm 4618
-VPMADDUBSWYrr 4619
-VPMADDUBSWZ 4620
-VPMADDUBSWZrm 4621
-VPMADDUBSWZrmk 4622
-VPMADDUBSWZrmkz 4623
-VPMADDUBSWZrr 4624
-VPMADDUBSWZrrk 4625
-VPMADDUBSWZrrkz 4626
-VPMADDUBSWrm 4627
-VPMADDUBSWrr 4628
-VPMADDWDYrm 4629
-VPMADDWDYrr 4630
-VPMADDWDZ 4631
-VPMADDWDZrm 4632
-VPMADDWDZrmk 4633
-VPMADDWDZrmkz 4634
-VPMADDWDZrr 4635
-VPMADDWDZrrk 4636
-VPMADDWDZrrkz 4637
-VPMADDWDrm 4638
-VPMADDWDrr 4639
-VPMASKMOVDYmr 4640
-VPMASKMOVDYrm 4641
-VPMASKMOVDmr 4642
-VPMASKMOVDrm 4643
-VPMASKMOVQYmr 4644
-VPMASKMOVQYrm 4645
-VPMASKMOVQmr 4646
-VPMASKMOVQrm 4647
-VPMAXSBYrm 4648
-VPMAXSBYrr 4649
-VPMAXSBZ 4650
-VPMAXSBZrm 4651
-VPMAXSBZrmk 4652
-VPMAXSBZrmkz 4653
-VPMAXSBZrr 4654
-VPMAXSBZrrk 4655
-VPMAXSBZrrkz 4656
-VPMAXSBrm 4657
-VPMAXSBrr 4658
-VPMAXSDYrm 4659
-VPMAXSDYrr 4660
-VPMAXSDZ 4661
-VPMAXSDZrm 4662
-VPMAXSDZrmb 4663
-VPMAXSDZrmbk 4664
-VPMAXSDZrmbkz 4665
-VPMAXSDZrmk 4666
-VPMAXSDZrmkz 4667
-VPMAXSDZrr 4668
-VPMAXSDZrrk 4669
-VPMAXSDZrrkz 4670
-VPMAXSDrm 4671
-VPMAXSDrr 4672
-VPMAXSQZ 4673
-VPMAXSQZrm 4674
-VPMAXSQZrmb 4675
-VPMAXSQZrmbk 4676
-VPMAXSQZrmbkz 4677
-VPMAXSQZrmk 4678
-VPMAXSQZrmkz 4679
-VPMAXSQZrr 4680
-VPMAXSQZrrk 4681
-VPMAXSQZrrkz 4682
-VPMAXSWYrm 4683
-VPMAXSWYrr 4684
-VPMAXSWZ 4685
-VPMAXSWZrm 4686
-VPMAXSWZrmk 4687
-VPMAXSWZrmkz 4688
-VPMAXSWZrr 4689
-VPMAXSWZrrk 4690
-VPMAXSWZrrkz 4691
-VPMAXSWrm 4692
-VPMAXSWrr 4693
-VPMAXUBYrm 4694
-VPMAXUBYrr 4695
-VPMAXUBZ 4696
-VPMAXUBZrm 4697
-VPMAXUBZrmk 4698
-VPMAXUBZrmkz 4699
-VPMAXUBZrr 4700
-VPMAXUBZrrk 4701
-VPMAXUBZrrkz 4702
-VPMAXUBrm 4703
-VPMAXUBrr 4704
-VPMAXUDYrm 4705
-VPMAXUDYrr 4706
-VPMAXUDZ 4707
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-VPUNPCKLBWZrr 6086
-VPUNPCKLBWZrrk 6087
-VPUNPCKLBWZrrkz 6088
-VPUNPCKLBWrm 6089
-VPUNPCKLBWrr 6090
-VPUNPCKLDQYrm 6091
-VPUNPCKLDQYrr 6092
-VPUNPCKLDQZ 6093
-VPUNPCKLDQZrm 6094
-VPUNPCKLDQZrmb 6095
-VPUNPCKLDQZrmbk 6096
-VPUNPCKLDQZrmbkz 6097
-VPUNPCKLDQZrmk 6098
-VPUNPCKLDQZrmkz 6099
-VPUNPCKLDQZrr 6100
-VPUNPCKLDQZrrk 6101
-VPUNPCKLDQZrrkz 6102
-VPUNPCKLDQrm 6103
-VPUNPCKLDQrr 6104
-VPUNPCKLQDQYrm 6105
-VPUNPCKLQDQYrr 6106
-VPUNPCKLQDQZ 6107
-VPUNPCKLQDQZrm 6108
-VPUNPCKLQDQZrmb 6109
-VPUNPCKLQDQZrmbk 6110
-VPUNPCKLQDQZrmbkz 6111
-VPUNPCKLQDQZrmk 6112
-VPUNPCKLQDQZrmkz 6113
-VPUNPCKLQDQZrr 6114
-VPUNPCKLQDQZrrk 6115
-VPUNPCKLQDQZrrkz 6116
-VPUNPCKLQDQrm 6117
-VPUNPCKLQDQrr 6118
-VPUNPCKLWDYrm 6119
-VPUNPCKLWDYrr 6120
-VPUNPCKLWDZ 6121
-VPUNPCKLWDZrm 6122
-VPUNPCKLWDZrmk 6123
-VPUNPCKLWDZrmkz 6124
-VPUNPCKLWDZrr 6125
-VPUNPCKLWDZrrk 6126
-VPUNPCKLWDZrrkz 6127
-VPUNPCKLWDrm 6128
-VPUNPCKLWDrr 6129
-VPXORDZ 6130
-VPXORDZrm 6131
-VPXORDZrmb 6132
-VPXORDZrmbk 6133
-VPXORDZrmbkz 6134
-VPXORDZrmk 6135
-VPXORDZrmkz 6136
-VPXORDZrr 6137
-VPXORDZrrk 6138
-VPXORDZrrkz 6139
-VPXORQZ 6140
-VPXORQZrm 6141
-VPXORQZrmb 6142
-VPXORQZrmbk 6143
-VPXORQZrmbkz 6144
-VPXORQZrmk 6145
-VPXORQZrmkz 6146
-VPXORQZrr 6147
-VPXORQZrrk 6148
-VPXORQZrrkz 6149
-VPXORYrm 6150
-VPXORYrr 6151
-VPXORrm 6152
-VPXORrr 6153
-VRANGEPDZ 6154
-VRANGEPDZrmbi 6155
-VRANGEPDZrmbik 6156
-VRANGEPDZrmbikz 6157
-VRANGEPDZrmi 6158
-VRANGEPDZrmik 6159
-VRANGEPDZrmikz 6160
-VRANGEPDZrri 6161
-VRANGEPDZrrib 6162
-VRANGEPDZrribk 6163
-VRANGEPDZrribkz 6164
-VRANGEPDZrrik 6165
-VRANGEPDZrrikz 6166
-VRANGEPSZ 6167
-VRANGEPSZrmbi 6168
-VRANGEPSZrmbik 6169
-VRANGEPSZrmbikz 6170
-VRANGEPSZrmi 6171
-VRANGEPSZrmik 6172
-VRANGEPSZrmikz 6173
-VRANGEPSZrri 6174
-VRANGEPSZrrib 6175
-VRANGEPSZrribk 6176
-VRANGEPSZrribkz 6177
-VRANGEPSZrrik 6178
-VRANGEPSZrrikz 6179
-VRANGESDZrmi 6180
-VRANGESDZrmik 6181
-VRANGESDZrmikz 6182
-VRANGESDZrri 6183
-VRANGESDZrrib 6184
-VRANGESDZrribk 6185
-VRANGESDZrribkz 6186
-VRANGESDZrrik 6187
-VRANGESDZrrikz 6188
-VRANGESSZrmi 6189
-VRANGESSZrmik 6190
-VRANGESSZrmikz 6191
-VRANGESSZrri 6192
-VRANGESSZrrib 6193
-VRANGESSZrribk 6194
-VRANGESSZrribkz 6195
-VRANGESSZrrik 6196
-VRANGESSZrrikz 6197
-VRCP 6198
-VRCPBF 6199
-VRCPPHZ 6200
-VRCPPHZm 6201
-VRCPPHZmb 6202
-VRCPPHZmbk 6203
-VRCPPHZmbkz 6204
-VRCPPHZmk 6205
-VRCPPHZmkz 6206
-VRCPPHZr 6207
-VRCPPHZrk 6208
-VRCPPHZrkz 6209
-VRCPPSYm 6210
-VRCPPSYr 6211
-VRCPPSm 6212
-VRCPPSr 6213
-VRCPSHZrm 6214
-VRCPSHZrmk 6215
-VRCPSHZrmkz 6216
-VRCPSHZrr 6217
-VRCPSHZrrk 6218
-VRCPSHZrrkz 6219
-VRCPSSm 6220
-VRCPSSm_Int 6221
-VRCPSSr 6222
-VRCPSSr_Int 6223
-VREDUCEBF 6224
-VREDUCEPDZ 6225
-VREDUCEPDZrmbi 6226
-VREDUCEPDZrmbik 6227
-VREDUCEPDZrmbikz 6228
-VREDUCEPDZrmi 6229
-VREDUCEPDZrmik 6230
-VREDUCEPDZrmikz 6231
-VREDUCEPDZrri 6232
-VREDUCEPDZrrib 6233
-VREDUCEPDZrribk 6234
-VREDUCEPDZrribkz 6235
-VREDUCEPDZrrik 6236
-VREDUCEPDZrrikz 6237
-VREDUCEPHZ 6238
-VREDUCEPHZrmbi 6239
-VREDUCEPHZrmbik 6240
-VREDUCEPHZrmbikz 6241
-VREDUCEPHZrmi 6242
-VREDUCEPHZrmik 6243
-VREDUCEPHZrmikz 6244
-VREDUCEPHZrri 6245
-VREDUCEPHZrrib 6246
-VREDUCEPHZrribk 6247
-VREDUCEPHZrribkz 6248
-VREDUCEPHZrrik 6249
-VREDUCEPHZrrikz 6250
-VREDUCEPSZ 6251
-VREDUCEPSZrmbi 6252
-VREDUCEPSZrmbik 6253
-VREDUCEPSZrmbikz 6254
-VREDUCEPSZrmi 6255
-VREDUCEPSZrmik 6256
-VREDUCEPSZrmikz 6257
-VREDUCEPSZrri 6258
-VREDUCEPSZrrib 6259
-VREDUCEPSZrribk 6260
-VREDUCEPSZrribkz 6261
-VREDUCEPSZrrik 6262
-VREDUCEPSZrrikz 6263
-VREDUCESDZrmi 6264
-VREDUCESDZrmik 6265
-VREDUCESDZrmikz 6266
-VREDUCESDZrri 6267
-VREDUCESDZrrib 6268
-VREDUCESDZrribk 6269
-VREDUCESDZrribkz 6270
-VREDUCESDZrrik 6271
-VREDUCESDZrrikz 6272
-VREDUCESHZrmi 6273
-VREDUCESHZrmik 6274
-VREDUCESHZrmikz 6275
-VREDUCESHZrri 6276
-VREDUCESHZrrib 6277
-VREDUCESHZrribk 6278
-VREDUCESHZrribkz 6279
-VREDUCESHZrrik 6280
-VREDUCESHZrrikz 6281
-VREDUCESSZrmi 6282
-VREDUCESSZrmik 6283
-VREDUCESSZrmikz 6284
-VREDUCESSZrri 6285
-VREDUCESSZrrib 6286
-VREDUCESSZrribk 6287
-VREDUCESSZrribkz 6288
-VREDUCESSZrrik 6289
-VREDUCESSZrrikz 6290
-VRNDSCALEBF 6291
-VRNDSCALEPDZ 6292
-VRNDSCALEPDZrmbi 6293
-VRNDSCALEPDZrmbik 6294
-VRNDSCALEPDZrmbikz 6295
-VRNDSCALEPDZrmi 6296
-VRNDSCALEPDZrmik 6297
-VRNDSCALEPDZrmikz 6298
-VRNDSCALEPDZrri 6299
-VRNDSCALEPDZrrib 6300
-VRNDSCALEPDZrribk 6301
-VRNDSCALEPDZrribkz 6302
-VRNDSCALEPDZrrik 6303
-VRNDSCALEPDZrrikz 6304
-VRNDSCALEPHZ 6305
-VRNDSCALEPHZrmbi 6306
-VRNDSCALEPHZrmbik 6307
-VRNDSCALEPHZrmbikz 6308
-VRNDSCALEPHZrmi 6309
-VRNDSCALEPHZrmik 6310
-VRNDSCALEPHZrmikz 6311
-VRNDSCALEPHZrri 6312
-VRNDSCALEPHZrrib 6313
-VRNDSCALEPHZrribk 6314
-VRNDSCALEPHZrribkz 6315
-VRNDSCALEPHZrrik 6316
-VRNDSCALEPHZrrikz 6317
-VRNDSCALEPSZ 6318
-VRNDSCALEPSZrmbi 6319
-VRNDSCALEPSZrmbik 6320
-VRNDSCALEPSZrmbikz 6321
-VRNDSCALEPSZrmi 6322
-VRNDSCALEPSZrmik 6323
-VRNDSCALEPSZrmikz 6324
-VRNDSCALEPSZrri 6325
-VRNDSCALEPSZrrib 6326
-VRNDSCALEPSZrribk 6327
-VRNDSCALEPSZrribkz 6328
-VRNDSCALEPSZrrik 6329
-VRNDSCALEPSZrrikz 6330
-VRNDSCALESDZrmi 6331
-VRNDSCALESDZrmi_Int 6332
-VRNDSCALESDZrmik_Int 6333
-VRNDSCALESDZrmikz_Int 6334
-VRNDSCALESDZrri 6335
-VRNDSCALESDZrri_Int 6336
-VRNDSCALESDZrrib_Int 6337
-VRNDSCALESDZrribk_Int 6338
-VRNDSCALESDZrribkz_Int 6339
-VRNDSCALESDZrrik_Int 6340
-VRNDSCALESDZrrikz_Int 6341
-VRNDSCALESHZrmi 6342
-VRNDSCALESHZrmi_Int 6343
-VRNDSCALESHZrmik_Int 6344
-VRNDSCALESHZrmikz_Int 6345
-VRNDSCALESHZrri 6346
-VRNDSCALESHZrri_Int 6347
-VRNDSCALESHZrrib_Int 6348
-VRNDSCALESHZrribk_Int 6349
-VRNDSCALESHZrribkz_Int 6350
-VRNDSCALESHZrrik_Int 6351
-VRNDSCALESHZrrikz_Int 6352
-VRNDSCALESSZrmi 6353
-VRNDSCALESSZrmi_Int 6354
-VRNDSCALESSZrmik_Int 6355
-VRNDSCALESSZrmikz_Int 6356
-VRNDSCALESSZrri 6357
-VRNDSCALESSZrri_Int 6358
-VRNDSCALESSZrrib_Int 6359
-VRNDSCALESSZrribk_Int 6360
-VRNDSCALESSZrribkz_Int 6361
-VRNDSCALESSZrrik_Int 6362
-VRNDSCALESSZrrikz_Int 6363
-VROUNDPDYmi 6364
-VROUNDPDYri 6365
-VROUNDPDmi 6366
-VROUNDPDri 6367
-VROUNDPSYmi 6368
-VROUNDPSYri 6369
-VROUNDPSmi 6370
-VROUNDPSri 6371
-VROUNDSDmi 6372
-VROUNDSDmi_Int 6373
-VROUNDSDri 6374
-VROUNDSDri_Int 6375
-VROUNDSSmi 6376
-VROUNDSSmi_Int 6377
-VROUNDSSri 6378
-VROUNDSSri_Int 6379
-VRSQRT 6380
-VRSQRTBF 6381
-VRSQRTPHZ 6382
-VRSQRTPHZm 6383
-VRSQRTPHZmb 6384
-VRSQRTPHZmbk 6385
-VRSQRTPHZmbkz 6386
-VRSQRTPHZmk 6387
-VRSQRTPHZmkz 6388
-VRSQRTPHZr 6389
-VRSQRTPHZrk 6390
-VRSQRTPHZrkz 6391
-VRSQRTPSYm 6392
-VRSQRTPSYr 6393
-VRSQRTPSm 6394
-VRSQRTPSr 6395
-VRSQRTSHZrm 6396
-VRSQRTSHZrmk 6397
-VRSQRTSHZrmkz 6398
-VRSQRTSHZrr 6399
-VRSQRTSHZrrk 6400
-VRSQRTSHZrrkz 6401
-VRSQRTSSm 6402
-VRSQRTSSm_Int 6403
-VRSQRTSSr 6404
-VRSQRTSSr_Int 6405
-VSCALEFBF 6406
-VSCALEFPDZ 6407
-VSCALEFPDZrm 6408
-VSCALEFPDZrmb 6409
-VSCALEFPDZrmbk 6410
-VSCALEFPDZrmbkz 6411
-VSCALEFPDZrmk 6412
-VSCALEFPDZrmkz 6413
-VSCALEFPDZrr 6414
-VSCALEFPDZrrb 6415
-VSCALEFPDZrrbk 6416
-VSCALEFPDZrrbkz 6417
-VSCALEFPDZrrk 6418
-VSCALEFPDZrrkz 6419
-VSCALEFPHZ 6420
-VSCALEFPHZrm 6421
-VSCALEFPHZrmb 6422
-VSCALEFPHZrmbk 6423
-VSCALEFPHZrmbkz 6424
-VSCALEFPHZrmk 6425
-VSCALEFPHZrmkz 6426
-VSCALEFPHZrr 6427
-VSCALEFPHZrrb 6428
-VSCALEFPHZrrbk 6429
-VSCALEFPHZrrbkz 6430
-VSCALEFPHZrrk 6431
-VSCALEFPHZrrkz 6432
-VSCALEFPSZ 6433
-VSCALEFPSZrm 6434
-VSCALEFPSZrmb 6435
-VSCALEFPSZrmbk 6436
-VSCALEFPSZrmbkz 6437
-VSCALEFPSZrmk 6438
-VSCALEFPSZrmkz 6439
-VSCALEFPSZrr 6440
-VSCALEFPSZrrb 6441
-VSCALEFPSZrrbk 6442
-VSCALEFPSZrrbkz 6443
-VSCALEFPSZrrk 6444
-VSCALEFPSZrrkz 6445
-VSCALEFSDZrm 6446
-VSCALEFSDZrmk 6447
-VSCALEFSDZrmkz 6448
-VSCALEFSDZrr 6449
-VSCALEFSDZrrb_Int 6450
-VSCALEFSDZrrbk_Int 6451
-VSCALEFSDZrrbkz_Int 6452
-VSCALEFSDZrrk 6453
-VSCALEFSDZrrkz 6454
-VSCALEFSHZrm 6455
-VSCALEFSHZrmk 6456
-VSCALEFSHZrmkz 6457
-VSCALEFSHZrr 6458
-VSCALEFSHZrrb_Int 6459
-VSCALEFSHZrrbk_Int 6460
-VSCALEFSHZrrbkz_Int 6461
-VSCALEFSHZrrk 6462
-VSCALEFSHZrrkz 6463
-VSCALEFSSZrm 6464
-VSCALEFSSZrmk 6465
-VSCALEFSSZrmkz 6466
-VSCALEFSSZrr 6467
-VSCALEFSSZrrb_Int 6468
-VSCALEFSSZrrbk_Int 6469
-VSCALEFSSZrrbkz_Int 6470
-VSCALEFSSZrrk 6471
-VSCALEFSSZrrkz 6472
-VSCATTERDPDZ 6473
-VSCATTERDPDZmr 6474
-VSCATTERDPSZ 6475
-VSCATTERDPSZmr 6476
-VSCATTERPF 6477
-VSCATTERQPDZ 6478
-VSCATTERQPDZmr 6479
-VSCATTERQPSZ 6480
-VSCATTERQPSZmr 6481
-VSHA 6482
-VSHUFF 6483
-VSHUFI 6484
-VSHUFPDYrmi 6485
-VSHUFPDYrri 6486
-VSHUFPDZ 6487
-VSHUFPDZrmbi 6488
-VSHUFPDZrmbik 6489
-VSHUFPDZrmbikz 6490
-VSHUFPDZrmi 6491
-VSHUFPDZrmik 6492
-VSHUFPDZrmikz 6493
-VSHUFPDZrri 6494
-VSHUFPDZrrik 6495
-VSHUFPDZrrikz 6496
-VSHUFPDrmi 6497
-VSHUFPDrri 6498
-VSHUFPSYrmi 6499
-VSHUFPSYrri 6500
-VSHUFPSZ 6501
-VSHUFPSZrmbi 6502
-VSHUFPSZrmbik 6503
-VSHUFPSZrmbikz 6504
-VSHUFPSZrmi 6505
-VSHUFPSZrmik 6506
-VSHUFPSZrmikz 6507
-VSHUFPSZrri 6508
-VSHUFPSZrrik 6509
-VSHUFPSZrrikz 6510
-VSHUFPSrmi 6511
-VSHUFPSrri 6512
-VSM 6513
-VSQRTBF 6514
-VSQRTPDYm 6515
-VSQRTPDYr 6516
-VSQRTPDZ 6517
-VSQRTPDZm 6518
-VSQRTPDZmb 6519
-VSQRTPDZmbk 6520
-VSQRTPDZmbkz 6521
-VSQRTPDZmk 6522
-VSQRTPDZmkz 6523
-VSQRTPDZr 6524
-VSQRTPDZrb 6525
-VSQRTPDZrbk 6526
-VSQRTPDZrbkz 6527
-VSQRTPDZrk 6528
-VSQRTPDZrkz 6529
-VSQRTPDm 6530
-VSQRTPDr 6531
-VSQRTPHZ 6532
-VSQRTPHZm 6533
-VSQRTPHZmb 6534
-VSQRTPHZmbk 6535
-VSQRTPHZmbkz 6536
-VSQRTPHZmk 6537
-VSQRTPHZmkz 6538
-VSQRTPHZr 6539
-VSQRTPHZrb 6540
-VSQRTPHZrbk 6541
-VSQRTPHZrbkz 6542
-VSQRTPHZrk 6543
-VSQRTPHZrkz 6544
-VSQRTPSYm 6545
-VSQRTPSYr 6546
-VSQRTPSZ 6547
-VSQRTPSZm 6548
-VSQRTPSZmb 6549
-VSQRTPSZmbk 6550
-VSQRTPSZmbkz 6551
-VSQRTPSZmk 6552
-VSQRTPSZmkz 6553
-VSQRTPSZr 6554
-VSQRTPSZrb 6555
-VSQRTPSZrbk 6556
-VSQRTPSZrbkz 6557
-VSQRTPSZrk 6558
-VSQRTPSZrkz 6559
-VSQRTPSm 6560
-VSQRTPSr 6561
-VSQRTSDZm 6562
-VSQRTSDZm_Int 6563
-VSQRTSDZmk_Int 6564
-VSQRTSDZmkz_Int 6565
-VSQRTSDZr 6566
-VSQRTSDZr_Int 6567
-VSQRTSDZrb_Int 6568
-VSQRTSDZrbk_Int 6569
-VSQRTSDZrbkz_Int 6570
-VSQRTSDZrk_Int 6571
-VSQRTSDZrkz_Int 6572
-VSQRTSDm 6573
-VSQRTSDm_Int 6574
-VSQRTSDr 6575
-VSQRTSDr_Int 6576
-VSQRTSHZm 6577
-VSQRTSHZm_Int 6578
-VSQRTSHZmk_Int 6579
-VSQRTSHZmkz_Int 6580
-VSQRTSHZr 6581
-VSQRTSHZr_Int 6582
-VSQRTSHZrb_Int 6583
-VSQRTSHZrbk_Int 6584
-VSQRTSHZrbkz_Int 6585
-VSQRTSHZrk_Int 6586
-VSQRTSHZrkz_Int 6587
-VSQRTSSZm 6588
-VSQRTSSZm_Int 6589
-VSQRTSSZmk_Int 6590
-VSQRTSSZmkz_Int 6591
-VSQRTSSZr 6592
-VSQRTSSZr_Int 6593
-VSQRTSSZrb_Int 6594
-VSQRTSSZrbk_Int 6595
-VSQRTSSZrbkz_Int 6596
-VSQRTSSZrk_Int 6597
-VSQRTSSZrkz_Int 6598
-VSQRTSSm 6599
-VSQRTSSm_Int 6600
-VSQRTSSr 6601
-VSQRTSSr_Int 6602
-VSTMXCSR 6603
-VSUBBF 6604
-VSUBPDYrm 6605
-VSUBPDYrr 6606
-VSUBPDZ 6607
-VSUBPDZrm 6608
-VSUBPDZrmb 6609
-VSUBPDZrmbk 6610
-VSUBPDZrmbkz 6611
-VSUBPDZrmk 6612
-VSUBPDZrmkz 6613
-VSUBPDZrr 6614
-VSUBPDZrrb 6615
-VSUBPDZrrbk 6616
-VSUBPDZrrbkz 6617
-VSUBPDZrrk 6618
-VSUBPDZrrkz 6619
-VSUBPDrm 6620
-VSUBPDrr 6621
-VSUBPHZ 6622
-VSUBPHZrm 6623
-VSUBPHZrmb 6624
-VSUBPHZrmbk 6625
-VSUBPHZrmbkz 6626
-VSUBPHZrmk 6627
-VSUBPHZrmkz 6628
-VSUBPHZrr 6629
-VSUBPHZrrb 6630
-VSUBPHZrrbk 6631
-VSUBPHZrrbkz 6632
-VSUBPHZrrk 6633
-VSUBPHZrrkz 6634
-VSUBPSYrm 6635
-VSUBPSYrr 6636
-VSUBPSZ 6637
-VSUBPSZrm 6638
-VSUBPSZrmb 6639
-VSUBPSZrmbk 6640
-VSUBPSZrmbkz 6641
-VSUBPSZrmk 6642
-VSUBPSZrmkz 6643
-VSUBPSZrr 6644
-VSUBPSZrrb 6645
-VSUBPSZrrbk 6646
-VSUBPSZrrbkz 6647
-VSUBPSZrrk 6648
-VSUBPSZrrkz 6649
-VSUBPSrm 6650
-VSUBPSrr 6651
-VSUBSDZrm 6652
-VSUBSDZrm_Int 6653
-VSUBSDZrmk_Int 6654
-VSUBSDZrmkz_Int 6655
-VSUBSDZrr 6656
-VSUBSDZrr_Int 6657
-VSUBSDZrrb_Int 6658
-VSUBSDZrrbk_Int 6659
-VSUBSDZrrbkz_Int 6660
-VSUBSDZrrk_Int 6661
-VSUBSDZrrkz_Int 6662
-VSUBSDrm 6663
-VSUBSDrm_Int 6664
-VSUBSDrr 6665
-VSUBSDrr_Int 6666
-VSUBSHZrm 6667
-VSUBSHZrm_Int 6668
-VSUBSHZrmk_Int 6669
-VSUBSHZrmkz_Int 6670
-VSUBSHZrr 6671
-VSUBSHZrr_Int 6672
-VSUBSHZrrb_Int 6673
-VSUBSHZrrbk_Int 6674
-VSUBSHZrrbkz_Int 6675
-VSUBSHZrrk_Int 6676
-VSUBSHZrrkz_Int 6677
-VSUBSSZrm 6678
-VSUBSSZrm_Int 6679
-VSUBSSZrmk_Int 6680
-VSUBSSZrmkz_Int 6681
-VSUBSSZrr 6682
-VSUBSSZrr_Int 6683
-VSUBSSZrrb_Int 6684
-VSUBSSZrrbk_Int 6685
-VSUBSSZrrbkz_Int 6686
-VSUBSSZrrk_Int 6687
-VSUBSSZrrkz_Int 6688
-VSUBSSrm 6689
-VSUBSSrm_Int 6690
-VSUBSSrr 6691
-VSUBSSrr_Int 6692
-VTESTPDYrm 6693
-VTESTPDYrr 6694
-VTESTPDrm 6695
-VTESTPDrr 6696
-VTESTPSYrm 6697
-VTESTPSYrr 6698
-VTESTPSrm 6699
-VTESTPSrr 6700
-VUCOMISDZrm 6701
-VUCOMISDZrm_Int 6702
-VUCOMISDZrr 6703
-VUCOMISDZrr_Int 6704
-VUCOMISDZrrb 6705
-VUCOMISDrm 6706
-VUCOMISDrm_Int 6707
-VUCOMISDrr 6708
-VUCOMISDrr_Int 6709
-VUCOMISHZrm 6710
-VUCOMISHZrm_Int 6711
-VUCOMISHZrr 6712
-VUCOMISHZrr_Int 6713
-VUCOMISHZrrb 6714
-VUCOMISSZrm 6715
-VUCOMISSZrm_Int 6716
-VUCOMISSZrr 6717
-VUCOMISSZrr_Int 6718
-VUCOMISSZrrb 6719
-VUCOMISSrm 6720
-VUCOMISSrm_Int 6721
-VUCOMISSrr 6722
-VUCOMISSrr_Int 6723
-VUCOMXSDZrm 6724
-VUCOMXSDZrm_Int 6725
-VUCOMXSDZrr 6726
-VUCOMXSDZrr_Int 6727
-VUCOMXSDZrrb_Int 6728
-VUCOMXSHZrm 6729
-VUCOMXSHZrm_Int 6730
-VUCOMXSHZrr 6731
-VUCOMXSHZrr_Int 6732
-VUCOMXSHZrrb_Int 6733
-VUCOMXSSZrm 6734
-VUCOMXSSZrm_Int 6735
-VUCOMXSSZrr 6736
-VUCOMXSSZrr_Int 6737
-VUCOMXSSZrrb_Int 6738
-VUNPCKHPDYrm 6739
-VUNPCKHPDYrr 6740
-VUNPCKHPDZ 6741
-VUNPCKHPDZrm 6742
-VUNPCKHPDZrmb 6743
-VUNPCKHPDZrmbk 6744
-VUNPCKHPDZrmbkz 6745
-VUNPCKHPDZrmk 6746
-VUNPCKHPDZrmkz 6747
-VUNPCKHPDZrr 6748
-VUNPCKHPDZrrk 6749
-VUNPCKHPDZrrkz 6750
-VUNPCKHPDrm 6751
-VUNPCKHPDrr 6752
-VUNPCKHPSYrm 6753
-VUNPCKHPSYrr 6754
-VUNPCKHPSZ 6755
-VUNPCKHPSZrm 6756
-VUNPCKHPSZrmb 6757
-VUNPCKHPSZrmbk 6758
-VUNPCKHPSZrmbkz 6759
-VUNPCKHPSZrmk 6760
-VUNPCKHPSZrmkz 6761
-VUNPCKHPSZrr 6762
-VUNPCKHPSZrrk 6763
-VUNPCKHPSZrrkz 6764
-VUNPCKHPSrm 6765
-VUNPCKHPSrr 6766
-VUNPCKLPDYrm 6767
-VUNPCKLPDYrr 6768
-VUNPCKLPDZ 6769
-VUNPCKLPDZrm 6770
-VUNPCKLPDZrmb 6771
-VUNPCKLPDZrmbk 6772
-VUNPCKLPDZrmbkz 6773
-VUNPCKLPDZrmk 6774
-VUNPCKLPDZrmkz 6775
-VUNPCKLPDZrr 6776
-VUNPCKLPDZrrk 6777
-VUNPCKLPDZrrkz 6778
-VUNPCKLPDrm 6779
-VUNPCKLPDrr 6780
-VUNPCKLPSYrm 6781
-VUNPCKLPSYrr 6782
-VUNPCKLPSZ 6783
-VUNPCKLPSZrm 6784
-VUNPCKLPSZrmb 6785
-VUNPCKLPSZrmbk 6786
-VUNPCKLPSZrmbkz 6787
-VUNPCKLPSZrmk 6788
-VUNPCKLPSZrmkz 6789
-VUNPCKLPSZrr 6790
-VUNPCKLPSZrrk 6791
-VUNPCKLPSZrrkz 6792
-VUNPCKLPSrm 6793
-VUNPCKLPSrr 6794
-VXORPDYrm 6795
-VXORPDYrr 6796
-VXORPDZ 6797
-VXORPDZrm 6798
-VXORPDZrmb 6799
-VXORPDZrmbk 6800
-VXORPDZrmbkz 6801
-VXORPDZrmk 6802
-VXORPDZrmkz 6803
-VXORPDZrr 6804
-VXORPDZrrk 6805
-VXORPDZrrkz 6806
-VXORPDrm 6807
-VXORPDrr 6808
-VXORPSYrm 6809
-VXORPSYrr 6810
-VXORPSZ 6811
-VXORPSZrm 6812
-VXORPSZrmb 6813
-VXORPSZrmbk 6814
-VXORPSZrmbkz 6815
-VXORPSZrmk 6816
-VXORPSZrmkz 6817
-VXORPSZrr 6818
-VXORPSZrrk 6819
-VXORPSZrrkz 6820
-VXORPSrm 6821
-VXORPSrr 6822
-VZEROALL 6823
-VZEROUPPER 6824
-V_SET 6825
-V_SETALLONES 6826
-WAIT 6827
-WBINVD 6828
-WBNOINVD 6829
-WRFLAGS 6830
-WRFSBASE 6831
-WRGSBASE 6832
-WRMSR 6833
-WRMSRLIST 6834
-WRMSRNS 6835
-WRMSRNSir 6836
-WRMSRNSir_EVEX 6837
-WRPKRUr 6838
-WRSSD 6839
-WRSSD_EVEX 6840
-WRSSQ 6841
-WRSSQ_EVEX 6842
-WRUSSD 6843
-WRUSSD_EVEX 6844
-WRUSSQ 6845
-WRUSSQ_EVEX 6846
-XABORT 6847
-XABORT_DEF 6848
-XACQUIRE_PREFIX 6849
-XADD 6850
-XAM_F 6851
-XAM_Fp 6852
-XBEGIN 6853
-XCHG 6854
-XCH_F 6855
-XCRYPTCBC 6856
-XCRYPTCFB 6857
-XCRYPTCTR 6858
-XCRYPTECB 6859
-XCRYPTOFB 6860
-XEND 6861
-XGETBV 6862
-XLAT 6863
-XOR 6864
-XORPDrm 6865
-XORPDrr 6866
-XORPSrm 6867
-XORPSrr 6868
-XRELEASE_PREFIX 6869
-XRESLDTRK 6870
-XRSTOR 6871
-XRSTORS 6872
-XSAVE 6873
-XSAVEC 6874
-XSAVEOPT 6875
-XSAVES 6876
-XSETBV 6877
-XSHA 6878
-XSTORE 6879
-XSUSLDTRK 6880
-XTEST 6881
-Immediate 6882
-CImmediate 6883
-FPImmediate 6884
-MBB 6885
-FrameIndex 6886
-ConstantPoolIndex 6887
-TargetIndex 6888
-JumpTableIndex 6889
-ExternalSymbol 6890
-GlobalAddress 6891
-BlockAddress 6892
-RegisterMask 6893
-RegisterLiveOut 6894
-Metadata 6895
-MCSymbol 6896
-CFIIndex 6897
-IntrinsicID 6898
-Predicate 6899
-ShuffleMask 6900
-PhyReg_GR8 6901
-PhyReg_GRH8 6902
-PhyReg_GR8_NOREX2 6903
-PhyReg_GR8_NOREX 6904
-PhyReg_GR8_ABCD_H 6905
-PhyReg_GR8_ABCD_L 6906
-PhyReg_GRH16 6907
-PhyReg_GR16 6908
-PhyReg_GR16_NOREX2 6909
-PhyReg_GR16_NOREX 6910
-PhyReg_VK1 6911
-PhyReg_VK16 6912
-PhyReg_VK2 6913
-PhyReg_VK4 6914
-PhyReg_VK8 6915
-PhyReg_VK16WM 6916
-PhyReg_VK1WM 6917
-PhyReg_VK2WM 6918
-PhyReg_VK4WM 6919
-PhyReg_VK8WM 6920
-PhyReg_SEGMENT_REG 6921
-PhyReg_GR16_ABCD 6922
-PhyReg_FPCCR 6923
-PhyReg_FR16X 6924
-PhyReg_FR16 6925
-PhyReg_VK16PAIR 6926
-PhyReg_VK1PAIR 6927
-PhyReg_VK2PAIR 6928
-PhyReg_VK4PAIR 6929
-PhyReg_VK8PAIR 6930
-PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6931
-PhyReg_LOW32_ADDR_ACCESS_RBP 6932
-PhyReg_LOW32_ADDR_ACCESS 6933
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6934
-PhyReg_FR32X 6935
-PhyReg_GR32 6936
-PhyReg_GR32_NOSP 6937
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6938
-PhyReg_DEBUG_REG 6939
-PhyReg_FR32 6940
-PhyReg_GR32_NOREX2 6941
-PhyReg_GR32_NOREX2_NOSP 6942
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6943
-PhyReg_GR32_NOREX 6944
-PhyReg_VK32 6945
-PhyReg_GR32_NOREX_NOSP 6946
-PhyReg_RFP32 6947
-PhyReg_VK32WM 6948
-PhyReg_GR32_ABCD 6949
-PhyReg_GR32_TC 6950
-PhyReg_GR32_ABCD_and_GR32_TC 6951
-PhyReg_GR32_AD 6952
-PhyReg_GR32_ArgRef 6953
-PhyReg_GR32_BPSP 6954
-PhyReg_GR32_BSI 6955
-PhyReg_GR32_CB 6956
-PhyReg_GR32_DC 6957
-PhyReg_GR32_DIBP 6958
-PhyReg_GR32_SIDI 6959
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6960
-PhyReg_CCR 6961
-PhyReg_DFCCR 6962
-PhyReg_GR32_ABCD_and_GR32_BSI 6963
-PhyReg_GR32_AD_and_GR32_ArgRef 6964
-PhyReg_GR32_ArgRef_and_GR32_CB 6965
-PhyReg_GR32_BPSP_and_GR32_DIBP 6966
-PhyReg_GR32_BPSP_and_GR32_TC 6967
-PhyReg_GR32_BSI_and_GR32_SIDI 6968
-PhyReg_GR32_DIBP_and_GR32_SIDI 6969
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6970
-PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6971
-PhyReg_RFP64 6972
-PhyReg_GR64 6973
-PhyReg_FR64X 6974
-PhyReg_GR64_with_sub_8bit 6975
-PhyReg_GR64_NOSP 6976
-PhyReg_GR64_NOREX2 6977
-PhyReg_CONTROL_REG 6978
-PhyReg_FR64 6979
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6980
-PhyReg_GR64_NOREX2_NOSP 6981
-PhyReg_GR64PLTSafe 6982
-PhyReg_GR64_TC 6983
-PhyReg_GR64_NOREX 6984
-PhyReg_GR64_TCW64 6985
-PhyReg_GR64_TC_with_sub_8bit 6986
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6987
-PhyReg_GR64_TCW64_with_sub_8bit 6988
-PhyReg_GR64_TC_and_GR64_TCW64 6989
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6990
-PhyReg_VK64 6991
-PhyReg_VR64 6992
-PhyReg_GR64PLTSafe_and_GR64_TC 6993
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6994
-PhyReg_GR64_NOREX_NOSP 6995
-PhyReg_GR64_NOREX_and_GR64_TC 6996
-PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6997
-PhyReg_VK64WM 6998
-PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6999
-PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7000
-PhyReg_GR64PLTSafe_and_GR64_TCW64 7001
-PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7002
-PhyReg_GR64_NOREX_and_GR64_TCW64 7003
-PhyReg_GR64_ABCD 7004
-PhyReg_GR64_with_sub_32bit_in_GR32_TC 7005
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7006
-PhyReg_GR64_AD 7007
-PhyReg_GR64_ArgRef 7008
-PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7009
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 7010
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 7011
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI 7012
-PhyReg_GR64_with_sub_32bit_in_GR32_CB 7013
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 7014
-PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 7015
-PhyReg_GR64_A 7016
-PhyReg_GR64_ArgRef_and_GR64_TC 7017
-PhyReg_GR64_and_LOW32_ADDR_ACCESS 7018
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7019
-PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7020
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7021
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7022
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7023
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7024
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7025
-PhyReg_RST 7026
-PhyReg_RFP80 7027
-PhyReg_RFP80_7 7028
-PhyReg_VR128X 7029
-PhyReg_VR128 7030
-PhyReg_VR256X 7031
-PhyReg_VR256 7032
-PhyReg_VR512 7033
-PhyReg_VR512_0_15 7034
-PhyReg_TILE 7035
-PhyReg_TILEPAIR 7036
-VirtReg_GR8 7037
-VirtReg_GRH8 7038
-VirtReg_GR8_NOREX2 7039
-VirtReg_GR8_NOREX 7040
-VirtReg_GR8_ABCD_H 7041
-VirtReg_GR8_ABCD_L 7042
-VirtReg_GRH16 7043
-VirtReg_GR16 7044
-VirtReg_GR16_NOREX2 7045
-VirtReg_GR16_NOREX 7046
-VirtReg_VK1 7047
-VirtReg_VK16 7048
-VirtReg_VK2 7049
-VirtReg_VK4 7050
-VirtReg_VK8 7051
-VirtReg_VK16WM 7052
-VirtReg_VK1WM 7053
-VirtReg_VK2WM 7054
-VirtReg_VK4WM 7055
-VirtReg_VK8WM 7056
-VirtReg_SEGMENT_REG 7057
-VirtReg_GR16_ABCD 7058
-VirtReg_FPCCR 7059
-VirtReg_FR16X 7060
-VirtReg_FR16 7061
-VirtReg_VK16PAIR 7062
-VirtReg_VK1PAIR 7063
-VirtReg_VK2PAIR 7064
-VirtReg_VK4PAIR 7065
-VirtReg_VK8PAIR 7066
-VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7067
-VirtReg_LOW32_ADDR_ACCESS_RBP 7068
-VirtReg_LOW32_ADDR_ACCESS 7069
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7070
-VirtReg_FR32X 7071
-VirtReg_GR32 7072
-VirtReg_GR32_NOSP 7073
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7074
-VirtReg_DEBUG_REG 7075
-VirtReg_FR32 7076
-VirtReg_GR32_NOREX2 7077
-VirtReg_GR32_NOREX2_NOSP 7078
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7079
-VirtReg_GR32_NOREX 7080
-VirtReg_VK32 7081
-VirtReg_GR32_NOREX_NOSP 7082
-VirtReg_RFP32 7083
-VirtReg_VK32WM 7084
-VirtReg_GR32_ABCD 7085
-VirtReg_GR32_TC 7086
-VirtReg_GR32_ABCD_and_GR32_TC 7087
-VirtReg_GR32_AD 7088
-VirtReg_GR32_ArgRef 7089
-VirtReg_GR32_BPSP 7090
-VirtReg_GR32_BSI 7091
-VirtReg_GR32_CB 7092
-VirtReg_GR32_DC 7093
-VirtReg_GR32_DIBP 7094
-VirtReg_GR32_SIDI 7095
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7096
-VirtReg_CCR 7097
-VirtReg_DFCCR 7098
-VirtReg_GR32_ABCD_and_GR32_BSI 7099
-VirtReg_GR32_AD_and_GR32_ArgRef 7100
-VirtReg_GR32_ArgRef_and_GR32_CB 7101
-VirtReg_GR32_BPSP_and_GR32_DIBP 7102
-VirtReg_GR32_BPSP_and_GR32_TC 7103
-VirtReg_GR32_BSI_and_GR32_SIDI 7104
-VirtReg_GR32_DIBP_and_GR32_SIDI 7105
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7106
-VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7107
-VirtReg_RFP64 7108
-VirtReg_GR64 7109
-VirtReg_FR64X 7110
-VirtReg_GR64_with_sub_8bit 7111
-VirtReg_GR64_NOSP 7112
-VirtReg_GR64_NOREX2 7113
-VirtReg_CONTROL_REG 7114
-VirtReg_FR64 7115
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7116
-VirtReg_GR64_NOREX2_NOSP 7117
-VirtReg_GR64PLTSafe 7118
-VirtReg_GR64_TC 7119
-VirtReg_GR64_NOREX 7120
-VirtReg_GR64_TCW64 7121
-VirtReg_GR64_TC_with_sub_8bit 7122
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7123
-VirtReg_GR64_TCW64_with_sub_8bit 7124
-VirtReg_GR64_TC_and_GR64_TCW64 7125
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7126
-VirtReg_VK64 7127
-VirtReg_VR64 7128
-VirtReg_GR64PLTSafe_and_GR64_TC 7129
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7130
-VirtReg_GR64_NOREX_NOSP 7131
-VirtReg_GR64_NOREX_and_GR64_TC 7132
-VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7133
-VirtReg_VK64WM 7134
-VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7135
-VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7136
-VirtReg_GR64PLTSafe_and_GR64_TCW64 7137
-VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7138
-VirtReg_GR64_NOREX_and_GR64_TCW64 7139
-VirtReg_GR64_ABCD 7140
-VirtReg_GR64_with_sub_32bit_in_GR32_TC 7141
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7142
-VirtReg_GR64_AD 7143
-VirtReg_GR64_ArgRef 7144
-VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7145
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7146
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7147
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7148
-VirtReg_GR64_with_sub_32bit_in_GR32_CB 7149
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7150
-VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7151
-VirtReg_GR64_A 7152
-VirtReg_GR64_ArgRef_and_GR64_TC 7153
-VirtReg_GR64_and_LOW32_ADDR_ACCESS 7154
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7155
-VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7156
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7157
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7158
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7159
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7160
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7161
-VirtReg_RST 7162
-VirtReg_RFP80 7163
-VirtReg_RFP80_7 7164
-VirtReg_VR128X 7165
-VirtReg_VR128 7166
-VirtReg_VR256X 7167
-VirtReg_VR256 7168
-VirtReg_VR512 7169
-VirtReg_VR512_0_15 7170
-VirtReg_TILE 7171
-VirtReg_TILEPAIR 7172
+PTCMMIMFP 1441
+PTCMMRLFP 1442
+PTCVTROWD 1443
+PTCVTROWPS 1444
+PTDPBF 1445
+PTDPBHF 1446
+PTDPBSSD 1447
+PTDPBSSDV 1448
+PTDPBSUD 1449
+PTDPBSUDV 1450
+PTDPBUSD 1451
+PTDPBUSDV 1452
+PTDPBUUD 1453
+PTDPBUUDV 1454
+PTDPFP 1455
+PTDPHBF 1456
+PTDPHF 1457
+PTESTrm 1458
+PTESTrr 1459
+PTILELOADD 1460
+PTILELOADDRS 1461
+PTILELOADDRST 1462
+PTILELOADDRSV 1463
+PTILELOADDT 1464
+PTILELOADDV 1465
+PTILEMOVROWrre 1466
+PTILEMOVROWrreV 1467
+PTILEMOVROWrri 1468
+PTILEMOVROWrriV 1469
+PTILESTORED 1470
+PTILESTOREDV 1471
+PTILEZERO 1472
+PTILEZEROV 1473
+PTMMULTF 1474
+PTWRITE 1475
+PTWRITEm 1476
+PTWRITEr 1477
+PUNPCKHBWrm 1478
+PUNPCKHBWrr 1479
+PUNPCKHDQrm 1480
+PUNPCKHDQrr 1481
+PUNPCKHQDQrm 1482
+PUNPCKHQDQrr 1483
+PUNPCKHWDrm 1484
+PUNPCKHWDrr 1485
+PUNPCKLBWrm 1486
+PUNPCKLBWrr 1487
+PUNPCKLDQrm 1488
+PUNPCKLDQrr 1489
+PUNPCKLQDQrm 1490
+PUNPCKLQDQrr 1491
+PUNPCKLWDrm 1492
+PUNPCKLWDrr 1493
+PUSH 1494
+PUSHA 1495
+PUSHCS 1496
+PUSHDS 1497
+PUSHES 1498
+PUSHF 1499
+PUSHFS 1500
+PUSHGS 1501
+PUSHP 1502
+PUSHSS 1503
+PVALIDATE 1504
+PXORrm 1505
+PXORrr 1506
+RCL 1507
+RCPPSm 1508
+RCPPSr 1509
+RCPSSm 1510
+RCPSSm_Int 1511
+RCPSSr 1512
+RCPSSr_Int 1513
+RCR 1514
+RDFLAGS 1515
+RDFSBASE 1516
+RDGSBASE 1517
+RDMSR 1518
+RDMSRLIST 1519
+RDMSRri 1520
+RDMSRri_EVEX 1521
+RDPID 1522
+RDPKRUr 1523
+RDPMC 1524
+RDPRU 1525
+RDRAND 1526
+RDSEED 1527
+RDSSPD 1528
+RDSSPQ 1529
+RDTSC 1530
+RDTSCP 1531
+REG_SEQUENCE 1532
+REPNE_PREFIX 1533
+REP_MOVSB 1534
+REP_MOVSD 1535
+REP_MOVSQ 1536
+REP_MOVSW 1537
+REP_PREFIX 1538
+REP_STOSB 1539
+REP_STOSD 1540
+REP_STOSQ 1541
+REP_STOSW 1542
+RET 1543
+RETI 1544
+REX 1545
+RMPADJUST 1546
+RMPQUERY 1547
+RMPUPDATE 1548
+ROL 1549
+ROR 1550
+RORX 1551
+ROUNDPDmi 1552
+ROUNDPDri 1553
+ROUNDPSmi 1554
+ROUNDPSri 1555
+ROUNDSDmi 1556
+ROUNDSDmi_Int 1557
+ROUNDSDri 1558
+ROUNDSDri_Int 1559
+ROUNDSSmi 1560
+ROUNDSSmi_Int 1561
+ROUNDSSri 1562
+ROUNDSSri_Int 1563
+RSM 1564
+RSQRTPSm 1565
+RSQRTPSr 1566
+RSQRTSSm 1567
+RSQRTSSm_Int 1568
+RSQRTSSr 1569
+RSQRTSSr_Int 1570
+RSTORSSP 1571
+SAHF 1572
+SALC 1573
+SAR 1574
+SARX 1575
+SAVEPREVSSP 1576
+SBB 1577
+SCASB 1578
+SCASL 1579
+SCASQ 1580
+SCASW 1581
+SEAMCALL 1582
+SEAMOPS 1583
+SEAMRET 1584
+SEG_ALLOCA 1585
+SEH_BeginEpilogue 1586
+SEH_EndEpilogue 1587
+SEH_EndPrologue 1588
+SEH_PushFrame 1589
+SEH_PushReg 1590
+SEH_SaveReg 1591
+SEH_SaveXMM 1592
+SEH_SetFrame 1593
+SEH_StackAlign 1594
+SEH_StackAlloc 1595
+SEH_UnwindV 1596
+SEH_UnwindVersion 1597
+SENDUIPI 1598
+SERIALIZE 1599
+SETB_C 1600
+SETCCm 1601
+SETCCm_EVEX 1602
+SETCCr 1603
+SETCCr_EVEX 1604
+SETSSBSY 1605
+SETZUCCm 1606
+SETZUCCr 1607
+SFENCE 1608
+SGDT 1609
+SHA 1610
+SHL 1611
+SHLD 1612
+SHLDROT 1613
+SHLX 1614
+SHR 1615
+SHRD 1616
+SHRDROT 1617
+SHRX 1618
+SHUFPDrmi 1619
+SHUFPDrri 1620
+SHUFPSrmi 1621
+SHUFPSrri 1622
+SIDT 1623
+SKINIT 1624
+SLDT 1625
+SLWPCB 1626
+SMSW 1627
+SQRTPDm 1628
+SQRTPDr 1629
+SQRTPSm 1630
+SQRTPSr 1631
+SQRTSDm 1632
+SQRTSDm_Int 1633
+SQRTSDr 1634
+SQRTSDr_Int 1635
+SQRTSSm 1636
+SQRTSSm_Int 1637
+SQRTSSr 1638
+SQRTSSr_Int 1639
+SQRT_F 1640
+SQRT_Fp 1641
+SS_PREFIX 1642
+STAC 1643
+STACKALLOC_W_PROBING 1644
+STACKMAP 1645
+STATEPOINT 1646
+STC 1647
+STD 1648
+STGI 1649
+STI 1650
+STMXCSR 1651
+STOSB 1652
+STOSL 1653
+STOSQ 1654
+STOSW 1655
+STR 1656
+STRm 1657
+STTILECFG 1658
+STTILECFG_EVEX 1659
+STUI 1660
+ST_F 1661
+ST_FP 1662
+ST_FPrr 1663
+ST_Fp 1664
+ST_FpP 1665
+ST_Frr 1666
+SUB 1667
+SUBPDrm 1668
+SUBPDrr 1669
+SUBPSrm 1670
+SUBPSrr 1671
+SUBREG_TO_REG 1672
+SUBR_F 1673
+SUBR_FI 1674
+SUBR_FPrST 1675
+SUBR_FST 1676
+SUBR_Fp 1677
+SUBR_FpI 1678
+SUBR_FrST 1679
+SUBSDrm 1680
+SUBSDrm_Int 1681
+SUBSDrr 1682
+SUBSDrr_Int 1683
+SUBSSrm 1684
+SUBSSrm_Int 1685
+SUBSSrr 1686
+SUBSSrr_Int 1687
+SUB_F 1688
+SUB_FI 1689
+SUB_FPrST 1690
+SUB_FST 1691
+SUB_Fp 1692
+SUB_FpI 1693
+SUB_FrST 1694
+SWAPGS 1695
+SYSCALL 1696
+SYSENTER 1697
+SYSEXIT 1698
+SYSRET 1699
+T 1700
+TAILJMPd 1701
+TAILJMPd_CC 1702
+TAILJMPm 1703
+TAILJMPr 1704
+TCMMIMFP 1705
+TCMMRLFP 1706
+TCRETURN_HIPE 1707
+TCRETURN_WIN 1708
+TCRETURN_WINmi 1709
+TCRETURNdi 1710
+TCRETURNdicc 1711
+TCRETURNmi 1712
+TCRETURNri 1713
+TCVTROWD 1714
+TCVTROWPS 1715
+TDCALL 1716
+TDPBF 1717
+TDPBHF 1718
+TDPBSSD 1719
+TDPBSUD 1720
+TDPBUSD 1721
+TDPBUUD 1722
+TDPFP 1723
+TDPHBF 1724
+TDPHF 1725
+TEST 1726
+TESTUI 1727
+TILELOADD 1728
+TILELOADDRS 1729
+TILELOADDRST 1730
+TILELOADDRS_EVEX 1731
+TILELOADDT 1732
+TILELOADD_EVEX 1733
+TILEMOVROWrre 1734
+TILEMOVROWrri 1735
+TILERELEASE 1736
+TILESTORED 1737
+TILESTORED_EVEX 1738
+TILEZERO 1739
+TLBSYNC 1740
+TLSCall 1741
+TLS_addr 1742
+TLS_addrX 1743
+TLS_base_addr 1744
+TLS_base_addrX 1745
+TLS_desc 1746
+TMMULTF 1747
+TPAUSE 1748
+TRAP 1749
+TST_F 1750
+TST_Fp 1751
+TZCNT 1752
+TZMSK 1753
+UBSAN_UD 1754
+UCOMISDrm 1755
+UCOMISDrm_Int 1756
+UCOMISDrr 1757
+UCOMISDrr_Int 1758
+UCOMISSrm 1759
+UCOMISSrm_Int 1760
+UCOMISSrr 1761
+UCOMISSrr_Int 1762
+UCOM_FIPr 1763
+UCOM_FIr 1764
+UCOM_FPPr 1765
+UCOM_FPr 1766
+UCOM_FpIr 1767
+UCOM_Fpr 1768
+UCOM_Fr 1769
+UD 1770
+UIRET 1771
+UMONITOR 1772
+UMWAIT 1773
+UNPCKHPDrm 1774
+UNPCKHPDrr 1775
+UNPCKHPSrm 1776
+UNPCKHPSrr 1777
+UNPCKLPDrm 1778
+UNPCKLPDrr 1779
+UNPCKLPSrm 1780
+UNPCKLPSrr 1781
+URDMSRri 1782
+URDMSRri_EVEX 1783
+URDMSRrr 1784
+URDMSRrr_EVEX 1785
+UWRMSRir 1786
+UWRMSRir_EVEX 1787
+UWRMSRrr 1788
+UWRMSRrr_EVEX 1789
+V 1790
+VAARG 1791
+VAARG_X 1792
+VADDBF 1793
+VADDPDYrm 1794
+VADDPDYrr 1795
+VADDPDZ 1796
+VADDPDZrm 1797
+VADDPDZrmb 1798
+VADDPDZrmbk 1799
+VADDPDZrmbkz 1800
+VADDPDZrmk 1801
+VADDPDZrmkz 1802
+VADDPDZrr 1803
+VADDPDZrrb 1804
+VADDPDZrrbk 1805
+VADDPDZrrbkz 1806
+VADDPDZrrk 1807
+VADDPDZrrkz 1808
+VADDPDrm 1809
+VADDPDrr 1810
+VADDPHZ 1811
+VADDPHZrm 1812
+VADDPHZrmb 1813
+VADDPHZrmbk 1814
+VADDPHZrmbkz 1815
+VADDPHZrmk 1816
+VADDPHZrmkz 1817
+VADDPHZrr 1818
+VADDPHZrrb 1819
+VADDPHZrrbk 1820
+VADDPHZrrbkz 1821
+VADDPHZrrk 1822
+VADDPHZrrkz 1823
+VADDPSYrm 1824
+VADDPSYrr 1825
+VADDPSZ 1826
+VADDPSZrm 1827
+VADDPSZrmb 1828
+VADDPSZrmbk 1829
+VADDPSZrmbkz 1830
+VADDPSZrmk 1831
+VADDPSZrmkz 1832
+VADDPSZrr 1833
+VADDPSZrrb 1834
+VADDPSZrrbk 1835
+VADDPSZrrbkz 1836
+VADDPSZrrk 1837
+VADDPSZrrkz 1838
+VADDPSrm 1839
+VADDPSrr 1840
+VADDSDZrm 1841
+VADDSDZrm_Int 1842
+VADDSDZrmk_Int 1843
+VADDSDZrmkz_Int 1844
+VADDSDZrr 1845
+VADDSDZrr_Int 1846
+VADDSDZrrb_Int 1847
+VADDSDZrrbk_Int 1848
+VADDSDZrrbkz_Int 1849
+VADDSDZrrk_Int 1850
+VADDSDZrrkz_Int 1851
+VADDSDrm 1852
+VADDSDrm_Int 1853
+VADDSDrr 1854
+VADDSDrr_Int 1855
+VADDSHZrm 1856
+VADDSHZrm_Int 1857
+VADDSHZrmk_Int 1858
+VADDSHZrmkz_Int 1859
+VADDSHZrr 1860
+VADDSHZrr_Int 1861
+VADDSHZrrb_Int 1862
+VADDSHZrrbk_Int 1863
+VADDSHZrrbkz_Int 1864
+VADDSHZrrk_Int 1865
+VADDSHZrrkz_Int 1866
+VADDSSZrm 1867
+VADDSSZrm_Int 1868
+VADDSSZrmk_Int 1869
+VADDSSZrmkz_Int 1870
+VADDSSZrr 1871
+VADDSSZrr_Int 1872
+VADDSSZrrb_Int 1873
+VADDSSZrrbk_Int 1874
+VADDSSZrrbkz_Int 1875
+VADDSSZrrk_Int 1876
+VADDSSZrrkz_Int 1877
+VADDSSrm 1878
+VADDSSrm_Int 1879
+VADDSSrr 1880
+VADDSSrr_Int 1881
+VADDSUBPDYrm 1882
+VADDSUBPDYrr 1883
+VADDSUBPDrm 1884
+VADDSUBPDrr 1885
+VADDSUBPSYrm 1886
+VADDSUBPSYrr 1887
+VADDSUBPSrm 1888
+VADDSUBPSrr 1889
+VAESDECLASTYrm 1890
+VAESDECLASTYrr 1891
+VAESDECLASTZ 1892
+VAESDECLASTZrm 1893
+VAESDECLASTZrr 1894
+VAESDECLASTrm 1895
+VAESDECLASTrr 1896
+VAESDECYrm 1897
+VAESDECYrr 1898
+VAESDECZ 1899
+VAESDECZrm 1900
+VAESDECZrr 1901
+VAESDECrm 1902
+VAESDECrr 1903
+VAESENCLASTYrm 1904
+VAESENCLASTYrr 1905
+VAESENCLASTZ 1906
+VAESENCLASTZrm 1907
+VAESENCLASTZrr 1908
+VAESENCLASTrm 1909
+VAESENCLASTrr 1910
+VAESENCYrm 1911
+VAESENCYrr 1912
+VAESENCZ 1913
+VAESENCZrm 1914
+VAESENCZrr 1915
+VAESENCrm 1916
+VAESENCrr 1917
+VAESIMCrm 1918
+VAESIMCrr 1919
+VAESKEYGENASSISTrmi 1920
+VAESKEYGENASSISTrri 1921
+VALIGNDZ 1922
+VALIGNDZrmbi 1923
+VALIGNDZrmbik 1924
+VALIGNDZrmbikz 1925
+VALIGNDZrmi 1926
+VALIGNDZrmik 1927
+VALIGNDZrmikz 1928
+VALIGNDZrri 1929
+VALIGNDZrrik 1930
+VALIGNDZrrikz 1931
+VALIGNQZ 1932
+VALIGNQZrmbi 1933
+VALIGNQZrmbik 1934
+VALIGNQZrmbikz 1935
+VALIGNQZrmi 1936
+VALIGNQZrmik 1937
+VALIGNQZrmikz 1938
+VALIGNQZrri 1939
+VALIGNQZrrik 1940
+VALIGNQZrrikz 1941
+VANDNPDYrm 1942
+VANDNPDYrr 1943
+VANDNPDZ 1944
+VANDNPDZrm 1945
+VANDNPDZrmb 1946
+VANDNPDZrmbk 1947
+VANDNPDZrmbkz 1948
+VANDNPDZrmk 1949
+VANDNPDZrmkz 1950
+VANDNPDZrr 1951
+VANDNPDZrrk 1952
+VANDNPDZrrkz 1953
+VANDNPDrm 1954
+VANDNPDrr 1955
+VANDNPSYrm 1956
+VANDNPSYrr 1957
+VANDNPSZ 1958
+VANDNPSZrm 1959
+VANDNPSZrmb 1960
+VANDNPSZrmbk 1961
+VANDNPSZrmbkz 1962
+VANDNPSZrmk 1963
+VANDNPSZrmkz 1964
+VANDNPSZrr 1965
+VANDNPSZrrk 1966
+VANDNPSZrrkz 1967
+VANDNPSrm 1968
+VANDNPSrr 1969
+VANDPDYrm 1970
+VANDPDYrr 1971
+VANDPDZ 1972
+VANDPDZrm 1973
+VANDPDZrmb 1974
+VANDPDZrmbk 1975
+VANDPDZrmbkz 1976
+VANDPDZrmk 1977
+VANDPDZrmkz 1978
+VANDPDZrr 1979
+VANDPDZrrk 1980
+VANDPDZrrkz 1981
+VANDPDrm 1982
+VANDPDrr 1983
+VANDPSYrm 1984
+VANDPSYrr 1985
+VANDPSZ 1986
+VANDPSZrm 1987
+VANDPSZrmb 1988
+VANDPSZrmbk 1989
+VANDPSZrmbkz 1990
+VANDPSZrmk 1991
+VANDPSZrmkz 1992
+VANDPSZrr 1993
+VANDPSZrrk 1994
+VANDPSZrrkz 1995
+VANDPSrm 1996
+VANDPSrr 1997
+VASTART_SAVE_XMM_REGS 1998
+VBCSTNEBF 1999
+VBCSTNESH 2000
+VBLENDMPDZ 2001
+VBLENDMPDZrm 2002
+VBLENDMPDZrmb 2003
+VBLENDMPDZrmbk 2004
+VBLENDMPDZrmbkz 2005
+VBLENDMPDZrmk 2006
+VBLENDMPDZrmkz 2007
+VBLENDMPDZrr 2008
+VBLENDMPDZrrk 2009
+VBLENDMPDZrrkz 2010
+VBLENDMPSZ 2011
+VBLENDMPSZrm 2012
+VBLENDMPSZrmb 2013
+VBLENDMPSZrmbk 2014
+VBLENDMPSZrmbkz 2015
+VBLENDMPSZrmk 2016
+VBLENDMPSZrmkz 2017
+VBLENDMPSZrr 2018
+VBLENDMPSZrrk 2019
+VBLENDMPSZrrkz 2020
+VBLENDPDYrmi 2021
+VBLENDPDYrri 2022
+VBLENDPDrmi 2023
+VBLENDPDrri 2024
+VBLENDPSYrmi 2025
+VBLENDPSYrri 2026
+VBLENDPSrmi 2027
+VBLENDPSrri 2028
+VBLENDVPDYrmr 2029
+VBLENDVPDYrrr 2030
+VBLENDVPDrmr 2031
+VBLENDVPDrrr 2032
+VBLENDVPSYrmr 2033
+VBLENDVPSYrrr 2034
+VBLENDVPSrmr 2035
+VBLENDVPSrrr 2036
+VBROADCASTF 2037
+VBROADCASTI 2038
+VBROADCASTSDYrm 2039
+VBROADCASTSDYrr 2040
+VBROADCASTSDZ 2041
+VBROADCASTSDZrm 2042
+VBROADCASTSDZrmk 2043
+VBROADCASTSDZrmkz 2044
+VBROADCASTSDZrr 2045
+VBROADCASTSDZrrk 2046
+VBROADCASTSDZrrkz 2047
+VBROADCASTSSYrm 2048
+VBROADCASTSSYrr 2049
+VBROADCASTSSZ 2050
+VBROADCASTSSZrm 2051
+VBROADCASTSSZrmk 2052
+VBROADCASTSSZrmkz 2053
+VBROADCASTSSZrr 2054
+VBROADCASTSSZrrk 2055
+VBROADCASTSSZrrkz 2056
+VBROADCASTSSrm 2057
+VBROADCASTSSrr 2058
+VCMPBF 2059
+VCMPPDYrmi 2060
+VCMPPDYrri 2061
+VCMPPDZ 2062
+VCMPPDZrmbi 2063
+VCMPPDZrmbik 2064
+VCMPPDZrmi 2065
+VCMPPDZrmik 2066
+VCMPPDZrri 2067
+VCMPPDZrrib 2068
+VCMPPDZrribk 2069
+VCMPPDZrrik 2070
+VCMPPDrmi 2071
+VCMPPDrri 2072
+VCMPPHZ 2073
+VCMPPHZrmbi 2074
+VCMPPHZrmbik 2075
+VCMPPHZrmi 2076
+VCMPPHZrmik 2077
+VCMPPHZrri 2078
+VCMPPHZrrib 2079
+VCMPPHZrribk 2080
+VCMPPHZrrik 2081
+VCMPPSYrmi 2082
+VCMPPSYrri 2083
+VCMPPSZ 2084
+VCMPPSZrmbi 2085
+VCMPPSZrmbik 2086
+VCMPPSZrmi 2087
+VCMPPSZrmik 2088
+VCMPPSZrri 2089
+VCMPPSZrrib 2090
+VCMPPSZrribk 2091
+VCMPPSZrrik 2092
+VCMPPSrmi 2093
+VCMPPSrri 2094
+VCMPSDZrmi 2095
+VCMPSDZrmi_Int 2096
+VCMPSDZrmik_Int 2097
+VCMPSDZrri 2098
+VCMPSDZrri_Int 2099
+VCMPSDZrrib_Int 2100
+VCMPSDZrribk_Int 2101
+VCMPSDZrrik_Int 2102
+VCMPSDrmi 2103
+VCMPSDrmi_Int 2104
+VCMPSDrri 2105
+VCMPSDrri_Int 2106
+VCMPSHZrmi 2107
+VCMPSHZrmi_Int 2108
+VCMPSHZrmik_Int 2109
+VCMPSHZrri 2110
+VCMPSHZrri_Int 2111
+VCMPSHZrrib_Int 2112
+VCMPSHZrribk_Int 2113
+VCMPSHZrrik_Int 2114
+VCMPSSZrmi 2115
+VCMPSSZrmi_Int 2116
+VCMPSSZrmik_Int 2117
+VCMPSSZrri 2118
+VCMPSSZrri_Int 2119
+VCMPSSZrrib_Int 2120
+VCMPSSZrribk_Int 2121
+VCMPSSZrrik_Int 2122
+VCMPSSrmi 2123
+VCMPSSrmi_Int 2124
+VCMPSSrri 2125
+VCMPSSrri_Int 2126
+VCOMISBF 2127
+VCOMISDZrm 2128
+VCOMISDZrm_Int 2129
+VCOMISDZrr 2130
+VCOMISDZrr_Int 2131
+VCOMISDZrrb 2132
+VCOMISDrm 2133
+VCOMISDrm_Int 2134
+VCOMISDrr 2135
+VCOMISDrr_Int 2136
+VCOMISHZrm 2137
+VCOMISHZrm_Int 2138
+VCOMISHZrr 2139
+VCOMISHZrr_Int 2140
+VCOMISHZrrb 2141
+VCOMISSZrm 2142
+VCOMISSZrm_Int 2143
+VCOMISSZrr 2144
+VCOMISSZrr_Int 2145
+VCOMISSZrrb 2146
+VCOMISSrm 2147
+VCOMISSrm_Int 2148
+VCOMISSrr 2149
+VCOMISSrr_Int 2150
+VCOMPRESSPDZ 2151
+VCOMPRESSPDZmr 2152
+VCOMPRESSPDZmrk 2153
+VCOMPRESSPDZrr 2154
+VCOMPRESSPDZrrk 2155
+VCOMPRESSPDZrrkz 2156
+VCOMPRESSPSZ 2157
+VCOMPRESSPSZmr 2158
+VCOMPRESSPSZmrk 2159
+VCOMPRESSPSZrr 2160
+VCOMPRESSPSZrrk 2161
+VCOMPRESSPSZrrkz 2162
+VCOMXSDZrm_Int 2163
+VCOMXSDZrr_Int 2164
+VCOMXSDZrrb_Int 2165
+VCOMXSHZrm_Int 2166
+VCOMXSHZrr_Int 2167
+VCOMXSHZrrb_Int 2168
+VCOMXSSZrm_Int 2169
+VCOMXSSZrr_Int 2170
+VCOMXSSZrrb_Int 2171
+VCVT 2172
+VCVTBF 2173
+VCVTBIASPH 2174
+VCVTDQ 2175
+VCVTHF 2176
+VCVTNE 2177
+VCVTNEEBF 2178
+VCVTNEEPH 2179
+VCVTNEOBF 2180
+VCVTNEOPH 2181
+VCVTNEPS 2182
+VCVTPD 2183
+VCVTPH 2184
+VCVTPS 2185
+VCVTQQ 2186
+VCVTSD 2187
+VCVTSH 2188
+VCVTSI 2189
+VCVTSS 2190
+VCVTTBF 2191
+VCVTTPD 2192
+VCVTTPH 2193
+VCVTTPS 2194
+VCVTTSD 2195
+VCVTTSH 2196
+VCVTTSS 2197
+VCVTUDQ 2198
+VCVTUQQ 2199
+VCVTUSI 2200
+VCVTUW 2201
+VCVTW 2202
+VDBPSADBWZ 2203
+VDBPSADBWZrmi 2204
+VDBPSADBWZrmik 2205
+VDBPSADBWZrmikz 2206
+VDBPSADBWZrri 2207
+VDBPSADBWZrrik 2208
+VDBPSADBWZrrikz 2209
+VDIVBF 2210
+VDIVPDYrm 2211
+VDIVPDYrr 2212
+VDIVPDZ 2213
+VDIVPDZrm 2214
+VDIVPDZrmb 2215
+VDIVPDZrmbk 2216
+VDIVPDZrmbkz 2217
+VDIVPDZrmk 2218
+VDIVPDZrmkz 2219
+VDIVPDZrr 2220
+VDIVPDZrrb 2221
+VDIVPDZrrbk 2222
+VDIVPDZrrbkz 2223
+VDIVPDZrrk 2224
+VDIVPDZrrkz 2225
+VDIVPDrm 2226
+VDIVPDrr 2227
+VDIVPHZ 2228
+VDIVPHZrm 2229
+VDIVPHZrmb 2230
+VDIVPHZrmbk 2231
+VDIVPHZrmbkz 2232
+VDIVPHZrmk 2233
+VDIVPHZrmkz 2234
+VDIVPHZrr 2235
+VDIVPHZrrb 2236
+VDIVPHZrrbk 2237
+VDIVPHZrrbkz 2238
+VDIVPHZrrk 2239
+VDIVPHZrrkz 2240
+VDIVPSYrm 2241
+VDIVPSYrr 2242
+VDIVPSZ 2243
+VDIVPSZrm 2244
+VDIVPSZrmb 2245
+VDIVPSZrmbk 2246
+VDIVPSZrmbkz 2247
+VDIVPSZrmk 2248
+VDIVPSZrmkz 2249
+VDIVPSZrr 2250
+VDIVPSZrrb 2251
+VDIVPSZrrbk 2252
+VDIVPSZrrbkz 2253
+VDIVPSZrrk 2254
+VDIVPSZrrkz 2255
+VDIVPSrm 2256
+VDIVPSrr 2257
+VDIVSDZrm 2258
+VDIVSDZrm_Int 2259
+VDIVSDZrmk_Int 2260
+VDIVSDZrmkz_Int 2261
+VDIVSDZrr 2262
+VDIVSDZrr_Int 2263
+VDIVSDZrrb_Int 2264
+VDIVSDZrrbk_Int 2265
+VDIVSDZrrbkz_Int 2266
+VDIVSDZrrk_Int 2267
+VDIVSDZrrkz_Int 2268
+VDIVSDrm 2269
+VDIVSDrm_Int 2270
+VDIVSDrr 2271
+VDIVSDrr_Int 2272
+VDIVSHZrm 2273
+VDIVSHZrm_Int 2274
+VDIVSHZrmk_Int 2275
+VDIVSHZrmkz_Int 2276
+VDIVSHZrr 2277
+VDIVSHZrr_Int 2278
+VDIVSHZrrb_Int 2279
+VDIVSHZrrbk_Int 2280
+VDIVSHZrrbkz_Int 2281
+VDIVSHZrrk_Int 2282
+VDIVSHZrrkz_Int 2283
+VDIVSSZrm 2284
+VDIVSSZrm_Int 2285
+VDIVSSZrmk_Int 2286
+VDIVSSZrmkz_Int 2287
+VDIVSSZrr 2288
+VDIVSSZrr_Int 2289
+VDIVSSZrrb_Int 2290
+VDIVSSZrrbk_Int 2291
+VDIVSSZrrbkz_Int 2292
+VDIVSSZrrk_Int 2293
+VDIVSSZrrkz_Int 2294
+VDIVSSrm 2295
+VDIVSSrm_Int 2296
+VDIVSSrr 2297
+VDIVSSrr_Int 2298
+VDPBF 2299
+VDPPDrmi 2300
+VDPPDrri 2301
+VDPPHPSZ 2302
+VDPPHPSZm 2303
+VDPPHPSZmb 2304
+VDPPHPSZmbk 2305
+VDPPHPSZmbkz 2306
+VDPPHPSZmk 2307
+VDPPHPSZmkz 2308
+VDPPHPSZr 2309
+VDPPHPSZrk 2310
+VDPPHPSZrkz 2311
+VDPPSYrmi 2312
+VDPPSYrri 2313
+VDPPSrmi 2314
+VDPPSrri 2315
+VERRm 2316
+VERRr 2317
+VERWm 2318
+VERWr 2319
+VEXP 2320
+VEXPANDPDZ 2321
+VEXPANDPDZrm 2322
+VEXPANDPDZrmk 2323
+VEXPANDPDZrmkz 2324
+VEXPANDPDZrr 2325
+VEXPANDPDZrrk 2326
+VEXPANDPDZrrkz 2327
+VEXPANDPSZ 2328
+VEXPANDPSZrm 2329
+VEXPANDPSZrmk 2330
+VEXPANDPSZrmkz 2331
+VEXPANDPSZrr 2332
+VEXPANDPSZrrk 2333
+VEXPANDPSZrrkz 2334
+VEXTRACTF 2335
+VEXTRACTI 2336
+VEXTRACTPSZmri 2337
+VEXTRACTPSZrri 2338
+VEXTRACTPSmri 2339
+VEXTRACTPSrri 2340
+VFCMADDCPHZ 2341
+VFCMADDCPHZm 2342
+VFCMADDCPHZmb 2343
+VFCMADDCPHZmbk 2344
+VFCMADDCPHZmbkz 2345
+VFCMADDCPHZmk 2346
+VFCMADDCPHZmkz 2347
+VFCMADDCPHZr 2348
+VFCMADDCPHZrb 2349
+VFCMADDCPHZrbk 2350
+VFCMADDCPHZrbkz 2351
+VFCMADDCPHZrk 2352
+VFCMADDCPHZrkz 2353
+VFCMADDCSHZm 2354
+VFCMADDCSHZmk 2355
+VFCMADDCSHZmkz 2356
+VFCMADDCSHZr 2357
+VFCMADDCSHZrb 2358
+VFCMADDCSHZrbk 2359
+VFCMADDCSHZrbkz 2360
+VFCMADDCSHZrk 2361
+VFCMADDCSHZrkz 2362
+VFCMULCPHZ 2363
+VFCMULCPHZrm 2364
+VFCMULCPHZrmb 2365
+VFCMULCPHZrmbk 2366
+VFCMULCPHZrmbkz 2367
+VFCMULCPHZrmk 2368
+VFCMULCPHZrmkz 2369
+VFCMULCPHZrr 2370
+VFCMULCPHZrrb 2371
+VFCMULCPHZrrbk 2372
+VFCMULCPHZrrbkz 2373
+VFCMULCPHZrrk 2374
+VFCMULCPHZrrkz 2375
+VFCMULCSHZrm 2376
+VFCMULCSHZrmk 2377
+VFCMULCSHZrmkz 2378
+VFCMULCSHZrr 2379
+VFCMULCSHZrrb 2380
+VFCMULCSHZrrbk 2381
+VFCMULCSHZrrbkz 2382
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+VSQRTPHZrk 6523
+VSQRTPHZrkz 6524
+VSQRTPSYm 6525
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+VSQRTPSZ 6527
+VSQRTPSZm 6528
+VSQRTPSZmb 6529
+VSQRTPSZmbk 6530
+VSQRTPSZmbkz 6531
+VSQRTPSZmk 6532
+VSQRTPSZmkz 6533
+VSQRTPSZr 6534
+VSQRTPSZrb 6535
+VSQRTPSZrbk 6536
+VSQRTPSZrbkz 6537
+VSQRTPSZrk 6538
+VSQRTPSZrkz 6539
+VSQRTPSm 6540
+VSQRTPSr 6541
+VSQRTSDZm 6542
+VSQRTSDZm_Int 6543
+VSQRTSDZmk_Int 6544
+VSQRTSDZmkz_Int 6545
+VSQRTSDZr 6546
+VSQRTSDZr_Int 6547
+VSQRTSDZrb_Int 6548
+VSQRTSDZrbk_Int 6549
+VSQRTSDZrbkz_Int 6550
+VSQRTSDZrk_Int 6551
+VSQRTSDZrkz_Int 6552
+VSQRTSDm 6553
+VSQRTSDm_Int 6554
+VSQRTSDr 6555
+VSQRTSDr_Int 6556
+VSQRTSHZm 6557
+VSQRTSHZm_Int 6558
+VSQRTSHZmk_Int 6559
+VSQRTSHZmkz_Int 6560
+VSQRTSHZr 6561
+VSQRTSHZr_Int 6562
+VSQRTSHZrb_Int 6563
+VSQRTSHZrbk_Int 6564
+VSQRTSHZrbkz_Int 6565
+VSQRTSHZrk_Int 6566
+VSQRTSHZrkz_Int 6567
+VSQRTSSZm 6568
+VSQRTSSZm_Int 6569
+VSQRTSSZmk_Int 6570
+VSQRTSSZmkz_Int 6571
+VSQRTSSZr 6572
+VSQRTSSZr_Int 6573
+VSQRTSSZrb_Int 6574
+VSQRTSSZrbk_Int 6575
+VSQRTSSZrbkz_Int 6576
+VSQRTSSZrk_Int 6577
+VSQRTSSZrkz_Int 6578
+VSQRTSSm 6579
+VSQRTSSm_Int 6580
+VSQRTSSr 6581
+VSQRTSSr_Int 6582
+VSTMXCSR 6583
+VSUBBF 6584
+VSUBPDYrm 6585
+VSUBPDYrr 6586
+VSUBPDZ 6587
+VSUBPDZrm 6588
+VSUBPDZrmb 6589
+VSUBPDZrmbk 6590
+VSUBPDZrmbkz 6591
+VSUBPDZrmk 6592
+VSUBPDZrmkz 6593
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+VSUBPDZrrb 6595
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+VSUBPDZrrbkz 6597
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+VSUBPDZrrkz 6599
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+VSUBPHZrrb 6610
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+VSUBPSZrrbk 6626
+VSUBPSZrrbkz 6627
+VSUBPSZrrk 6628
+VSUBPSZrrkz 6629
+VSUBPSrm 6630
+VSUBPSrr 6631
+VSUBSDZrm 6632
+VSUBSDZrm_Int 6633
+VSUBSDZrmk_Int 6634
+VSUBSDZrmkz_Int 6635
+VSUBSDZrr 6636
+VSUBSDZrr_Int 6637
+VSUBSDZrrb_Int 6638
+VSUBSDZrrbk_Int 6639
+VSUBSDZrrbkz_Int 6640
+VSUBSDZrrk_Int 6641
+VSUBSDZrrkz_Int 6642
+VSUBSDrm 6643
+VSUBSDrm_Int 6644
+VSUBSDrr 6645
+VSUBSDrr_Int 6646
+VSUBSHZrm 6647
+VSUBSHZrm_Int 6648
+VSUBSHZrmk_Int 6649
+VSUBSHZrmkz_Int 6650
+VSUBSHZrr 6651
+VSUBSHZrr_Int 6652
+VSUBSHZrrb_Int 6653
+VSUBSHZrrbk_Int 6654
+VSUBSHZrrbkz_Int 6655
+VSUBSHZrrk_Int 6656
+VSUBSHZrrkz_Int 6657
+VSUBSSZrm 6658
+VSUBSSZrm_Int 6659
+VSUBSSZrmk_Int 6660
+VSUBSSZrmkz_Int 6661
+VSUBSSZrr 6662
+VSUBSSZrr_Int 6663
+VSUBSSZrrb_Int 6664
+VSUBSSZrrbk_Int 6665
+VSUBSSZrrbkz_Int 6666
+VSUBSSZrrk_Int 6667
+VSUBSSZrrkz_Int 6668
+VSUBSSrm 6669
+VSUBSSrm_Int 6670
+VSUBSSrr 6671
+VSUBSSrr_Int 6672
+VTESTPDYrm 6673
+VTESTPDYrr 6674
+VTESTPDrm 6675
+VTESTPDrr 6676
+VTESTPSYrm 6677
+VTESTPSYrr 6678
+VTESTPSrm 6679
+VTESTPSrr 6680
+VUCOMISDZrm 6681
+VUCOMISDZrm_Int 6682
+VUCOMISDZrr 6683
+VUCOMISDZrr_Int 6684
+VUCOMISDZrrb 6685
+VUCOMISDrm 6686
+VUCOMISDrm_Int 6687
+VUCOMISDrr 6688
+VUCOMISDrr_Int 6689
+VUCOMISHZrm 6690
+VUCOMISHZrm_Int 6691
+VUCOMISHZrr 6692
+VUCOMISHZrr_Int 6693
+VUCOMISHZrrb 6694
+VUCOMISSZrm 6695
+VUCOMISSZrm_Int 6696
+VUCOMISSZrr 6697
+VUCOMISSZrr_Int 6698
+VUCOMISSZrrb 6699
+VUCOMISSrm 6700
+VUCOMISSrm_Int 6701
+VUCOMISSrr 6702
+VUCOMISSrr_Int 6703
+VUCOMXSDZrm 6704
+VUCOMXSDZrm_Int 6705
+VUCOMXSDZrr 6706
+VUCOMXSDZrr_Int 6707
+VUCOMXSDZrrb_Int 6708
+VUCOMXSHZrm 6709
+VUCOMXSHZrm_Int 6710
+VUCOMXSHZrr 6711
+VUCOMXSHZrr_Int 6712
+VUCOMXSHZrrb_Int 6713
+VUCOMXSSZrm 6714
+VUCOMXSSZrm_Int 6715
+VUCOMXSSZrr 6716
+VUCOMXSSZrr_Int 6717
+VUCOMXSSZrrb_Int 6718
+VUNPCKHPDYrm 6719
+VUNPCKHPDYrr 6720
+VUNPCKHPDZ 6721
+VUNPCKHPDZrm 6722
+VUNPCKHPDZrmb 6723
+VUNPCKHPDZrmbk 6724
+VUNPCKHPDZrmbkz 6725
+VUNPCKHPDZrmk 6726
+VUNPCKHPDZrmkz 6727
+VUNPCKHPDZrr 6728
+VUNPCKHPDZrrk 6729
+VUNPCKHPDZrrkz 6730
+VUNPCKHPDrm 6731
+VUNPCKHPDrr 6732
+VUNPCKHPSYrm 6733
+VUNPCKHPSYrr 6734
+VUNPCKHPSZ 6735
+VUNPCKHPSZrm 6736
+VUNPCKHPSZrmb 6737
+VUNPCKHPSZrmbk 6738
+VUNPCKHPSZrmbkz 6739
+VUNPCKHPSZrmk 6740
+VUNPCKHPSZrmkz 6741
+VUNPCKHPSZrr 6742
+VUNPCKHPSZrrk 6743
+VUNPCKHPSZrrkz 6744
+VUNPCKHPSrm 6745
+VUNPCKHPSrr 6746
+VUNPCKLPDYrm 6747
+VUNPCKLPDYrr 6748
+VUNPCKLPDZ 6749
+VUNPCKLPDZrm 6750
+VUNPCKLPDZrmb 6751
+VUNPCKLPDZrmbk 6752
+VUNPCKLPDZrmbkz 6753
+VUNPCKLPDZrmk 6754
+VUNPCKLPDZrmkz 6755
+VUNPCKLPDZrr 6756
+VUNPCKLPDZrrk 6757
+VUNPCKLPDZrrkz 6758
+VUNPCKLPDrm 6759
+VUNPCKLPDrr 6760
+VUNPCKLPSYrm 6761
+VUNPCKLPSYrr 6762
+VUNPCKLPSZ 6763
+VUNPCKLPSZrm 6764
+VUNPCKLPSZrmb 6765
+VUNPCKLPSZrmbk 6766
+VUNPCKLPSZrmbkz 6767
+VUNPCKLPSZrmk 6768
+VUNPCKLPSZrmkz 6769
+VUNPCKLPSZrr 6770
+VUNPCKLPSZrrk 6771
+VUNPCKLPSZrrkz 6772
+VUNPCKLPSrm 6773
+VUNPCKLPSrr 6774
+VXORPDYrm 6775
+VXORPDYrr 6776
+VXORPDZ 6777
+VXORPDZrm 6778
+VXORPDZrmb 6779
+VXORPDZrmbk 6780
+VXORPDZrmbkz 6781
+VXORPDZrmk 6782
+VXORPDZrmkz 6783
+VXORPDZrr 6784
+VXORPDZrrk 6785
+VXORPDZrrkz 6786
+VXORPDrm 6787
+VXORPDrr 6788
+VXORPSYrm 6789
+VXORPSYrr 6790
+VXORPSZ 6791
+VXORPSZrm 6792
+VXORPSZrmb 6793
+VXORPSZrmbk 6794
+VXORPSZrmbkz 6795
+VXORPSZrmk 6796
+VXORPSZrmkz 6797
+VXORPSZrr 6798
+VXORPSZrrk 6799
+VXORPSZrrkz 6800
+VXORPSrm 6801
+VXORPSrr 6802
+VZEROALL 6803
+VZEROUPPER 6804
+V_SET 6805
+V_SETALLONES 6806
+WAIT 6807
+WBINVD 6808
+WBNOINVD 6809
+WRFLAGS 6810
+WRFSBASE 6811
+WRGSBASE 6812
+WRMSR 6813
+WRMSRLIST 6814
+WRMSRNS 6815
+WRMSRNSir 6816
+WRMSRNSir_EVEX 6817
+WRPKRUr 6818
+WRSSD 6819
+WRSSD_EVEX 6820
+WRSSQ 6821
+WRSSQ_EVEX 6822
+WRUSSD 6823
+WRUSSD_EVEX 6824
+WRUSSQ 6825
+WRUSSQ_EVEX 6826
+XABORT 6827
+XABORT_DEF 6828
+XACQUIRE_PREFIX 6829
+XADD 6830
+XAM_F 6831
+XAM_Fp 6832
+XBEGIN 6833
+XCHG 6834
+XCH_F 6835
+XCRYPTCBC 6836
+XCRYPTCFB 6837
+XCRYPTCTR 6838
+XCRYPTECB 6839
+XCRYPTOFB 6840
+XEND 6841
+XGETBV 6842
+XLAT 6843
+XOR 6844
+XORPDrm 6845
+XORPDrr 6846
+XORPSrm 6847
+XORPSrr 6848
+XRELEASE_PREFIX 6849
+XRESLDTRK 6850
+XRSTOR 6851
+XRSTORS 6852
+XSAVE 6853
+XSAVEC 6854
+XSAVEOPT 6855
+XSAVES 6856
+XSETBV 6857
+XSHA 6858
+XSTORE 6859
+XSUSLDTRK 6860
+XTEST 6861
+Immediate 6862
+CImmediate 6863
+FPImmediate 6864
+MBB 6865
+FrameIndex 6866
+ConstantPoolIndex 6867
+TargetIndex 6868
+JumpTableIndex 6869
+ExternalSymbol 6870
+GlobalAddress 6871
+BlockAddress 6872
+RegisterMask 6873
+RegisterLiveOut 6874
+Metadata 6875
+MCSymbol 6876
+CFIIndex 6877
+IntrinsicID 6878
+Predicate 6879
+ShuffleMask 6880
+PhyReg_GR8 6881
+PhyReg_GRH8 6882
+PhyReg_GR8_NOREX2 6883
+PhyReg_GR8_NOREX 6884
+PhyReg_GR8_ABCD_H 6885
+PhyReg_GR8_ABCD_L 6886
+PhyReg_GRH16 6887
+PhyReg_GR16 6888
+PhyReg_GR16_NOREX2 6889
+PhyReg_GR16_NOREX 6890
+PhyReg_VK1 6891
+PhyReg_VK16 6892
+PhyReg_VK2 6893
+PhyReg_VK4 6894
+PhyReg_VK8 6895
+PhyReg_VK16WM 6896
+PhyReg_VK1WM 6897
+PhyReg_VK2WM 6898
+PhyReg_VK4WM 6899
+PhyReg_VK8WM 6900
+PhyReg_SEGMENT_REG 6901
+PhyReg_GR16_ABCD 6902
+PhyReg_FPCCR 6903
+PhyReg_FR16X 6904
+PhyReg_FR16 6905
+PhyReg_VK16PAIR 6906
+PhyReg_VK1PAIR 6907
+PhyReg_VK2PAIR 6908
+PhyReg_VK4PAIR 6909
+PhyReg_VK8PAIR 6910
+PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6911
+PhyReg_LOW32_ADDR_ACCESS_RBP 6912
+PhyReg_LOW32_ADDR_ACCESS 6913
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6914
+PhyReg_FR32X 6915
+PhyReg_GR32 6916
+PhyReg_GR32_NOSP 6917
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6918
+PhyReg_DEBUG_REG 6919
+PhyReg_FR32 6920
+PhyReg_GR32_NOREX2 6921
+PhyReg_GR32_NOREX2_NOSP 6922
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6923
+PhyReg_GR32_NOREX 6924
+PhyReg_VK32 6925
+PhyReg_GR32_NOREX_NOSP 6926
+PhyReg_RFP32 6927
+PhyReg_VK32WM 6928
+PhyReg_GR32_ABCD 6929
+PhyReg_GR32_TC 6930
+PhyReg_GR32_ABCD_and_GR32_TC 6931
+PhyReg_GR32_AD 6932
+PhyReg_GR32_ArgRef 6933
+PhyReg_GR32_BPSP 6934
+PhyReg_GR32_BSI 6935
+PhyReg_GR32_CB 6936
+PhyReg_GR32_DC 6937
+PhyReg_GR32_DIBP 6938
+PhyReg_GR32_SIDI 6939
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6940
+PhyReg_CCR 6941
+PhyReg_DFCCR 6942
+PhyReg_GR32_ABCD_and_GR32_BSI 6943
+PhyReg_GR32_AD_and_GR32_ArgRef 6944
+PhyReg_GR32_ArgRef_and_GR32_CB 6945
+PhyReg_GR32_BPSP_and_GR32_DIBP 6946
+PhyReg_GR32_BPSP_and_GR32_TC 6947
+PhyReg_GR32_BSI_and_GR32_SIDI 6948
+PhyReg_GR32_DIBP_and_GR32_SIDI 6949
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6950
+PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6951
+PhyReg_RFP64 6952
+PhyReg_GR64 6953
+PhyReg_FR64X 6954
+PhyReg_GR64_with_sub_8bit 6955
+PhyReg_GR64_NOSP 6956
+PhyReg_GR64_NOREX2 6957
+PhyReg_CONTROL_REG 6958
+PhyReg_FR64 6959
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6960
+PhyReg_GR64_NOREX2_NOSP 6961
+PhyReg_GR64PLTSafe 6962
+PhyReg_GR64_TC 6963
+PhyReg_GR64_NOREX 6964
+PhyReg_GR64_TCW64 6965
+PhyReg_GR64_TC_with_sub_8bit 6966
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6967
+PhyReg_GR64_TCW64_with_sub_8bit 6968
+PhyReg_GR64_TC_and_GR64_TCW64 6969
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6970
+PhyReg_VK64 6971
+PhyReg_VR64 6972
+PhyReg_GR64PLTSafe_and_GR64_TC 6973
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6974
+PhyReg_GR64_NOREX_NOSP 6975
+PhyReg_GR64_NOREX_and_GR64_TC 6976
+PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6977
+PhyReg_VK64WM 6978
+PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6979
+PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6980
+PhyReg_GR64PLTSafe_and_GR64_TCW64 6981
+PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6982
+PhyReg_GR64_NOREX_and_GR64_TCW64 6983
+PhyReg_GR64_ABCD 6984
+PhyReg_GR64_with_sub_32bit_in_GR32_TC 6985
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6986
+PhyReg_GR64_AD 6987
+PhyReg_GR64_ArgRef 6988
+PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6989
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6990
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6991
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6992
+PhyReg_GR64_with_sub_32bit_in_GR32_CB 6993
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6994
+PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6995
+PhyReg_GR64_A 6996
+PhyReg_GR64_ArgRef_and_GR64_TC 6997
+PhyReg_GR64_and_LOW32_ADDR_ACCESS 6998
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 6999
+PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7000
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7001
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7002
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7003
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7004
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7005
+PhyReg_RST 7006
+PhyReg_RFP80 7007
+PhyReg_RFP80_7 7008
+PhyReg_VR128X 7009
+PhyReg_VR128 7010
+PhyReg_VR256X 7011
+PhyReg_VR256 7012
+PhyReg_VR512 7013
+PhyReg_VR512_0_15 7014
+PhyReg_TILE 7015
+VirtReg_GR8 7016
+VirtReg_GRH8 7017
+VirtReg_GR8_NOREX2 7018
+VirtReg_GR8_NOREX 7019
+VirtReg_GR8_ABCD_H 7020
+VirtReg_GR8_ABCD_L 7021
+VirtReg_GRH16 7022
+VirtReg_GR16 7023
+VirtReg_GR16_NOREX2 7024
+VirtReg_GR16_NOREX 7025
+VirtReg_VK1 7026
+VirtReg_VK16 7027
+VirtReg_VK2 7028
+VirtReg_VK4 7029
+VirtReg_VK8 7030
+VirtReg_VK16WM 7031
+VirtReg_VK1WM 7032
+VirtReg_VK2WM 7033
+VirtReg_VK4WM 7034
+VirtReg_VK8WM 7035
+VirtReg_SEGMENT_REG 7036
+VirtReg_GR16_ABCD 7037
+VirtReg_FPCCR 7038
+VirtReg_FR16X 7039
+VirtReg_FR16 7040
+VirtReg_VK16PAIR 7041
+VirtReg_VK1PAIR 7042
+VirtReg_VK2PAIR 7043
+VirtReg_VK4PAIR 7044
+VirtReg_VK8PAIR 7045
+VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7046
+VirtReg_LOW32_ADDR_ACCESS_RBP 7047
+VirtReg_LOW32_ADDR_ACCESS 7048
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7049
+VirtReg_FR32X 7050
+VirtReg_GR32 7051
+VirtReg_GR32_NOSP 7052
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7053
+VirtReg_DEBUG_REG 7054
+VirtReg_FR32 7055
+VirtReg_GR32_NOREX2 7056
+VirtReg_GR32_NOREX2_NOSP 7057
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7058
+VirtReg_GR32_NOREX 7059
+VirtReg_VK32 7060
+VirtReg_GR32_NOREX_NOSP 7061
+VirtReg_RFP32 7062
+VirtReg_VK32WM 7063
+VirtReg_GR32_ABCD 7064
+VirtReg_GR32_TC 7065
+VirtReg_GR32_ABCD_and_GR32_TC 7066
+VirtReg_GR32_AD 7067
+VirtReg_GR32_ArgRef 7068
+VirtReg_GR32_BPSP 7069
+VirtReg_GR32_BSI 7070
+VirtReg_GR32_CB 7071
+VirtReg_GR32_DC 7072
+VirtReg_GR32_DIBP 7073
+VirtReg_GR32_SIDI 7074
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7075
+VirtReg_CCR 7076
+VirtReg_DFCCR 7077
+VirtReg_GR32_ABCD_and_GR32_BSI 7078
+VirtReg_GR32_AD_and_GR32_ArgRef 7079
+VirtReg_GR32_ArgRef_and_GR32_CB 7080
+VirtReg_GR32_BPSP_and_GR32_DIBP 7081
+VirtReg_GR32_BPSP_and_GR32_TC 7082
+VirtReg_GR32_BSI_and_GR32_SIDI 7083
+VirtReg_GR32_DIBP_and_GR32_SIDI 7084
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7085
+VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7086
+VirtReg_RFP64 7087
+VirtReg_GR64 7088
+VirtReg_FR64X 7089
+VirtReg_GR64_with_sub_8bit 7090
+VirtReg_GR64_NOSP 7091
+VirtReg_GR64_NOREX2 7092
+VirtReg_CONTROL_REG 7093
+VirtReg_FR64 7094
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7095
+VirtReg_GR64_NOREX2_NOSP 7096
+VirtReg_GR64PLTSafe 7097
+VirtReg_GR64_TC 7098
+VirtReg_GR64_NOREX 7099
+VirtReg_GR64_TCW64 7100
+VirtReg_GR64_TC_with_sub_8bit 7101
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7102
+VirtReg_GR64_TCW64_with_sub_8bit 7103
+VirtReg_GR64_TC_and_GR64_TCW64 7104
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7105
+VirtReg_VK64 7106
+VirtReg_VR64 7107
+VirtReg_GR64PLTSafe_and_GR64_TC 7108
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7109
+VirtReg_GR64_NOREX_NOSP 7110
+VirtReg_GR64_NOREX_and_GR64_TC 7111
+VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7112
+VirtReg_VK64WM 7113
+VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7114
+VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7115
+VirtReg_GR64PLTSafe_and_GR64_TCW64 7116
+VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7117
+VirtReg_GR64_NOREX_and_GR64_TCW64 7118
+VirtReg_GR64_ABCD 7119
+VirtReg_GR64_with_sub_32bit_in_GR32_TC 7120
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7121
+VirtReg_GR64_AD 7122
+VirtReg_GR64_ArgRef 7123
+VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7124
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7125
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7126
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7127
+VirtReg_GR64_with_sub_32bit_in_GR32_CB 7128
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7129
+VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7130
+VirtReg_GR64_A 7131
+VirtReg_GR64_ArgRef_and_GR64_TC 7132
+VirtReg_GR64_and_LOW32_ADDR_ACCESS 7133
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7134
+VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7135
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7136
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7137
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7138
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7139
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7140
+VirtReg_RST 7141
+VirtReg_RFP80 7142
+VirtReg_RFP80_7 7143
+VirtReg_VR128X 7144
+VirtReg_VR128 7145
+VirtReg_VR256X 7146
+VirtReg_VR256 7147
+VirtReg_VR512 7148
+VirtReg_VR512_0_15 7149
+VirtReg_TILE 7150
diff --git a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
index ff87e7b6a1018..235a53dcc156e 100644
--- a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
+++ b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
@@ -1113,7 +1113,7 @@ TEST_F(InstrRefLDVTest, MLocDiamondSpills) {
// Create a stack location and ensure it's tracked.
SpillLoc SL = {getRegByName("RSP"), StackOffset::getFixed(-8)};
SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(SL);
- ASSERT_EQ(MTracker->getNumLocs(), 13u); // Tracks all possible stack locs.
+ ASSERT_EQ(MTracker->getNumLocs(), 11u); // Tracks all possible stack locs.
// Locations are: RSP, stack slots from 2^3 bits wide up to 2^9 for zmm regs,
// then slots for sub_8bit_hi and sub_16bit_hi ({8, 8} and {16, 16}).
// Finally, one for spilt fp80 registers.
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index a006888a2352c..44b76ae7e8487 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -1141,7 +1141,6 @@ OperandType RecognizableInstr::typeFromString(StringRef Str, bool hasREX_W,
.Case("vz64mem", TYPE_MVSIBZ)
.Case("BNDR", TYPE_BNDR)
.Case("TILE", TYPE_TMM)
- .Case("TILEPair", TYPE_TMM_PAIR)
.Default(TYPE_NONE);
// clang-format on
>From 4e86b458bae41f36fa05820f8f5e22e6d83f70b1 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 29 Oct 2025 20:29:03 +0100
Subject: [PATCH 2/6] Delete unused variable
---
llvm/lib/TargetParser/X86TargetParser.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index adbcc610f669a..37e8ad986aa55 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -615,7 +615,6 @@ constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE;
-constexpr FeatureBitset ImpliedFeaturesAMX_TRANSPOSE = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesAMX_MOVRS = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesAMX_AVX512 =
FeatureAMX_TILE | FeatureAVX10_2;
>From ef75547b11ae1a5f134c62ce20b17253d56ad79c Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 29 Oct 2025 20:40:55 +0100
Subject: [PATCH 3/6] Formatting
---
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 4 +++-
llvm/lib/Target/X86/X86ISelLowering.cpp | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index c7e1d3e9db2c8..1676acd7aaa60 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -674,7 +674,9 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break;
case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
- case X86::PTDPFP16PSV: Opc = X86::TDPFP16PS; break;
+ case X86::PTDPFP16PSV:
+ Opc = X86::TDPFP16PS;
+ break;
case X86::PTMMULTF32PSV:
Opc = X86::TMMULTF32PS;
break;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 787f05ebf99d7..a8850b358f7e6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38083,7 +38083,9 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::PTDPBF8PS: Opc = X86::TDPBF8PS; break;
case X86::PTDPBHF8PS: Opc = X86::TDPBHF8PS; break;
case X86::PTDPHBF8PS: Opc = X86::TDPHBF8PS; break;
- case X86::PTDPHF8PS: Opc = X86::TDPHF8PS; break;
+ case X86::PTDPHF8PS:
+ Opc = X86::TDPHF8PS;
+ break;
case X86::PTMMULTF32PS:
Opc = X86::TMMULTF32PS;
break;
>From 6510899d8742476b68fb37310671d4c81eadddb1 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Thu, 30 Oct 2025 11:03:16 +0100
Subject: [PATCH 4/6] Remove unused variable
---
clang/lib/Basic/Targets/X86.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index be3a473174370..e7da2622e78b5 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -160,7 +160,6 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasAMXCOMPLEX = false;
bool HasAMXFP8 = false;
bool HasAMXMOVRS = false;
- bool HasAMXTRANSPOSE = false;
bool HasAMXAVX512 = false;
bool HasAMXTF32 = false;
bool HasSERIALIZE = false;
>From 88d58b2d6c668b20048f631aae93df5fc45313e8 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Thu, 30 Oct 2025 11:36:08 +0100
Subject: [PATCH 5/6] Reviewer suggestions
---
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 27 ++++++--------------
llvm/lib/Target/X86/X86FastPreTileConfig.cpp | 2 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 18 +++++--------
llvm/lib/Target/X86/X86InstrInfo.cpp | 2 +-
llvm/lib/Target/X86/X86RegisterInfo.td | 4 +--
5 files changed, 18 insertions(+), 35 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index 1676acd7aaa60..cb33b739adf93 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -667,6 +667,7 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MI.removeOperand(i);
unsigned Opc;
switch (Opcode) {
+ // clang-format off
case X86::PTCMMIMFP16PSV: Opc = X86::TCMMIMFP16PS; break;
case X86::PTCMMRLFP16PSV: Opc = X86::TCMMRLFP16PS; break;
case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
@@ -674,25 +675,13 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break;
case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
- case X86::PTDPFP16PSV:
- Opc = X86::TDPFP16PS;
- break;
- case X86::PTMMULTF32PSV:
- Opc = X86::TMMULTF32PS;
- break;
- case X86::PTDPBF8PSV:
- Opc = X86::TDPBF8PS;
- break;
- case X86::PTDPBHF8PSV:
- Opc = X86::TDPBHF8PS;
- break;
- case X86::PTDPHBF8PSV:
- Opc = X86::TDPHBF8PS;
- break;
- case X86::PTDPHF8PSV:
- Opc = X86::TDPHF8PS;
- break;
-
+ case X86::PTDPFP16PSV: Opc = X86::TDPFP16PS; break;
+ case X86::PTMMULTF32PSV: Opc = X86::TMMULTF32PS; break;
+ case X86::PTDPBF8PSV: Opc = X86::TDPBF8PS; break;
+ case X86::PTDPBHF8PSV: Opc = X86::TDPBHF8PS; break;
+ case X86::PTDPHBF8PSV: Opc = X86::TDPHBF8PS; break;
+ case X86::PTDPHF8PSV: Opc = X86::TDPHF8PS; break;
+ // clang-format on
default:
llvm_unreachable("Unexpected Opcode");
}
diff --git a/llvm/lib/Target/X86/X86FastPreTileConfig.cpp b/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
index 443d016519504..40a4cecb08b93 100644
--- a/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
@@ -269,7 +269,7 @@ void X86FastPreTileConfig::reload(MachineBasicBlock::iterator UseMI,
static unsigned getTileDefNum(MachineRegisterInfo *MRI, Register Reg) {
if (Reg.isVirtual() &&
- MRI->getRegClass(Reg)->getID() == X86::TILERegClassID) {
+ (MRI->getRegClass(Reg)->getID() == X86::TILERegClassID)) {
return 1;
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a8850b358f7e6..6d97cc6d0f700 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38068,27 +38068,21 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
unsigned Opc;
switch (MI.getOpcode()) {
default: llvm_unreachable("illegal opcode!");
+ // clang-format off
case X86::PTDPBSSD: Opc = X86::TDPBSSD; break;
case X86::PTDPBSUD: Opc = X86::TDPBSUD; break;
case X86::PTDPBUSD: Opc = X86::TDPBUSD; break;
case X86::PTDPBUUD: Opc = X86::TDPBUUD; break;
case X86::PTDPBF16PS: Opc = X86::TDPBF16PS; break;
case X86::PTDPFP16PS: Opc = X86::TDPFP16PS; break;
- case X86::PTCMMIMFP16PS:
- Opc = X86::TCMMIMFP16PS;
- break;
- case X86::PTCMMRLFP16PS:
- Opc = X86::TCMMRLFP16PS;
- break;
+ case X86::PTCMMIMFP16PS: Opc = X86::TCMMIMFP16PS; break;
+ case X86::PTCMMRLFP16PS: Opc = X86::TCMMRLFP16PS; break;
case X86::PTDPBF8PS: Opc = X86::TDPBF8PS; break;
case X86::PTDPBHF8PS: Opc = X86::TDPBHF8PS; break;
case X86::PTDPHBF8PS: Opc = X86::TDPHBF8PS; break;
- case X86::PTDPHF8PS:
- Opc = X86::TDPHF8PS;
- break;
- case X86::PTMMULTF32PS:
- Opc = X86::TMMULTF32PS;
- break;
+ case X86::PTDPHF8PS: Opc = X86::TDPHF8PS; break;
+ case X86::PTMMULTF32PS: Opc = X86::TMMULTF32PS; break;
+ // clang-format on
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, MIMD, TII->get(Opc));
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index e97b57a49cefe..6b2a7a4ec3583 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4736,8 +4736,8 @@ static bool isAMXOpcode(unsigned Opc) {
return false;
case X86::TILELOADD:
case X86::TILESTORED:
- case X86::TILESTORED_EVEX:
case X86::TILELOADD_EVEX:
+ case X86::TILESTORED_EVEX:
return true;
}
}
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 1806561e9d7cf..692e42ae5e752 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -29,7 +29,7 @@ let Namespace = "X86" in {
def sub_xmm : SubRegIndex<128>;
def sub_ymm : SubRegIndex<256>;
def sub_mask_0 : SubRegIndex<-1>;
- def sub_mask_1 : SubRegIndex<-1, -1>;
+ def sub_mask_1 : SubRegIndex<-1, -1>;
}
//===----------------------------------------------------------------------===//
@@ -429,7 +429,7 @@ def TMM3: X86Reg<"tmm3", 3>;
def TMM4: X86Reg<"tmm4", 4>;
def TMM5: X86Reg<"tmm5", 5>;
def TMM6: X86Reg<"tmm6", 6>;
-def TMM7 : X86Reg<"tmm7", 7>;
+def TMM7: X86Reg<"tmm7", 7>;
}
// Floating point stack registers. These don't map one-to-one to the FP
>From cbede571ba2e21922b9d329247aadd9489a6b085 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Thu, 30 Oct 2025 11:58:59 +0100
Subject: [PATCH 6/6] Formatting
---
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 2 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index cb33b739adf93..e3c44c048f7bf 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -667,7 +667,7 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MI.removeOperand(i);
unsigned Opc;
switch (Opcode) {
- // clang-format off
+ // clang-format off
case X86::PTCMMIMFP16PSV: Opc = X86::TCMMIMFP16PS; break;
case X86::PTCMMRLFP16PSV: Opc = X86::TCMMRLFP16PS; break;
case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6d97cc6d0f700..20c24e8f75fbe 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38068,7 +38068,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
unsigned Opc;
switch (MI.getOpcode()) {
default: llvm_unreachable("illegal opcode!");
- // clang-format off
+ // clang-format off
case X86::PTDPBSSD: Opc = X86::TDPBSSD; break;
case X86::PTDPBSUD: Opc = X86::TDPBSUD; break;
case X86::PTDPBUSD: Opc = X86::TDPBUSD; break;
@@ -38082,7 +38082,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::PTDPHBF8PS: Opc = X86::TDPHBF8PS; break;
case X86::PTDPHF8PS: Opc = X86::TDPHF8PS; break;
case X86::PTMMULTF32PS: Opc = X86::TMMULTF32PS; break;
- // clang-format on
+ // clang-format on
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, MIMD, TII->get(Opc));
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