[clang] [llvm] [HLSL] Implement the f16tof32() intrinsic (PR #165860)

[Steven Perron via cfe-commits]

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@@ -3780,6 +3751,89 @@ bool SPIRVInstructionSelector::selectResourceNonUniformIndex(
   return true;
 }
 
+bool SPIRVInstructionSelector::selectF16ToF32(Register ResVReg,
+                                              const SPIRVType *ResType,
+                                              MachineInstr &I) const {
+  assert(I.getNumOperands() == 3);
+  assert(I.getOperand(0).isReg());
+  assert(I.getOperand(2).isReg());
+  Register SrcReg = I.getOperand(2).getReg();
+  const SPIRVType *SrcRegType = GR.getSPIRVTypeForVReg(SrcReg);
+  LLT SrcType = MRI->getType(SrcReg);
+  SPIRVType *SrcEltType = GR.getScalarOrVectorComponentType(SrcRegType);
+  SPIRVType *ResEltType = GR.getScalarOrVectorComponentType(ResType);
+  const TargetRegisterClass *SrcRegClass = GR.getRegClass(SrcEltType);
+  const TargetRegisterClass *ResRegClass = GR.getRegClass(ResEltType);
+  MachineIRBuilder MIRBuilder(I);
+  const SPIRVType *Vec2ResType =
+      GR.getOrCreateSPIRVVectorType(ResEltType, 2, MIRBuilder, false);
+  const TargetRegisterClass *Vec2RegClass = GR.getRegClass(Vec2ResType);
+
+  bool Result = true;
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s-perron wrote:

You might want to explain why you expand it this way. I believe DXC did it this way to avoid using any 16-bit types. You might be able to generate better code if we are able to use 16-bit types. If that is what user want, then they can write different HLSL.

https://github.com/llvm/llvm-project/pull/165860