[clang] [clang-format] Recognize Verilog export and import (PR #165595)

[Björn Schäpers via cfe-commits]

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@@ -4555,6 +4559,26 @@ void UnwrappedLineParser::parseVerilogCaseLabel() {
   Line->Level = OrigLevel;
 }
 
+bool UnwrappedLineParser::tryToParseVerilogExtern() {
+  assert(
+      FormatTok->isOneOf(tok::kw_extern, tok::kw_export, Keywords.kw_import));
+  nextToken();
+  // "DPI-C"
+  if (FormatTok->is(tok::string_literal))
+    nextToken();
+  if (FormatTok->isOneOf(Keywords.kw_context, Keywords.kw_pure))
+    nextToken();
+  if (Keywords.isVerilogIdentifier(*FormatTok))
+    nextToken();
+  if (FormatTok->is(tok::equal))
+    nextToken();
+  if (Keywords.isVerilogHierarchy(*FormatTok)) {
+    parseVerilogHierarchyHeader();
+    return true;
+  }
+  return false;
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HazardyKnusperkeks wrote:

I assume when we land here we have incomplete or invalid code and don't really care about the remaining formatting?

https://github.com/llvm/llvm-project/pull/165595