[clang] [Headers][X86] Allow SLLDQ/SRLDQ byte shift intrinsics to be used in constexpr (PR #164166)

[Simon Pilgrim via cfe-commits]

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@@ -4149,6 +4181,42 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
   case X86::BI__builtin_ia32_vec_set_v4di:
     return interp__builtin_vec_set(S, OpPC, Call, BuiltinID);
 
+  case X86::BI__builtin_ia32_pslldqi128_byteshift:
+  case X86::BI__builtin_ia32_pslldqi256_byteshift:
+    return interp__builtin_x86_byteshift(
+        S, OpPC, Call, BuiltinID,
+        [](const Pointer &Src, PrimType ElemT, unsigned Lane, unsigned I,
+           unsigned Shift) {
+          APInt v;
+          INT_TYPE_SWITCH_NO_BOOL(ElemT, {
+            if (I < Shift) {
+              v = APInt(sizeof(T) * 8, 0);
+            } else {
+              v = APInt(sizeof(T) * 8,
+                        static_cast<uint64_t>(Src.elem<T>(Lane + I - Shift)));
+            }
+          });
+          return v;
+        });
+
+  case X86::BI__builtin_ia32_psrldqi128_byteshift:
+  case X86::BI__builtin_ia32_psrldqi256_byteshift:
+    return interp__builtin_x86_byteshift(
+        S, OpPC, Call, BuiltinID,
+        [](const Pointer &Src, PrimType ElemT, unsigned Lane, unsigned I,
+           unsigned Shift) {
+          APInt v;
+          INT_TYPE_SWITCH_NO_BOOL(ElemT, {
+            if (I + Shift < 16) {
+              v = APInt(sizeof(T) * 8,
+                        static_cast<uint64_t>(Src.elem<T>(Lane + I + Shift)));
----------------
RKSimon wrote:

You're hardcoding the lane width to 16 but using "sizeof(T) * 8" even though it will equal 8?

https://github.com/llvm/llvm-project/pull/164166