[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)
via cfe-commits
cfe-commits at lists.llvm.org
Thu Oct 16 16:50:09 PDT 2025
https://github.com/slachowsky updated https://github.com/llvm/llvm-project/pull/163672
>From b6180fd2922035d03714378fa96d03c97ebc6a89 Mon Sep 17 00:00:00 2001
From: Stephan Lachowsky <slachowsky at apple.com>
Date: Tue, 14 Oct 2025 11:02:34 -0700
Subject: [PATCH 1/3] [RISCV][LLVM] Enable atomics for 'Zalrsc'
The 'A' atomics extension is composed of two subextensions, 'Zaamo' which has
atomic memory operation instructions, and 'Zalrsc' which has load-reserve /
store-conditional instructions.
For machines where 'Zalrsc' is present, but 'Zaamo' is not, implement and enable
atomics memory operations through pseudo expansion. Updates the predication
and lowering control to be more precise about which 'Zaamo'/'Zalrsc' feature
was truly requisite.
There will be no functional change to subtargets supporting 'A', while allowing
'Zalrsc' only subtargets to utilize atomics at an increased code footprint.
---
.../RISCV/RISCVExpandAtomicPseudoInsts.cpp | 251 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 +-
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 76 +-
llvm/test/CodeGen/RISCV/atomic-fence.ll | 4 +
llvm/test/CodeGen/RISCV/atomic-load-store.ll | 406 +
llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll | 102 +
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 9004 +++++++++++++++++
llvm/test/CodeGen/RISCV/atomic-signext.ll | 2644 +++++
9 files changed, 12456 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index 5dd4bf415a23c..31b9bf9c15b69 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -109,12 +109,72 @@ bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB,
// expanded instructions for each pseudo is correct in the Size field of the
// tablegen definition for the pseudo.
switch (MBBI->getOpcode()) {
+ case RISCV::PseudoAtomicSwap32:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicSwap64:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadAdd32:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Add, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadAdd64:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Add, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadSub32:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Sub, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadSub64:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Sub, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadAnd32:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::And, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadAnd64:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::And, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadOr32:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Or, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadOr64:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Or, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadXor32:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xor, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadXor64:
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xor, false, 64,
+ NextMBBI);
case RISCV::PseudoAtomicLoadNand32:
return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 32,
NextMBBI);
case RISCV::PseudoAtomicLoadNand64:
return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 64,
NextMBBI);
+ case RISCV::PseudoAtomicLoadMin32:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Min, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadMin64:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Min, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadMax32:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Max, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadMax64:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Max, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadUMin32:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMin, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadUMin64:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMin, false, 64,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadUMax32:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMax, false, 32,
+ NextMBBI);
+ case RISCV::PseudoAtomicLoadUMax64:
+ return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMax, false, 64,
+ NextMBBI);
case RISCV::PseudoMaskedAtomicSwap32:
return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, true, 32,
NextMBBI);
@@ -277,6 +337,36 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
switch (BinOp) {
default:
llvm_unreachable("Unexpected AtomicRMW BinOp");
+ case AtomicRMWInst::Xchg:
+ BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
+ .addReg(IncrReg)
+ .addImm(0);
+ break;
+ case AtomicRMWInst::Add:
+ BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
+ .addReg(DestReg)
+ .addReg(IncrReg);
+ break;
+ case AtomicRMWInst::Sub:
+ BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
+ .addReg(DestReg)
+ .addReg(IncrReg);
+ break;
+ case AtomicRMWInst::And:
+ BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
+ .addReg(DestReg)
+ .addReg(IncrReg);
+ break;
+ case AtomicRMWInst::Or:
+ BuildMI(LoopMBB, DL, TII->get(RISCV::OR), ScratchReg)
+ .addReg(DestReg)
+ .addReg(IncrReg);
+ break;
+ case AtomicRMWInst::Xor:
+ BuildMI(LoopMBB, DL, TII->get(RISCV::XOR), ScratchReg)
+ .addReg(DestReg)
+ .addReg(IncrReg);
+ break;
case AtomicRMWInst::Nand:
BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
.addReg(DestReg)
@@ -433,38 +523,105 @@ static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
.addReg(ShamtReg);
}
-bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
- MachineBasicBlock::iterator &NextMBBI) {
- assert(IsMasked == true &&
- "Should only need to expand masked atomic max/min");
- assert(Width == 32 && "Should never need to expand masked 64-bit operations");
+static void insertZext(const RISCVInstrInfo *TII, DebugLoc DL,
+ MachineBasicBlock *MBB, Register ValReg,
+ Register SrcReg, int64_t Shamt) {
+ BuildMI(MBB, DL, TII->get(RISCV::SLLI), ValReg)
+ .addReg(SrcReg)
+ .addImm(Shamt);
+ BuildMI(MBB, DL, TII->get(RISCV::SRLI), ValReg)
+ .addReg(ValReg)
+ .addImm(Shamt);
+}
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
- MachineFunction *MF = MBB.getParent();
- auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
- auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
- auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
- auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
+ DebugLoc DL, MachineBasicBlock *ThisMBB,
+ MachineBasicBlock *LoopHeadMBB,
+ MachineBasicBlock *LoopIfBodyMBB,
+ MachineBasicBlock *LoopTailMBB,
+ MachineBasicBlock *DoneMBB,
+ AtomicRMWInst::BinOp BinOp, int Width,
+ const RISCVSubtarget *STI) {
+ Register DestReg = MI.getOperand(0).getReg();
+ Register ScratchReg = MI.getOperand(1).getReg();
+ Register AddrReg = MI.getOperand(2).getReg();
+ Register IncrReg = MI.getOperand(3).getReg();
+ bool IsUnsigned = BinOp == AtomicRMWInst::UMin ||
+ BinOp == AtomicRMWInst::UMax;
+ bool Zext = IsUnsigned && STI->is64Bit() && Width == 32;
+ AtomicOrdering Ordering =
+ static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
- // Insert new MBBs.
- MF->insert(++MBB.getIterator(), LoopHeadMBB);
- MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
- MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
- MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
+ // .loophead:
+ // lr.[w|d] dest, (addr)
+ // mv scratch, dest
+ // ifnochangeneeded scratch, incr, .looptail
+ BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg)
+ .addReg(AddrReg);
+ if (Zext)
+ insertZext(TII, DL, LoopHeadMBB, ScratchReg, DestReg, 32);
+ else
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
+ .addReg(DestReg)
+ .addImm(0);
+ switch (BinOp) {
+ default:
+ llvm_unreachable("Unexpected AtomicRMW BinOp");
+ case AtomicRMWInst::Max: {
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
+ .addReg(ScratchReg)
+ .addReg(IncrReg)
+ .addMBB(LoopTailMBB);
+ break;
+ }
+ case AtomicRMWInst::Min: {
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
+ .addReg(IncrReg)
+ .addReg(ScratchReg)
+ .addMBB(LoopTailMBB);
+ break;
+ }
+ case AtomicRMWInst::UMax:
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
+ .addReg(ScratchReg)
+ .addReg(IncrReg)
+ .addMBB(LoopTailMBB);
+ break;
+ case AtomicRMWInst::UMin:
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
+ .addReg(IncrReg)
+ .addReg(ScratchReg)
+ .addMBB(LoopTailMBB);
+ break;
+ }
- // Set up successors and transfer remaining instructions to DoneMBB.
- LoopHeadMBB->addSuccessor(LoopIfBodyMBB);
- LoopHeadMBB->addSuccessor(LoopTailMBB);
- LoopIfBodyMBB->addSuccessor(LoopTailMBB);
- LoopTailMBB->addSuccessor(LoopHeadMBB);
- LoopTailMBB->addSuccessor(DoneMBB);
- DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
- DoneMBB->transferSuccessors(&MBB);
- MBB.addSuccessor(LoopHeadMBB);
+ // .loopifbody:
+ // mv scratch, incr
+ BuildMI(LoopIfBodyMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
+ .addReg(IncrReg)
+ .addImm(0);
+ // .looptail:
+ // sc.[w|d] scratch, scratch, (addr)
+ // bnez scratch, loop
+ BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg)
+ .addReg(ScratchReg)
+ .addReg(AddrReg);
+ BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
+ .addReg(ScratchReg)
+ .addReg(RISCV::X0)
+ .addMBB(LoopHeadMBB);
+}
+
+static void doMaskedAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
+ DebugLoc DL, MachineBasicBlock *ThisMBB,
+ MachineBasicBlock *LoopHeadMBB,
+ MachineBasicBlock *LoopIfBodyMBB,
+ MachineBasicBlock *LoopTailMBB,
+ MachineBasicBlock *DoneMBB,
+ AtomicRMWInst::BinOp BinOp, int Width,
+ const RISCVSubtarget *STI) {
+ assert(Width == 32 && "Should never need to expand masked 64-bit operations");
Register DestReg = MI.getOperand(0).getReg();
Register Scratch1Reg = MI.getOperand(1).getReg();
Register Scratch2Reg = MI.getOperand(2).getReg();
@@ -541,6 +698,44 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
.addReg(Scratch1Reg)
.addReg(RISCV::X0)
.addMBB(LoopHeadMBB);
+}
+
+bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
+ MachineBasicBlock::iterator &NextMBBI) {
+
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+ MachineFunction *MF = MBB.getParent();
+ auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+ auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+ auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+ auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+
+ // Insert new MBBs.
+ MF->insert(++MBB.getIterator(), LoopHeadMBB);
+ MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
+ MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
+ MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
+
+ // Set up successors and transfer remaining instructions to DoneMBB.
+ LoopHeadMBB->addSuccessor(LoopIfBodyMBB);
+ LoopHeadMBB->addSuccessor(LoopTailMBB);
+ LoopIfBodyMBB->addSuccessor(LoopTailMBB);
+ LoopTailMBB->addSuccessor(LoopHeadMBB);
+ LoopTailMBB->addSuccessor(DoneMBB);
+ DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
+ DoneMBB->transferSuccessors(&MBB);
+ MBB.addSuccessor(LoopHeadMBB);
+
+ if (!IsMasked)
+ doAtomicMinMaxOpExpansion(TII, MI, DL, &MBB, LoopHeadMBB, LoopIfBodyMBB,
+ LoopTailMBB, DoneMBB, BinOp, Width, STI);
+ else
+ doMaskedAtomicMinMaxOpExpansion(TII, MI, DL, &MBB, LoopHeadMBB,
+ LoopIfBodyMBB, LoopTailMBB, DoneMBB, BinOp,
+ Width, STI);
NextMBBI = MBB.end();
MI.eraseFromParent();
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 5ceb477069188..f5c12998a8baf 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -218,6 +218,7 @@ def HasStdExtZaamo
: Predicate<"Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtZaamo),
"'Zaamo' (Atomic Memory Operations)">;
+def NoStdExtZaamo : Predicate<"!Subtarget->hasStdExtZaamo()">;
def FeatureStdExtZalrsc
: RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">;
@@ -1861,7 +1862,7 @@ def FeatureForcedAtomics : SubtargetFeature<
"forced-atomics", "HasForcedAtomics", "true",
"Assume that lock-free native-width atomics are available">;
def HasAtomicLdSt
- : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
+ : Predicate<"Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">;
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7123a2d706787..1e1b4b785059f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -688,7 +688,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
else if (Subtarget.hasStdExtZicbop())
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
- if (Subtarget.hasStdExtA()) {
+ if (Subtarget.hasStdExtZalrsc()) {
setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
if (Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas())
setMinCmpXchgSizeInBits(8);
@@ -1558,7 +1558,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
}
- if (Subtarget.hasStdExtA())
+ if (Subtarget.hasStdExtZaamo())
setOperationAction(ISD::ATOMIC_LOAD_SUB, XLenVT, Expand);
if (Subtarget.hasForcedAtomics()) {
@@ -21876,7 +21876,7 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
// result is then sign extended to XLEN. With +A, the minimum width is
// 32 for both 64 and 32.
assert(getMinCmpXchgSizeInBits() == 32);
- assert(Subtarget.hasStdExtA());
+ assert(Subtarget.hasStdExtZalrsc());
return Op.getValueSizeInBits() - 31;
}
break;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 571d72f904ca7..8b88b2ab89941 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -308,7 +308,67 @@ class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
timm:$ordering)>;
-let Predicates = [HasStdExtA] in {
+let Predicates = [HasStdExtZalrsc, NoStdExtZaamo] in {
+
+let Size = 16 in {
+def PseudoAtomicSwap32 : PseudoAMO;
+def PseudoAtomicLoadAdd32 : PseudoAMO;
+def PseudoAtomicLoadSub32 : PseudoAMO;
+def PseudoAtomicLoadAnd32 : PseudoAMO;
+def PseudoAtomicLoadOr32 : PseudoAMO;
+def PseudoAtomicLoadXor32 : PseudoAMO;
+} // Size = 16
+let Size = 24 in {
+def PseudoAtomicLoadMax32 : PseudoAMO;
+def PseudoAtomicLoadMin32 : PseudoAMO;
+} // Size = 24
+let Size = 28 in {
+def PseudoAtomicLoadUMax32 : PseudoAMO;
+def PseudoAtomicLoadUMin32 : PseudoAMO;
+} // Size = 28
+
+defm : PseudoAMOPat<"atomic_swap_i32", PseudoAtomicSwap32>;
+defm : PseudoAMOPat<"atomic_load_add_i32", PseudoAtomicLoadAdd32>;
+defm : PseudoAMOPat<"atomic_load_sub_i32", PseudoAtomicLoadSub32>;
+defm : PseudoAMOPat<"atomic_load_and_i32", PseudoAtomicLoadAnd32>;
+defm : PseudoAMOPat<"atomic_load_or_i32", PseudoAtomicLoadOr32>;
+defm : PseudoAMOPat<"atomic_load_xor_i32", PseudoAtomicLoadXor32>;
+defm : PseudoAMOPat<"atomic_load_max_i32", PseudoAtomicLoadMax32>;
+defm : PseudoAMOPat<"atomic_load_min_i32", PseudoAtomicLoadMin32>;
+defm : PseudoAMOPat<"atomic_load_umax_i32", PseudoAtomicLoadUMax32>;
+defm : PseudoAMOPat<"atomic_load_umin_i32", PseudoAtomicLoadUMin32>;
+} // Predicates = [HasStdExtZalrsc, NoStdExtZaamo]
+
+let Predicates = [HasStdExtZalrsc, NoStdExtZaamo, IsRV64] in {
+
+let Size = 16 in {
+def PseudoAtomicSwap64 : PseudoAMO;
+def PseudoAtomicLoadAdd64 : PseudoAMO;
+def PseudoAtomicLoadSub64 : PseudoAMO;
+def PseudoAtomicLoadAnd64 : PseudoAMO;
+def PseudoAtomicLoadOr64 : PseudoAMO;
+def PseudoAtomicLoadXor64 : PseudoAMO;
+} // Size = 16
+let Size = 24 in {
+def PseudoAtomicLoadMax64 : PseudoAMO;
+def PseudoAtomicLoadMin64 : PseudoAMO;
+def PseudoAtomicLoadUMax64 : PseudoAMO;
+def PseudoAtomicLoadUMin64 : PseudoAMO;
+} // Size = 24
+
+defm : PseudoAMOPat<"atomic_swap_i64", PseudoAtomicSwap64, i64>;
+defm : PseudoAMOPat<"atomic_load_add_i64", PseudoAtomicLoadAdd64, i64>;
+defm : PseudoAMOPat<"atomic_load_sub_i64", PseudoAtomicLoadSub64, i64>;
+defm : PseudoAMOPat<"atomic_load_and_i64", PseudoAtomicLoadAnd64, i64>;
+defm : PseudoAMOPat<"atomic_load_or_i64", PseudoAtomicLoadOr64, i64>;
+defm : PseudoAMOPat<"atomic_load_xor_i64", PseudoAtomicLoadXor64, i64>;
+defm : PseudoAMOPat<"atomic_load_max_i64", PseudoAtomicLoadMax64, i64>;
+defm : PseudoAMOPat<"atomic_load_min_i64", PseudoAtomicLoadMin64, i64>;
+defm : PseudoAMOPat<"atomic_load_umax_i64", PseudoAtomicLoadUMax64, i64>;
+defm : PseudoAMOPat<"atomic_load_umin_i64", PseudoAtomicLoadUMin64, i64>;
+} // Predicates = [HasStdExtZalrsc, NoStdExtZaamo, IsRV64]
+
+let Predicates = [HasStdExtZalrsc] in {
let Size = 20 in
def PseudoAtomicLoadNand32 : PseudoAMO;
@@ -347,14 +407,14 @@ def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax,
PseudoMaskedAtomicLoadUMax32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin,
PseudoMaskedAtomicLoadUMin32>;
-} // Predicates = [HasStdExtA]
+} // Predicates = [HasStdExtZalrsc]
-let Predicates = [HasStdExtA, IsRV64] in {
+let Predicates = [HasStdExtZalrsc, IsRV64] in {
let Size = 20 in
def PseudoAtomicLoadNand64 : PseudoAMO;
defm : PseudoAMOPat<"atomic_load_nand_i64", PseudoAtomicLoadNand64, i64>;
-} // Predicates = [HasStdExtA, IsRV64]
+} // Predicates = [HasStdExtZalrsc, IsRV64]
/// Compare and exchange
@@ -385,17 +445,17 @@ multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst,
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
}
-let Predicates = [HasStdExtA, NoStdExtZacas] in {
+let Predicates = [HasStdExtZalrsc, NoStdExtZacas] in {
def PseudoCmpXchg32 : PseudoCmpXchg;
defm : PseudoCmpXchgPat<"atomic_cmp_swap_i32", PseudoCmpXchg32>;
}
-let Predicates = [HasStdExtA, NoStdExtZacas, IsRV64] in {
+let Predicates = [HasStdExtZalrsc, NoStdExtZacas, IsRV64] in {
def PseudoCmpXchg64 : PseudoCmpXchg;
defm : PseudoCmpXchgPat<"atomic_cmp_swap_i64", PseudoCmpXchg64, i64>;
}
-let Predicates = [HasStdExtA] in {
+let Predicates = [HasStdExtZalrsc] in {
def PseudoMaskedCmpXchg32
: Pseudo<(outs GPR:$res, GPR:$scratch),
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
@@ -412,4 +472,4 @@ def : Pat<(XLenVT (int_riscv_masked_cmpxchg
(XLenVT GPR:$mask), (XLenVT timm:$ordering))),
(PseudoMaskedCmpXchg32
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
-} // Predicates = [HasStdExtA]
+} // Predicates = [HasStdExtZalrsc]
diff --git a/llvm/test/CodeGen/RISCV/atomic-fence.ll b/llvm/test/CodeGen/RISCV/atomic-fence.ll
index 7103345ce7bc2..77148f64a3166 100644
--- a/llvm/test/CodeGen/RISCV/atomic-fence.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-fence.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,TSO %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \
diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
index 7e3abc753333b..c6234dedcef36 100644
--- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I-ZALRSC %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I-ZALRSC %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
@@ -44,6 +48,11 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
@@ -59,6 +68,11 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i8_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
@@ -78,6 +92,11 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
@@ -93,6 +112,11 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
@@ -112,6 +136,12 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i8_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lb a0, 0(a0)
@@ -133,6 +163,12 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i8_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lb a0, 0(a0)
@@ -200,6 +236,13 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i8_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
@@ -223,6 +266,13 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i8_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -286,6 +336,11 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
@@ -301,6 +356,11 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i16_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0)
@@ -320,6 +380,11 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
@@ -335,6 +400,11 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0)
@@ -354,6 +424,12 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i16_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lh a0, 0(a0)
@@ -375,6 +451,12 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i16_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lh a0, 0(a0)
@@ -442,6 +524,13 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i16_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
@@ -465,6 +554,13 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i16_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -528,6 +624,11 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
@@ -543,6 +644,11 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i32_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0)
@@ -562,6 +668,11 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
@@ -577,6 +688,11 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0)
@@ -596,6 +712,12 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lw a0, 0(a0)
@@ -617,6 +739,12 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lw a0, 0(a0)
@@ -684,6 +812,13 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
@@ -707,6 +842,13 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -770,6 +912,16 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 0
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -790,6 +942,11 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i64_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0)
@@ -809,6 +966,16 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 0
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -829,6 +996,11 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0)
@@ -848,6 +1020,16 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 2
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -868,6 +1050,12 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: ld a0, 0(a0)
@@ -914,6 +1102,16 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 5
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -934,6 +1132,13 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -979,6 +1184,11 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0)
@@ -994,6 +1204,11 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i8_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0)
@@ -1013,6 +1228,11 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0)
@@ -1028,6 +1248,11 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0)
@@ -1047,6 +1272,12 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i8_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1068,6 +1299,12 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i8_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1135,6 +1372,13 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i8_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1157,6 +1401,13 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i8_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1219,6 +1470,11 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0)
@@ -1234,6 +1490,11 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i16_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0)
@@ -1253,6 +1514,11 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0)
@@ -1268,6 +1534,11 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0)
@@ -1287,6 +1558,12 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i16_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1308,6 +1585,12 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i16_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1375,6 +1658,13 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i16_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1397,6 +1687,13 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i16_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1459,6 +1756,11 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0)
@@ -1474,6 +1776,11 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i32_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0)
@@ -1493,6 +1800,11 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0)
@@ -1508,6 +1820,11 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0)
@@ -1527,6 +1844,12 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1548,6 +1871,12 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1615,6 +1944,13 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1637,6 +1973,13 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1699,6 +2042,16 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1719,6 +2072,11 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i64_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0)
@@ -1738,6 +2096,16 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1758,6 +2126,11 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0)
@@ -1777,6 +2150,16 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1797,6 +2180,12 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1843,6 +2232,16 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1863,6 +2262,13 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll b/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
index 4dafd6a08d973..d5238ab941a14 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
@@ -3,10 +3,14 @@
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s
define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_constant:
@@ -26,6 +30,18 @@ define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind {
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_constant:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a1, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB0_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a1
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i32_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -42,6 +58,18 @@ define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind {
; RV64IA-NEXT: li a1, -1
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_constant:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB0_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw sub ptr %a, i32 1 seq_cst
ret i32 %1
}
@@ -71,6 +99,18 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_constant:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 1
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: li a2, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i64_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -87,6 +127,18 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind {
; RV64IA-NEXT: li a1, -1
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_constant:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB1_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw sub ptr %a, i64 1 seq_cst
ret i64 %1
}
@@ -109,6 +161,18 @@ define i32 @atomicrmw_sub_i32_neg(ptr %a, i32 %x, i32 %y) nounwind {
; RV32IA-NEXT: amoadd.w.aqrl a0, a2, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_neg:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sub a2, a1, a2
+; RV32I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a1, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB2_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a1
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i32_neg:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -125,6 +189,18 @@ define i32 @atomicrmw_sub_i32_neg(ptr %a, i32 %x, i32 %y) nounwind {
; RV64IA-NEXT: sub a2, a2, a1
; RV64IA-NEXT: amoadd.w.aqrl a0, a2, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_neg:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: subw a2, a1, a2
+; RV64I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB2_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
%b = sub i32 %x, %y
%1 = atomicrmw sub ptr %a, i32 %b seq_cst
ret i32 %1
@@ -159,6 +235,20 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_neg:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sltu a5, a1, a3
+; RV32I-ZALRSC-NEXT: sub a2, a2, a4
+; RV32I-ZALRSC-NEXT: sub a2, a2, a5
+; RV32I-ZALRSC-NEXT: sub a1, a1, a3
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i64_neg:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -175,6 +265,18 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind {
; RV64IA-NEXT: sub a2, a2, a1
; RV64IA-NEXT: amoadd.d.aqrl a0, a2, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_neg:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sub a2, a1, a2
+; RV64I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB3_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
%b = sub i64 %x, %y
%1 = atomicrmw sub ptr %a, i64 %b seq_cst
ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 12132563c97d1..b1e4645c0d27f 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS,RV32IA-WMO,RV32IA-WMO-NOZACAS %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS,RV32IA-TSO,RV32IA-TSO-NOZACAS %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-NOZACAS,RV64IA-WMO,RV64IA-WMO-NOZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \
@@ -50,6 +54,26 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB0_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -80,6 +104,26 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB0_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -174,6 +218,26 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB1_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -224,6 +288,26 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB1_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -378,6 +462,26 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB2_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -428,6 +532,26 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB2_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -582,6 +706,26 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB3_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -632,6 +776,26 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB3_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -786,6 +950,26 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB4_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -816,6 +1000,26 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB4_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -914,6 +1118,22 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB5_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -936,6 +1156,22 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB5_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -1004,6 +1240,22 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB6_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1037,6 +1289,22 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB6_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1138,6 +1406,22 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB7_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1171,6 +1455,22 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB7_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1272,6 +1572,22 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB8_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1305,6 +1621,22 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB8_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1406,6 +1738,22 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB9_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1439,6 +1787,22 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB9_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1540,6 +1904,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB10_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -1561,6 +1940,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB10_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -1630,6 +2024,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB11_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1661,6 +2070,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB11_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1760,6 +2184,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB12_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1791,6 +2230,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB12_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1890,6 +2344,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB13_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -1921,6 +2390,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB13_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -2020,6 +2504,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a2, 255
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB14_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -2051,6 +2550,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a2, 255
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB14_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -2149,6 +2663,26 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB15_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -2179,6 +2713,26 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB15_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -2273,6 +2827,26 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB16_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -2323,6 +2897,26 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB16_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -2477,6 +3071,26 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB17_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -2527,6 +3141,26 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB17_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -2681,6 +3315,26 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB18_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -2731,6 +3385,26 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB18_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -2885,6 +3559,26 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB19_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -2915,6 +3609,26 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB19_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3009,6 +3723,26 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB20_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3039,6 +3773,26 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB20_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3137,6 +3891,26 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB21_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -3187,6 +3961,26 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB21_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -3345,6 +4139,26 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB22_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -3395,6 +4209,26 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB22_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -3553,6 +4387,26 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB23_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -3603,6 +4457,26 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB23_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -3761,6 +4635,26 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB24_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3791,6 +4685,26 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB24_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3889,6 +4803,25 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB25_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3913,6 +4846,25 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB25_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -3989,6 +4941,25 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB26_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4027,6 +4998,25 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB26_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4145,6 +5135,25 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB27_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4183,6 +5192,25 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB27_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4301,6 +5329,25 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB28_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4339,6 +5386,25 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB28_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4457,6 +5523,25 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB29_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4495,6 +5580,25 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB29_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4613,6 +5717,27 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a4, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB30_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -4644,6 +5769,27 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a4, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB30_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -4865,6 +6011,27 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a4, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB31_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -4917,6 +6084,27 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a4, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB31_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -5201,6 +6389,27 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a4, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB32_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -5253,6 +6462,27 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a4, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB32_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -5537,6 +6767,27 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a4, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB33_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -5589,6 +6840,27 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a4, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB33_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -5873,6 +7145,27 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a4, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB34_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -5904,6 +7197,27 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a4, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB34_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -6129,6 +7443,21 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB35_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -6149,6 +7478,21 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB35_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -6213,6 +7557,21 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB36_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6243,6 +7602,21 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB36_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6337,6 +7711,21 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB37_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6367,6 +7756,21 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB37_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6461,6 +7865,21 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB38_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6491,6 +7910,21 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB38_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6585,6 +8019,21 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB39_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6615,6 +8064,21 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB39_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6709,6 +8173,21 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB40_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -6729,6 +8208,21 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB40_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -6793,6 +8287,21 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB41_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6823,6 +8332,21 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB41_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6917,6 +8441,21 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB42_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -6947,6 +8486,21 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB42_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7041,6 +8595,21 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB43_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7071,6 +8640,21 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB43_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7165,6 +8749,21 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB44_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7195,6 +8794,21 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB44_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7321,6 +8935,35 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB45_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB45_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -7392,6 +9035,35 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB45_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB45_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -7545,6 +9217,35 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB46_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB46_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7645,6 +9346,35 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB46_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB46_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7885,6 +9615,35 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB47_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB47_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -7985,6 +9744,35 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB47_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB47_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -8225,6 +10013,35 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB48_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB48_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -8325,6 +10142,35 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB48_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB48_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -8565,6 +10411,35 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB49_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB49_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -8636,6 +10511,35 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB49_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB49_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -8789,6 +10693,35 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB50_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB50_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -8860,6 +10793,35 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB50_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB50_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -9013,6 +10975,35 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB51_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB51_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -9113,6 +11104,35 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB51_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB51_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -9353,6 +11373,35 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB52_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB52_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -9453,6 +11502,35 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB52_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB52_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -9693,6 +11771,35 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB53_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB53_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -9793,6 +11900,35 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB53_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB53_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -10033,6 +12169,35 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB54_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB54_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -10104,6 +12269,35 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB54_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB54_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -10255,6 +12449,30 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB55_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB55_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -10319,6 +12537,30 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB55_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB55_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -10455,6 +12697,30 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB56_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB56_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -10543,6 +12809,30 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB56_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB56_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -10751,6 +13041,30 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB57_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB57_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -10839,6 +13153,30 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB57_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB57_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -11047,6 +13385,30 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB58_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB58_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -11135,6 +13497,30 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB58_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB58_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -11343,6 +13729,30 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB59_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB59_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -11407,6 +13817,30 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB59_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB59_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -11543,6 +13977,30 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB60_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB60_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -11607,6 +14065,30 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB60_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB60_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -11743,6 +14225,30 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB61_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB61_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -11831,6 +14337,30 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB61_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB61_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -12039,6 +14569,30 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB62_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB62_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -12127,6 +14681,30 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB62_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB62_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -12335,6 +14913,30 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB63_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB63_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -12423,6 +15025,30 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB63_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB63_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -12631,6 +15257,30 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB64_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB64_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -12695,6 +15345,30 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB64_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB64_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -12801,6 +15475,27 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB65_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -12832,6 +15527,27 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB65_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -12929,6 +15645,27 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB66_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -12981,6 +15718,27 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB66_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -13141,6 +15899,27 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB67_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -13193,6 +15972,27 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB67_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -13353,6 +16153,27 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB68_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -13405,6 +16226,27 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB68_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -13565,6 +16407,27 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB69_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -13596,6 +16459,27 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB69_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -13697,6 +16581,23 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB70_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB70_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -13720,6 +16621,23 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB70_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB70_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -13791,6 +16709,23 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB71_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB71_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -13826,6 +16761,23 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB71_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB71_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -13933,6 +16885,23 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB72_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB72_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -13968,6 +16937,23 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB72_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB72_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14075,6 +17061,23 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB73_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB73_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14110,6 +17113,23 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB73_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB73_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14217,6 +17237,23 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: not a2, a2
+; RV32I-ZALRSC-NEXT: .LBB74_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV32I-ZALRSC-NEXT: and a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB74_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14252,6 +17289,23 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: not a2, a2
+; RV64I-ZALRSC-NEXT: .LBB74_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV64I-ZALRSC-NEXT: and a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB74_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14360,6 +17414,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB75_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -14383,6 +17453,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB75_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
@@ -14456,6 +17542,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB76_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14490,6 +17592,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB76_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14596,6 +17714,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB77_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14630,6 +17764,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB77_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14736,6 +17886,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB78_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14770,6 +17936,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB78_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14876,6 +18058,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a1, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a2, 16
+; RV32I-ZALRSC-NEXT: addi a2, a2, -1
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV32I-ZALRSC-NEXT: or a4, a3, a2
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB79_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -14910,6 +18108,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a2, 16
+; RV64I-ZALRSC-NEXT: addi a2, a2, -1
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1)
+; RV64I-ZALRSC-NEXT: or a4, a3, a2
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB79_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
@@ -15014,6 +18228,27 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB80_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -15045,6 +18280,27 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB80_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -15142,6 +18398,27 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB81_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -15194,6 +18471,27 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB81_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -15354,6 +18652,27 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB82_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -15406,6 +18725,27 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB82_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -15566,6 +18906,27 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB83_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -15618,6 +18979,27 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB83_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -15778,6 +19160,27 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB84_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -15809,6 +19212,27 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB84_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -15906,6 +19330,27 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB85_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -15937,6 +19382,27 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB85_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -16038,6 +19504,27 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB86_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16090,6 +19577,27 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB86_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16254,6 +19762,27 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB87_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16306,6 +19835,27 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB87_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16470,6 +20020,27 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB88_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16522,6 +20093,27 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB88_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16686,6 +20278,27 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB89_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -16717,6 +20330,27 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB89_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -16818,6 +20452,26 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: not a3, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB90_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -16843,6 +20497,26 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: not a3, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB90_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -16922,6 +20596,26 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: not a3, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB91_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -16962,6 +20656,26 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: not a3, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB91_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17086,6 +20800,26 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: not a3, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB92_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17126,6 +20860,26 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: not a3, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB92_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17250,6 +21004,26 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: not a3, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB93_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17290,6 +21064,26 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: not a3, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB93_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17414,6 +21208,26 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: not a3, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB94_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17454,6 +21268,26 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: not a3, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB94_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17578,6 +21412,28 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a3, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB95_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -17610,6 +21466,28 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a3, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB95_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -17838,6 +21716,28 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a3, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB96_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -17892,6 +21792,28 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a3, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB96_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -18186,6 +22108,28 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a3, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB97_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -18240,6 +22184,28 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a3, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB97_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -18534,6 +22500,28 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a3, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB98_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -18588,6 +22576,28 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a3, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB98_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -18882,6 +22892,28 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a3, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB99_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -18914,6 +22946,28 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a3, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB99_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -19146,6 +23200,22 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB100_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -19167,6 +23237,22 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB100_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -19234,6 +23320,22 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB101_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19266,6 +23368,22 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB101_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19366,6 +23484,22 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB102_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19398,6 +23532,22 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB102_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19498,6 +23648,22 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB103_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19530,6 +23696,22 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB103_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19630,6 +23812,22 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB104_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19662,6 +23860,22 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB104_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19762,6 +23976,22 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB105_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -19783,6 +24013,22 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB105_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -19850,6 +24096,22 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB106_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19882,6 +24144,22 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB106_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -19982,6 +24260,22 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB107_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20014,6 +24308,22 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB107_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20114,6 +24424,22 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB108_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20146,6 +24472,22 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB108_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20246,6 +24588,22 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB109_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20278,6 +24636,22 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB109_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20410,6 +24784,37 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB110_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB110_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -20483,6 +24888,37 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB110_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB110_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -20642,6 +25078,37 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB111_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB111_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20746,6 +25213,37 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB111_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB111_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -20998,6 +25496,37 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB112_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB112_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -21102,6 +25631,37 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB112_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB112_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -21354,6 +25914,37 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB113_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB113_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -21458,6 +26049,37 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB113_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB113_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -21710,6 +26332,37 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB114_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB114_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -21783,6 +26436,37 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB114_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB114_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -21942,6 +26626,37 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB115_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB115_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -22015,6 +26730,37 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB115_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB115_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -22174,6 +26920,37 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB116_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB116_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -22278,6 +27055,37 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB116_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB116_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -22530,6 +27338,37 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB117_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB117_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -22634,6 +27473,37 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB117_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB117_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -22886,6 +27756,37 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB118_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB118_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -22990,6 +27891,37 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB118_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB118_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -23242,6 +28174,37 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB119_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB119_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -23315,6 +28278,37 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB119_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB119_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -23476,6 +28470,31 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB120_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB120_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -23545,6 +28564,31 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB120_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB120_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -23688,6 +28732,31 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB121_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB121_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -23782,6 +28851,31 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB121_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB121_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -24000,6 +29094,31 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB122_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB122_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -24094,6 +29213,31 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB122_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB122_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -24312,6 +29456,31 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB123_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB123_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -24406,6 +29575,31 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB123_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB123_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -24624,6 +29818,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB124_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB124_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -24693,6 +29912,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB124_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB124_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -24836,6 +30080,31 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB125_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB125_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -24905,6 +30174,31 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB125_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB125_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -25048,6 +30342,31 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB126_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB126_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -25142,6 +30461,31 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB126_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB126_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -25360,6 +30704,31 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB127_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB127_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -25454,6 +30823,31 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB127_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB127_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -25672,6 +31066,31 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB128_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB128_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -25766,6 +31185,31 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB128_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB128_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
@@ -25984,6 +31428,31 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB129_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB129_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -26053,6 +31522,31 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB129_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB129_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
@@ -26162,6 +31656,17 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB130_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xchg_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w a0, a1, (a0)
@@ -26177,6 +31682,17 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB130_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w a0, a1, (a0)
@@ -26196,6 +31712,17 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB131_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoswap.w.aq a0, a1, (a0)
@@ -26216,6 +31743,17 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB131_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.w.aq a0, a1, (a0)
@@ -26240,6 +31778,17 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB132_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoswap.w.rl a0, a1, (a0)
@@ -26260,6 +31809,17 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB132_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.w.rl a0, a1, (a0)
@@ -26284,6 +31844,17 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB133_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
@@ -26304,6 +31875,17 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB133_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
@@ -26328,6 +31910,17 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB134_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
@@ -26348,6 +31941,17 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB134_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
@@ -26372,6 +31976,17 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB135_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: add a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB135_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_add_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w a0, a1, (a0)
@@ -26387,6 +32002,17 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB135_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB135_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_add_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w a0, a1, (a0)
@@ -26406,6 +32032,17 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB136_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: add a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB136_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_add_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0)
@@ -26426,6 +32063,17 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB136_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB136_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0)
@@ -26450,6 +32098,17 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB137_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: add a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB137_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_add_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0)
@@ -26470,6 +32129,17 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB137_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB137_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0)
@@ -26494,6 +32164,17 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB138_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: add a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB138_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_add_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
@@ -26514,6 +32195,17 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB138_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB138_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
@@ -26538,6 +32230,17 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB139_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: add a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB139_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_add_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
@@ -26558,6 +32261,17 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB139_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB139_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
@@ -26582,6 +32296,17 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB140_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB140_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_sub_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1
@@ -26598,6 +32323,17 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB140_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB140_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_sub_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1
@@ -26618,6 +32354,17 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB141_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB141_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_sub_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: neg a1, a1
@@ -26640,6 +32387,17 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB141_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB141_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -26666,6 +32424,17 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB142_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB142_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_sub_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: neg a1, a1
@@ -26688,6 +32457,17 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB142_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB142_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -26714,6 +32494,17 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB143_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB143_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_sub_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: neg a1, a1
@@ -26736,6 +32527,17 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB143_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB143_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -26762,6 +32564,17 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB144_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB144_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_sub_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: neg a1, a1
@@ -26784,6 +32597,17 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB144_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB144_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -26810,6 +32634,17 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB145_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB145_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_and_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w a0, a1, (a0)
@@ -26825,6 +32660,17 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB145_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB145_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_and_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w a0, a1, (a0)
@@ -26844,6 +32690,17 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB146_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB146_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_and_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoand.w.aq a0, a1, (a0)
@@ -26864,6 +32721,17 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB146_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB146_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.w.aq a0, a1, (a0)
@@ -26888,6 +32756,17 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB147_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB147_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_and_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoand.w.rl a0, a1, (a0)
@@ -26908,6 +32787,17 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB147_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB147_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.w.rl a0, a1, (a0)
@@ -26932,6 +32822,17 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB148_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB148_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_and_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
@@ -26952,6 +32853,17 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB148_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB148_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
@@ -26976,6 +32888,17 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB149_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB149_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_and_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
@@ -26996,6 +32919,17 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB149_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB149_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
@@ -27020,6 +32954,18 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB150_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
@@ -27042,6 +32988,18 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB150_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
@@ -27200,6 +33158,18 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB151_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acquire:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
@@ -27234,6 +33204,18 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB151_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
@@ -27432,6 +33414,18 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB152_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_release:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
@@ -27466,6 +33460,18 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB152_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
@@ -27664,6 +33670,18 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB153_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
; RV32IA-WMO-NOZACAS: # %bb.0:
; RV32IA-WMO-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
@@ -27698,6 +33716,18 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB153_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
@@ -27896,6 +33926,18 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB154_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
; RV32IA-NOZACAS: # %bb.0:
; RV32IA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
@@ -27918,6 +33960,18 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB154_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
@@ -28112,6 +34166,17 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB155_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: or a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB155_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_or_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w a0, a1, (a0)
@@ -28127,6 +34192,17 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB155_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB155_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_or_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w a0, a1, (a0)
@@ -28146,6 +34222,17 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB156_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: or a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB156_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_or_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoor.w.aq a0, a1, (a0)
@@ -28166,6 +34253,17 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB156_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB156_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.w.aq a0, a1, (a0)
@@ -28190,6 +34288,17 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB157_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: or a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB157_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_or_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoor.w.rl a0, a1, (a0)
@@ -28210,6 +34319,17 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB157_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB157_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.w.rl a0, a1, (a0)
@@ -28234,6 +34354,17 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB158_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: or a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB158_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_or_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
@@ -28254,6 +34385,17 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB158_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB158_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
@@ -28278,6 +34420,17 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB159_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: or a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB159_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_or_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
@@ -28298,6 +34451,17 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB159_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB159_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
@@ -28322,6 +34486,17 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB160_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: xor a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB160_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xor_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w a0, a1, (a0)
@@ -28337,6 +34512,17 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB160_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB160_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_xor_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w a0, a1, (a0)
@@ -28356,6 +34542,17 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB161_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: xor a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB161_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xor_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoxor.w.aq a0, a1, (a0)
@@ -28376,6 +34573,17 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB161_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB161_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.w.aq a0, a1, (a0)
@@ -28400,6 +34608,17 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB162_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: xor a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB162_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xor_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoxor.w.rl a0, a1, (a0)
@@ -28420,6 +34639,17 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB162_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB162_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.w.rl a0, a1, (a0)
@@ -28444,6 +34674,17 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB163_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: xor a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB163_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xor_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
@@ -28464,6 +34705,17 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB163_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB163_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
@@ -28488,6 +34740,17 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB164_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: xor a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB164_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_xor_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
@@ -28508,6 +34771,17 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB164_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB164_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
@@ -28558,6 +34832,21 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB165_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB165_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB165_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB165_3: # in Loop: Header=BB165_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB165_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_max_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w a0, a1, (a0)
@@ -28602,6 +34891,21 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB165_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB165_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB165_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB165_3: # in Loop: Header=BB165_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB165_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w a0, a1, (a0)
@@ -28647,6 +34951,21 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB166_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB166_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB166_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB166_3: # in Loop: Header=BB166_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB166_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_max_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomax.w.aq a0, a1, (a0)
@@ -28696,6 +35015,21 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB166_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB166_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB166_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB166_3: # in Loop: Header=BB166_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB166_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.w.aq a0, a1, (a0)
@@ -28746,6 +35080,21 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB167_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB167_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB167_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB167_3: # in Loop: Header=BB167_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB167_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_max_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomax.w.rl a0, a1, (a0)
@@ -28795,6 +35144,21 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB167_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB167_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB167_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB167_3: # in Loop: Header=BB167_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB167_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.w.rl a0, a1, (a0)
@@ -28845,6 +35209,21 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB168_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB168_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB168_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB168_3: # in Loop: Header=BB168_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB168_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_max_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
@@ -28894,6 +35273,21 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB168_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB168_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB168_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB168_3: # in Loop: Header=BB168_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB168_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
@@ -28944,6 +35338,21 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB169_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB169_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB169_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB169_3: # in Loop: Header=BB169_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB169_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_max_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
@@ -28993,6 +35402,21 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB169_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB169_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB169_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB169_3: # in Loop: Header=BB169_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB169_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
@@ -29043,6 +35467,21 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB170_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB170_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB170_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB170_3: # in Loop: Header=BB170_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB170_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_min_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w a0, a1, (a0)
@@ -29087,6 +35526,21 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB170_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB170_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB170_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB170_3: # in Loop: Header=BB170_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB170_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w a0, a1, (a0)
@@ -29132,6 +35586,21 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB171_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB171_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB171_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB171_3: # in Loop: Header=BB171_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB171_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_min_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomin.w.aq a0, a1, (a0)
@@ -29181,6 +35650,21 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB171_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB171_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB171_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB171_3: # in Loop: Header=BB171_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB171_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.w.aq a0, a1, (a0)
@@ -29231,6 +35715,21 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB172_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB172_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB172_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB172_3: # in Loop: Header=BB172_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB172_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_min_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomin.w.rl a0, a1, (a0)
@@ -29280,6 +35779,21 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB172_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB172_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB172_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB172_3: # in Loop: Header=BB172_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB172_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.w.rl a0, a1, (a0)
@@ -29330,6 +35844,21 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB173_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB173_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB173_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB173_3: # in Loop: Header=BB173_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB173_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_min_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
@@ -29379,6 +35908,21 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB173_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB173_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB173_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB173_3: # in Loop: Header=BB173_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB173_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
@@ -29429,6 +35973,21 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB174_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB174_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB174_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB174_3: # in Loop: Header=BB174_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB174_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_min_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
@@ -29478,6 +36037,21 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB174_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB174_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB174_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB174_3: # in Loop: Header=BB174_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB174_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
@@ -29528,6 +36102,21 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB175_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB175_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB175_3: # in Loop: Header=BB175_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB175_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w a0, a1, (a0)
@@ -29572,6 +36161,22 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB175_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB175_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB175_3: # in Loop: Header=BB175_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB175_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w a0, a1, (a0)
@@ -29617,6 +36222,21 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB176_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB176_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB176_3: # in Loop: Header=BB176_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB176_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umax_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomaxu.w.aq a0, a1, (a0)
@@ -29666,6 +36286,22 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB176_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB176_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB176_3: # in Loop: Header=BB176_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB176_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.w.aq a0, a1, (a0)
@@ -29716,6 +36352,21 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB177_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB177_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB177_3: # in Loop: Header=BB177_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB177_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umax_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomaxu.w.rl a0, a1, (a0)
@@ -29765,6 +36416,22 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB177_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB177_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB177_3: # in Loop: Header=BB177_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB177_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.w.rl a0, a1, (a0)
@@ -29815,6 +36482,21 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB178_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB178_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB178_3: # in Loop: Header=BB178_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB178_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
@@ -29864,6 +36546,22 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB178_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB178_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB178_3: # in Loop: Header=BB178_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB178_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
@@ -29914,6 +36612,21 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB179_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB179_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB179_3: # in Loop: Header=BB179_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB179_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
@@ -29963,6 +36676,22 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB179_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB179_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB179_3: # in Loop: Header=BB179_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB179_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
@@ -30013,6 +36742,21 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB180_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB180_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB180_3: # in Loop: Header=BB180_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB180_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w a0, a1, (a0)
@@ -30057,6 +36801,22 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB180_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB180_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB180_3: # in Loop: Header=BB180_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB180_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w a0, a1, (a0)
@@ -30102,6 +36862,21 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB181_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB181_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB181_3: # in Loop: Header=BB181_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB181_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umin_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amominu.w.aq a0, a1, (a0)
@@ -30151,6 +36926,22 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB181_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB181_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB181_3: # in Loop: Header=BB181_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB181_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.w.aq a0, a1, (a0)
@@ -30201,6 +36992,21 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB182_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB182_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB182_3: # in Loop: Header=BB182_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB182_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umin_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amominu.w.rl a0, a1, (a0)
@@ -30250,6 +37056,22 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB182_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB182_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB182_3: # in Loop: Header=BB182_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB182_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.w.rl a0, a1, (a0)
@@ -30300,6 +37122,21 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB183_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB183_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB183_3: # in Loop: Header=BB183_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB183_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
@@ -30349,6 +37186,22 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB183_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB183_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB183_3: # in Loop: Header=BB183_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB183_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
@@ -30399,6 +37252,21 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB184_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB184_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB184_3: # in Loop: Header=BB184_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB184_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
@@ -30448,6 +37316,22 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB184_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB184_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB184_3: # in Loop: Header=BB184_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB184_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
@@ -30472,6 +37356,16 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_exchange_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xchg_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30492,6 +37386,17 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB185_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB185_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d a0, a1, (a0)
@@ -30511,6 +37416,16 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_exchange_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xchg_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30531,6 +37446,17 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB186_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB186_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.d.aq a0, a1, (a0)
@@ -30555,6 +37481,16 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_exchange_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xchg_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30575,6 +37511,17 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB187_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB187_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.d.rl a0, a1, (a0)
@@ -30599,6 +37546,16 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_exchange_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30619,6 +37576,17 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB188_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB188_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.d.aqrl a0, a1, (a0)
@@ -30643,6 +37611,16 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_exchange_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30663,6 +37641,17 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB189_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoswap.d.aqrl a0, a1, (a0)
@@ -30687,6 +37676,16 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_add_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30707,6 +37706,17 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB190_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB190_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_add_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d a0, a1, (a0)
@@ -30726,6 +37736,16 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_add_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30746,6 +37766,17 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB191_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB191_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.d.aq a0, a1, (a0)
@@ -30770,6 +37801,16 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_add_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30790,6 +37831,17 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB192_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB192_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.d.rl a0, a1, (a0)
@@ -30814,6 +37866,16 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_add_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30834,6 +37896,17 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB193_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB193_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0)
@@ -30858,6 +37931,16 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_add_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30878,6 +37961,17 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB194_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB194_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_add_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0)
@@ -30902,6 +37996,16 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_sub_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30922,6 +38026,17 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB195_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB195_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_sub_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1
@@ -30942,6 +38057,16 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_sub_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -30962,6 +38087,17 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB196_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB196_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -30988,6 +38124,16 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_sub_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31008,6 +38154,17 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB197_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB197_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -31034,6 +38191,16 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_sub_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31054,6 +38221,17 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB198_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB198_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -31080,6 +38258,16 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_sub_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31100,6 +38288,17 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB199_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB199_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_sub_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: neg a1, a1
@@ -31126,6 +38325,16 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_and_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31146,6 +38355,17 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB200_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB200_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_and_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d a0, a1, (a0)
@@ -31165,6 +38385,16 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_and_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31185,6 +38415,17 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB201_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB201_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.d.aq a0, a1, (a0)
@@ -31209,6 +38450,16 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_and_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31229,6 +38480,17 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB202_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB202_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.d.rl a0, a1, (a0)
@@ -31253,6 +38515,16 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_and_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31273,6 +38545,17 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB203_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB203_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.d.aqrl a0, a1, (a0)
@@ -31297,6 +38580,16 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_and_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31317,6 +38610,17 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB204_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB204_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_and_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoand.d.aqrl a0, a1, (a0)
@@ -31341,6 +38645,16 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_nand_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31361,6 +38675,18 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB205_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i64_monotonic:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1
@@ -31453,6 +38779,16 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_nand_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31473,6 +38809,18 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB206_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i64_acquire:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1
@@ -31591,6 +38939,16 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_nand_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31611,6 +38969,18 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB207_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i64_release:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1
@@ -31729,6 +39099,16 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_nand_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31749,6 +39129,18 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB208_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
; RV64IA-WMO-NOZACAS: # %bb.0:
; RV64IA-WMO-NOZACAS-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1
@@ -31867,6 +39259,16 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_nand_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -31887,6 +39289,18 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB209_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
; RV64IA-NOZACAS: # %bb.0:
; RV64IA-NOZACAS-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1
@@ -31997,6 +39411,16 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_or_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32017,6 +39441,17 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB210_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB210_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_or_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d a0, a1, (a0)
@@ -32036,6 +39471,16 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_or_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32056,6 +39501,17 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB211_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB211_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.d.aq a0, a1, (a0)
@@ -32080,6 +39536,16 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_or_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32100,6 +39566,17 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB212_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB212_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.d.rl a0, a1, (a0)
@@ -32124,6 +39601,16 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_or_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32144,6 +39631,17 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB213_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB213_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.d.aqrl a0, a1, (a0)
@@ -32168,6 +39666,16 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_or_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32188,6 +39696,17 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB214_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB214_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_or_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoor.d.aqrl a0, a1, (a0)
@@ -32212,6 +39731,16 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xor_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32232,6 +39761,17 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB215_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB215_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_xor_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d a0, a1, (a0)
@@ -32251,6 +39791,16 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 2
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xor_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32271,6 +39821,17 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB216_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB216_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.d.aq a0, a1, (a0)
@@ -32295,6 +39856,16 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xor_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32315,6 +39886,17 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB217_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB217_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.d.rl a0, a1, (a0)
@@ -32339,6 +39921,16 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 4
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xor_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32359,6 +39951,17 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB218_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB218_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.d.aqrl a0, a1, (a0)
@@ -32383,6 +39986,16 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_xor_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -32403,6 +40016,17 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB219_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB219_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_xor_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amoxor.d.aqrl a0, a1, (a0)
@@ -32471,6 +40095,60 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB220_2
+; RV32I-ZALRSC-NEXT: .LBB220_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB220_7
+; RV32I-ZALRSC-NEXT: .LBB220_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB220_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB220_5
+; RV32I-ZALRSC-NEXT: .LBB220_4: # in Loop: Header=BB220_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB220_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB220_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB220_1
+; RV32I-ZALRSC-NEXT: .LBB220_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_max_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -32561,6 +40239,21 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB220_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB220_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB220_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB220_3: # in Loop: Header=BB220_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB220_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_max_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d a0, a1, (a0)
@@ -32624,6 +40317,60 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB221_2
+; RV32I-ZALRSC-NEXT: .LBB221_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 2
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB221_7
+; RV32I-ZALRSC-NEXT: .LBB221_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB221_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB221_5
+; RV32I-ZALRSC-NEXT: .LBB221_4: # in Loop: Header=BB221_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB221_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB221_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB221_1
+; RV32I-ZALRSC-NEXT: .LBB221_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_max_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -32714,6 +40461,21 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB221_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB221_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB221_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB221_3: # in Loop: Header=BB221_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB221_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.d.aq a0, a1, (a0)
@@ -32782,6 +40544,60 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB222_2
+; RV32I-ZALRSC-NEXT: .LBB222_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 3
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB222_7
+; RV32I-ZALRSC-NEXT: .LBB222_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB222_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB222_5
+; RV32I-ZALRSC-NEXT: .LBB222_4: # in Loop: Header=BB222_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB222_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB222_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB222_1
+; RV32I-ZALRSC-NEXT: .LBB222_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_max_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -32872,6 +40688,21 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB222_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB222_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB222_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB222_3: # in Loop: Header=BB222_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB222_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.d.rl a0, a1, (a0)
@@ -32940,6 +40771,60 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB223_2
+; RV32I-ZALRSC-NEXT: .LBB223_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 4
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB223_7
+; RV32I-ZALRSC-NEXT: .LBB223_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB223_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB223_5
+; RV32I-ZALRSC-NEXT: .LBB223_4: # in Loop: Header=BB223_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB223_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB223_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB223_1
+; RV32I-ZALRSC-NEXT: .LBB223_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33030,6 +40915,21 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB223_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB223_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB223_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB223_3: # in Loop: Header=BB223_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB223_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.d.aqrl a0, a1, (a0)
@@ -33098,6 +40998,60 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB224_2
+; RV32I-ZALRSC-NEXT: .LBB224_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 5
+; RV32I-ZALRSC-NEXT: li a5, 5
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB224_7
+; RV32I-ZALRSC-NEXT: .LBB224_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB224_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB224_5
+; RV32I-ZALRSC-NEXT: .LBB224_4: # in Loop: Header=BB224_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB224_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB224_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB224_1
+; RV32I-ZALRSC-NEXT: .LBB224_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_max_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33188,6 +41142,21 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB224_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB224_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB224_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB224_3: # in Loop: Header=BB224_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB224_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_max_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomax.d.aqrl a0, a1, (a0)
@@ -33256,6 +41225,60 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB225_2
+; RV32I-ZALRSC-NEXT: .LBB225_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB225_7
+; RV32I-ZALRSC-NEXT: .LBB225_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB225_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB225_5
+; RV32I-ZALRSC-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB225_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB225_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB225_1
+; RV32I-ZALRSC-NEXT: .LBB225_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_min_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33346,6 +41369,21 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB225_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB225_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB225_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB225_3: # in Loop: Header=BB225_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB225_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_min_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d a0, a1, (a0)
@@ -33409,6 +41447,60 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB226_2
+; RV32I-ZALRSC-NEXT: .LBB226_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 2
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB226_7
+; RV32I-ZALRSC-NEXT: .LBB226_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB226_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB226_5
+; RV32I-ZALRSC-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB226_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB226_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB226_1
+; RV32I-ZALRSC-NEXT: .LBB226_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_min_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33499,6 +41591,21 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB226_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB226_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB226_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB226_3: # in Loop: Header=BB226_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB226_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.d.aq a0, a1, (a0)
@@ -33567,6 +41674,60 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB227_2
+; RV32I-ZALRSC-NEXT: .LBB227_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 3
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB227_7
+; RV32I-ZALRSC-NEXT: .LBB227_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB227_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB227_5
+; RV32I-ZALRSC-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB227_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB227_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB227_1
+; RV32I-ZALRSC-NEXT: .LBB227_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_min_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33657,6 +41818,21 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB227_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB227_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB227_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB227_3: # in Loop: Header=BB227_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB227_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.d.rl a0, a1, (a0)
@@ -33725,6 +41901,60 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB228_2
+; RV32I-ZALRSC-NEXT: .LBB228_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 4
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB228_7
+; RV32I-ZALRSC-NEXT: .LBB228_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB228_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB228_5
+; RV32I-ZALRSC-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB228_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB228_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB228_1
+; RV32I-ZALRSC-NEXT: .LBB228_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_min_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33815,6 +42045,21 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB228_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB228_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB228_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB228_3: # in Loop: Header=BB228_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB228_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.d.aqrl a0, a1, (a0)
@@ -33883,6 +42128,60 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB229_2
+; RV32I-ZALRSC-NEXT: .LBB229_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 5
+; RV32I-ZALRSC-NEXT: li a5, 5
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB229_7
+; RV32I-ZALRSC-NEXT: .LBB229_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB229_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB229_5
+; RV32I-ZALRSC-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB229_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB229_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB229_1
+; RV32I-ZALRSC-NEXT: .LBB229_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_min_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -33973,6 +42272,21 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB229_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB229_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB229_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB229_3: # in Loop: Header=BB229_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB229_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_min_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomin.d.aqrl a0, a1, (a0)
@@ -34041,6 +42355,60 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB230_2
+; RV32I-ZALRSC-NEXT: .LBB230_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB230_7
+; RV32I-ZALRSC-NEXT: .LBB230_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB230_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB230_5
+; RV32I-ZALRSC-NEXT: .LBB230_4: # in Loop: Header=BB230_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB230_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB230_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB230_1
+; RV32I-ZALRSC-NEXT: .LBB230_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umax_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -34131,6 +42499,21 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB230_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB230_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB230_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB230_3: # in Loop: Header=BB230_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB230_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_umax_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d a0, a1, (a0)
@@ -34194,6 +42577,60 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB231_2
+; RV32I-ZALRSC-NEXT: .LBB231_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 2
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB231_7
+; RV32I-ZALRSC-NEXT: .LBB231_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB231_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB231_5
+; RV32I-ZALRSC-NEXT: .LBB231_4: # in Loop: Header=BB231_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB231_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB231_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB231_1
+; RV32I-ZALRSC-NEXT: .LBB231_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umax_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -34284,6 +42721,21 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB231_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB231_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB231_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB231_3: # in Loop: Header=BB231_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB231_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.d.aq a0, a1, (a0)
@@ -34352,6 +42804,60 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB232_2
+; RV32I-ZALRSC-NEXT: .LBB232_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 3
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB232_7
+; RV32I-ZALRSC-NEXT: .LBB232_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB232_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB232_5
+; RV32I-ZALRSC-NEXT: .LBB232_4: # in Loop: Header=BB232_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB232_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB232_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB232_1
+; RV32I-ZALRSC-NEXT: .LBB232_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umax_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -34442,6 +42948,21 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB232_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB232_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB232_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB232_3: # in Loop: Header=BB232_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB232_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.d.rl a0, a1, (a0)
@@ -34510,6 +43031,60 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB233_2
+; RV32I-ZALRSC-NEXT: .LBB233_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 4
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB233_7
+; RV32I-ZALRSC-NEXT: .LBB233_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB233_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB233_5
+; RV32I-ZALRSC-NEXT: .LBB233_4: # in Loop: Header=BB233_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB233_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB233_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB233_1
+; RV32I-ZALRSC-NEXT: .LBB233_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -34600,6 +43175,21 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB233_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB233_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB233_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB233_3: # in Loop: Header=BB233_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB233_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.d.aqrl a0, a1, (a0)
@@ -34668,6 +43258,60 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB234_2
+; RV32I-ZALRSC-NEXT: .LBB234_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 5
+; RV32I-ZALRSC-NEXT: li a5, 5
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB234_7
+; RV32I-ZALRSC-NEXT: .LBB234_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB234_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB234_5
+; RV32I-ZALRSC-NEXT: .LBB234_4: # in Loop: Header=BB234_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB234_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB234_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB234_1
+; RV32I-ZALRSC-NEXT: .LBB234_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umax_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -34758,6 +43402,21 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB234_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB234_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB234_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB234_3: # in Loop: Header=BB234_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB234_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umax_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amomaxu.d.aqrl a0, a1, (a0)
@@ -34826,6 +43485,60 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB235_2
+; RV32I-ZALRSC-NEXT: .LBB235_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB235_7
+; RV32I-ZALRSC-NEXT: .LBB235_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB235_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB235_5
+; RV32I-ZALRSC-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB235_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB235_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB235_1
+; RV32I-ZALRSC-NEXT: .LBB235_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umin_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -34916,6 +43629,21 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB235_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB235_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB235_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB235_3: # in Loop: Header=BB235_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB235_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomicrmw_umin_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d a0, a1, (a0)
@@ -34979,6 +43707,60 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB236_2
+; RV32I-ZALRSC-NEXT: .LBB236_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 2
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB236_7
+; RV32I-ZALRSC-NEXT: .LBB236_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB236_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB236_5
+; RV32I-ZALRSC-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB236_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB236_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB236_1
+; RV32I-ZALRSC-NEXT: .LBB236_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umin_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -35069,6 +43851,21 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB236_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB236_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB236_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB236_3: # in Loop: Header=BB236_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB236_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.d.aq a0, a1, (a0)
@@ -35137,6 +43934,60 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB237_2
+; RV32I-ZALRSC-NEXT: .LBB237_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 3
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB237_7
+; RV32I-ZALRSC-NEXT: .LBB237_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB237_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB237_5
+; RV32I-ZALRSC-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB237_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB237_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB237_1
+; RV32I-ZALRSC-NEXT: .LBB237_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umin_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -35227,6 +44078,21 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB237_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB237_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB237_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB237_3: # in Loop: Header=BB237_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB237_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.d.rl a0, a1, (a0)
@@ -35295,6 +44161,60 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_acq_rel:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB238_2
+; RV32I-ZALRSC-NEXT: .LBB238_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 4
+; RV32I-ZALRSC-NEXT: li a5, 2
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB238_7
+; RV32I-ZALRSC-NEXT: .LBB238_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB238_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB238_5
+; RV32I-ZALRSC-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB238_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB238_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB238_1
+; RV32I-ZALRSC-NEXT: .LBB238_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -35385,6 +44305,21 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_acq_rel:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB238_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB238_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB238_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB238_3: # in Loop: Header=BB238_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB238_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i64_acq_rel:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.d.aqrl a0, a1, (a0)
@@ -35453,6 +44388,60 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB239_2
+; RV32I-ZALRSC-NEXT: .LBB239_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: li a4, 5
+; RV32I-ZALRSC-NEXT: li a5, 5
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB239_7
+; RV32I-ZALRSC-NEXT: .LBB239_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB239_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB239_5
+; RV32I-ZALRSC-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB239_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB239_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB239_1
+; RV32I-ZALRSC-NEXT: .LBB239_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomicrmw_umin_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32
@@ -35543,6 +44532,21 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB239_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB239_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB239_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB239_3: # in Loop: Header=BB239_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB239_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: amominu.d.aqrl a0, a1, (a0)
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index 7d29ac9944834..4b49271735492 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -5,12 +5,16 @@
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-NOZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s
define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV32I-LABEL: atomic_load_i8_unordered:
@@ -30,6 +34,11 @@ define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomic_load_i8_unordered:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -46,6 +55,11 @@ define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
%1 = load atomic i8, ptr %a unordered, align 1
ret i8 %1
}
@@ -68,6 +82,11 @@ define signext i16 @atomic_load_i16_unordered(ptr %a) nounwind {
; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomic_load_i16_unordered:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -84,6 +103,11 @@ define signext i16 @atomic_load_i16_unordered(ptr %a) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
%1 = load atomic i16, ptr %a unordered, align 2
ret i16 %1
}
@@ -104,6 +128,11 @@ define signext i32 @atomic_load_i32_unordered(ptr %a) nounwind {
; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomic_load_i32_unordered:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -119,6 +148,11 @@ define signext i32 @atomic_load_i32_unordered(ptr %a) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
%1 = load atomic i32, ptr %a unordered, align 4
ret i32 %1
}
@@ -159,6 +193,28 @@ define signext i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB3_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -192,6 +248,28 @@ define signext i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB3_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -231,6 +309,28 @@ define signext i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB4_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_add_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -264,6 +364,28 @@ define signext i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB4_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -303,6 +425,28 @@ define signext i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a4, a1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB5_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -336,6 +480,28 @@ define signext i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a4, a1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB5_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -369,6 +535,27 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB6_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_and_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -396,6 +583,27 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB6_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -436,6 +644,29 @@ define signext i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a4, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB7_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_nand_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -470,6 +701,29 @@ define signext i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a4, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB7_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -499,6 +753,23 @@ define signext i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB8_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_or_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -522,6 +793,23 @@ define signext i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB8_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -551,6 +839,23 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB9_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xor_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -574,6 +879,23 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB9_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -653,6 +975,37 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB10_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB10_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -726,6 +1079,37 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB10_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB10_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -805,6 +1189,37 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: slli a1, a1, 24
+; RV32I-ZALRSC-NEXT: andi a4, a0, 24
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: srai a1, a1, 24
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: xori a4, a4, 24
+; RV32I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB11_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB11_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -878,6 +1293,37 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: slli a1, a1, 56
+; RV64I-ZALRSC-NEXT: andi a4, a0, 24
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: srai a1, a1, 56
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: xori a4, a4, 56
+; RV64I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB11_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB11_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -950,6 +1396,32 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB12_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB12_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -1016,6 +1488,32 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB12_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB12_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -1088,6 +1586,32 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a3, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a4, a3
+; RV32I-ZALRSC-NEXT: mv a5, a4
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB13_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a4, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a3
+; RV32I-ZALRSC-NEXT: xor a5, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB13_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -1154,6 +1678,32 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a3, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a4, a3
+; RV64I-ZALRSC-NEXT: mv a5, a4
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB13_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a4, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a3
+; RV64I-ZALRSC-NEXT: xor a5, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB13_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -1194,6 +1744,29 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: mv a5, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB14_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1228,6 +1801,29 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: mv a5, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB14_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1268,6 +1864,29 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: add a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB15_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_add_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1302,6 +1921,29 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: add a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB15_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1342,6 +1984,29 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: sub a5, a3, a1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB16_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1376,6 +2041,29 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: sub a5, a3, a1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB16_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1410,6 +2098,28 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: not a3, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: or a1, a1, a3
+; RV32I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB17_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_and_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1438,6 +2148,28 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: not a3, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: or a1, a1, a3
+; RV64I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB17_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1479,6 +2211,30 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a5, a3, a1
+; RV32I-ZALRSC-NEXT: not a5, a5
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB18_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_nand_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1514,6 +2270,30 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a5, a3, a1
+; RV64I-ZALRSC-NEXT: not a5, a5
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB18_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1544,6 +2324,24 @@ define signext i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: or a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB19_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_or_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1568,6 +2366,24 @@ define signext i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: or a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB19_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1598,6 +2414,24 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: srli a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: xor a4, a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB20_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xor_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1622,6 +2456,24 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: srli a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: xor a4, a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB20_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1703,6 +2555,39 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB21_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB21_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -1778,6 +2663,39 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB21_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB21_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -1859,6 +2777,39 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: slli a1, a1, 16
+; RV32I-ZALRSC-NEXT: li a4, 16
+; RV32I-ZALRSC-NEXT: andi a5, a0, 24
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: srai a1, a1, 16
+; RV32I-ZALRSC-NEXT: sll a3, a3, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sub a4, a4, a5
+; RV32I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV32I-ZALRSC-NEXT: and a7, a5, a3
+; RV32I-ZALRSC-NEXT: mv a6, a5
+; RV32I-ZALRSC-NEXT: sll a7, a7, a4
+; RV32I-ZALRSC-NEXT: sra a7, a7, a4
+; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB22_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a1
+; RV32I-ZALRSC-NEXT: and a6, a6, a3
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB22_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -1934,6 +2885,39 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: slli a1, a1, 48
+; RV64I-ZALRSC-NEXT: li a4, 48
+; RV64I-ZALRSC-NEXT: andi a5, a0, 24
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: srai a1, a1, 48
+; RV64I-ZALRSC-NEXT: sllw a3, a3, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sub a4, a4, a5
+; RV64I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a2)
+; RV64I-ZALRSC-NEXT: and a7, a5, a3
+; RV64I-ZALRSC-NEXT: mv a6, a5
+; RV64I-ZALRSC-NEXT: sll a7, a7, a4
+; RV64I-ZALRSC-NEXT: sra a7, a7, a4
+; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB22_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a1
+; RV64I-ZALRSC-NEXT: and a6, a6, a3
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB22_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -2011,6 +2995,33 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB23_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB23_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -2082,6 +3093,33 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB23_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB23_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -2159,6 +3197,33 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a3, 16
+; RV32I-ZALRSC-NEXT: addi a3, a3, -1
+; RV32I-ZALRSC-NEXT: sll a4, a3, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a3
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV32I-ZALRSC-NEXT: and a6, a3, a4
+; RV32I-ZALRSC-NEXT: mv a5, a3
+; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB24_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a3, a1
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a3, a5
+; RV32I-ZALRSC-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB24_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: srl a0, a3, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -2230,6 +3295,33 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a3, 16
+; RV64I-ZALRSC-NEXT: addi a3, a3, -1
+; RV64I-ZALRSC-NEXT: sllw a4, a3, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a3
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a2)
+; RV64I-ZALRSC-NEXT: and a6, a3, a4
+; RV64I-ZALRSC-NEXT: mv a5, a3
+; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB24_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a3, a1
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a3, a5
+; RV64I-ZALRSC-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB24_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: srlw a0, a3, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -2250,6 +3342,17 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amoswap.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB25_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xchg_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2265,6 +3368,17 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB25_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xchg ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2285,6 +3399,17 @@ define signext i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amoadd.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: add a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB26_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_add_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2300,6 +3425,17 @@ define signext i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB26_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw add ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2321,6 +3457,17 @@ define signext i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amoadd.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: sub a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB27_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2337,6 +3484,17 @@ define signext i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB27_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw sub ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2357,6 +3515,17 @@ define signext i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amoand.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB28_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_and_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2372,6 +3541,17 @@ define signext i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB28_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw and ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2413,6 +3593,18 @@ define signext i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV32IA-ZACAS-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: and a3, a2, a1
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB29_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_nand_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2449,6 +3641,18 @@ define signext i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB29_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB29_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2469,6 +3673,17 @@ define signext i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amoor.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: or a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB30_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_or_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2484,6 +3699,17 @@ define signext i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB30_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2504,6 +3730,17 @@ define signext i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amoxor.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: xor a3, a2, a1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB31_1
+; RV32I-ZALRSC-NEXT: # %bb.2:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xor_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2519,6 +3756,17 @@ define signext i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB31_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xor ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2565,6 +3813,21 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amomax.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB32_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB32_3: # in Loop: Header=BB32_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB32_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -2608,6 +3871,21 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB32_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB32_3: # in Loop: Header=BB32_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB32_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2654,6 +3932,21 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amomin.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB33_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB33_3: # in Loop: Header=BB33_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB33_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -2697,6 +3990,21 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB33_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB33_3: # in Loop: Header=BB33_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB33_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2743,6 +4051,21 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amomaxu.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB34_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB34_3: # in Loop: Header=BB34_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB34_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -2786,6 +4109,22 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB34_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB34_3: # in Loop: Header=BB34_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB34_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2832,6 +4171,21 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32IA-NEXT: amominu.w a0, a1, (a0)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB35_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB35_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
@@ -2875,6 +4229,22 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a2, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB35_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB35_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -2900,6 +4270,16 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_exchange_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xchg_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2914,6 +4294,17 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB36_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xchg ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -2939,6 +4330,16 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_add_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2953,6 +4354,17 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB37_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw add ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -2978,6 +4390,16 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2993,6 +4415,17 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB38_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw sub ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3018,6 +4451,16 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_and_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -3032,6 +4475,17 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB39_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw and ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3057,6 +4511,16 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_nand_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -3092,6 +4556,18 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB40_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a2, a1
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB40_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3117,6 +4593,16 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_or_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -3131,6 +4617,17 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB41_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3156,6 +4653,16 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xor_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -3170,6 +4677,17 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a2, a1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB42_1
+; RV64I-ZALRSC-NEXT: # %bb.2:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw xor ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3283,6 +4801,60 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB43_2
+; RV32I-ZALRSC-NEXT: .LBB43_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB43_7
+; RV32I-ZALRSC-NEXT: .LBB43_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB43_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB43_5
+; RV32I-ZALRSC-NEXT: .LBB43_4: # in Loop: Header=BB43_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB43_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB43_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB43_1
+; RV32I-ZALRSC-NEXT: .LBB43_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_max_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -3323,6 +4895,21 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB43_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB43_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw max ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3436,6 +5023,60 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB44_2
+; RV32I-ZALRSC-NEXT: .LBB44_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB44_7
+; RV32I-ZALRSC-NEXT: .LBB44_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB44_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
+; RV32I-ZALRSC-NEXT: slt a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB44_5
+; RV32I-ZALRSC-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB44_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB44_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB44_1
+; RV32I-ZALRSC-NEXT: .LBB44_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_min_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -3476,6 +5117,21 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB44_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB44_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw min ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3589,6 +5245,60 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB45_2
+; RV32I-ZALRSC-NEXT: .LBB45_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB45_7
+; RV32I-ZALRSC-NEXT: .LBB45_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB45_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB45_5
+; RV32I-ZALRSC-NEXT: .LBB45_4: # in Loop: Header=BB45_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB45_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB45_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB45_1
+; RV32I-ZALRSC-NEXT: .LBB45_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umax_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -3629,6 +5339,21 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB45_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB45_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umax ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3742,6 +5467,60 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -32
+; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: mv s0, a2
+; RV32I-ZALRSC-NEXT: mv s1, a0
+; RV32I-ZALRSC-NEXT: lw a4, 0(a0)
+; RV32I-ZALRSC-NEXT: lw a5, 4(a0)
+; RV32I-ZALRSC-NEXT: mv s2, a1
+; RV32I-ZALRSC-NEXT: j .LBB46_2
+; RV32I-ZALRSC-NEXT: .LBB46_1: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
+; RV32I-ZALRSC-NEXT: sw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: sw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: addi a1, sp, 8
+; RV32I-ZALRSC-NEXT: mv a0, s1
+; RV32I-ZALRSC-NEXT: li a4, 0
+; RV32I-ZALRSC-NEXT: li a5, 0
+; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8
+; RV32I-ZALRSC-NEXT: lw a4, 8(sp)
+; RV32I-ZALRSC-NEXT: lw a5, 12(sp)
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB46_7
+; RV32I-ZALRSC-NEXT: .LBB46_2: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB46_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s0, a5
+; RV32I-ZALRSC-NEXT: j .LBB46_5
+; RV32I-ZALRSC-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
+; RV32I-ZALRSC-NEXT: sltu a0, s2, a4
+; RV32I-ZALRSC-NEXT: .LBB46_5: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, a4
+; RV32I-ZALRSC-NEXT: mv a3, a5
+; RV32I-ZALRSC-NEXT: beqz a0, .LBB46_1
+; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
+; RV32I-ZALRSC-NEXT: mv a2, s2
+; RV32I-ZALRSC-NEXT: mv a3, s0
+; RV32I-ZALRSC-NEXT: j .LBB46_1
+; RV32I-ZALRSC-NEXT: .LBB46_7: # %atomicrmw.end
+; RV32I-ZALRSC-NEXT: mv a0, a4
+; RV32I-ZALRSC-NEXT: mv a1, a5
+; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 32
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umin_i64_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -3782,6 +5561,21 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d a0, a1, (a0)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.d a2, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB46_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB46_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -3827,6 +5621,32 @@ define signext i8 @cmpxchg_i8_monotonic_monotonic_val0(ptr %ptr, i8 signext %cmp
; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val0:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a3, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a4, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: zext.b a2, a2
+; RV32I-ZALRSC-NEXT: sll a4, a4, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a5, (a3)
+; RV32I-ZALRSC-NEXT: and a6, a5, a4
+; RV32I-ZALRSC-NEXT: bne a6, a1, .LBB47_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a5, a2
+; RV32I-ZALRSC-NEXT: and a6, a6, a4
+; RV32I-ZALRSC-NEXT: xor a6, a5, a6
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a3)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB47_1
+; RV32I-ZALRSC-NEXT: .LBB47_3:
+; RV32I-ZALRSC-NEXT: srl a0, a5, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 24
+; RV32I-ZALRSC-NEXT: srai a0, a0, 24
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic_val0:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -3866,6 +5686,32 @@ define signext i8 @cmpxchg_i8_monotonic_monotonic_val0(ptr %ptr, i8 signext %cmp
; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val0:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a3, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a4, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: zext.b a2, a2
+; RV64I-ZALRSC-NEXT: sllw a4, a4, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a5, (a3)
+; RV64I-ZALRSC-NEXT: and a6, a5, a4
+; RV64I-ZALRSC-NEXT: bne a6, a1, .LBB47_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a5, a2
+; RV64I-ZALRSC-NEXT: and a6, a6, a4
+; RV64I-ZALRSC-NEXT: xor a6, a5, a6
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a3)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB47_1
+; RV64I-ZALRSC-NEXT: .LBB47_3:
+; RV64I-ZALRSC-NEXT: srlw a0, a5, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 56
+; RV64I-ZALRSC-NEXT: srai a0, a0, 56
+; RV64I-ZALRSC-NEXT: ret
%1 = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic
%2 = extractvalue { i8, i1 } %1, 0
ret i8 %2
@@ -3911,6 +5757,32 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(ptr %ptr, i8 signext %cmp, i8 sig
; RV32IA-NEXT: seqz a0, a1
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val1:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a3, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: li a4, 255
+; RV32I-ZALRSC-NEXT: zext.b a1, a1
+; RV32I-ZALRSC-NEXT: zext.b a2, a2
+; RV32I-ZALRSC-NEXT: sll a4, a4, a0
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sll a0, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a3)
+; RV32I-ZALRSC-NEXT: and a5, a2, a4
+; RV32I-ZALRSC-NEXT: bne a5, a1, .LBB48_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a5, a2, a0
+; RV32I-ZALRSC-NEXT: and a5, a5, a4
+; RV32I-ZALRSC-NEXT: xor a5, a2, a5
+; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a3)
+; RV32I-ZALRSC-NEXT: bnez a5, .LBB48_1
+; RV32I-ZALRSC-NEXT: .LBB48_3:
+; RV32I-ZALRSC-NEXT: and a2, a2, a4
+; RV32I-ZALRSC-NEXT: xor a1, a1, a2
+; RV32I-ZALRSC-NEXT: seqz a0, a1
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic_val1:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -3949,6 +5821,32 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(ptr %ptr, i8 signext %cmp, i8 sig
; RV64IA-NEXT: xor a1, a1, a2
; RV64IA-NEXT: seqz a0, a1
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val1:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a3, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: li a4, 255
+; RV64I-ZALRSC-NEXT: zext.b a1, a1
+; RV64I-ZALRSC-NEXT: zext.b a2, a2
+; RV64I-ZALRSC-NEXT: sllw a4, a4, a0
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sllw a0, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a3)
+; RV64I-ZALRSC-NEXT: and a5, a2, a4
+; RV64I-ZALRSC-NEXT: bne a5, a1, .LBB48_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a5, a2, a0
+; RV64I-ZALRSC-NEXT: and a5, a5, a4
+; RV64I-ZALRSC-NEXT: xor a5, a2, a5
+; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a3)
+; RV64I-ZALRSC-NEXT: bnez a5, .LBB48_1
+; RV64I-ZALRSC-NEXT: .LBB48_3:
+; RV64I-ZALRSC-NEXT: and a2, a2, a4
+; RV64I-ZALRSC-NEXT: xor a1, a1, a2
+; RV64I-ZALRSC-NEXT: seqz a0, a1
+; RV64I-ZALRSC-NEXT: ret
%1 = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic
%2 = extractvalue { i8, i1 } %1, 1
ret i1 %2
@@ -3996,6 +5894,33 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext %
; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val0:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a3, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a4, 16
+; RV32I-ZALRSC-NEXT: addi a4, a4, -1
+; RV32I-ZALRSC-NEXT: sll a5, a4, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a4
+; RV32I-ZALRSC-NEXT: and a2, a2, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sll a2, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a4, (a3)
+; RV32I-ZALRSC-NEXT: and a6, a4, a5
+; RV32I-ZALRSC-NEXT: bne a6, a1, .LBB49_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a6, a4, a2
+; RV32I-ZALRSC-NEXT: and a6, a6, a5
+; RV32I-ZALRSC-NEXT: xor a6, a4, a6
+; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a3)
+; RV32I-ZALRSC-NEXT: bnez a6, .LBB49_1
+; RV32I-ZALRSC-NEXT: .LBB49_3:
+; RV32I-ZALRSC-NEXT: srl a0, a4, a0
+; RV32I-ZALRSC-NEXT: slli a0, a0, 16
+; RV32I-ZALRSC-NEXT: srai a0, a0, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic_val0:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -4036,6 +5961,33 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext %
; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val0:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a3, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a4, 16
+; RV64I-ZALRSC-NEXT: addi a4, a4, -1
+; RV64I-ZALRSC-NEXT: sllw a5, a4, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a4
+; RV64I-ZALRSC-NEXT: and a2, a2, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sllw a2, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a4, (a3)
+; RV64I-ZALRSC-NEXT: and a6, a4, a5
+; RV64I-ZALRSC-NEXT: bne a6, a1, .LBB49_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a6, a4, a2
+; RV64I-ZALRSC-NEXT: and a6, a6, a5
+; RV64I-ZALRSC-NEXT: xor a6, a4, a6
+; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a3)
+; RV64I-ZALRSC-NEXT: bnez a6, .LBB49_1
+; RV64I-ZALRSC-NEXT: .LBB49_3:
+; RV64I-ZALRSC-NEXT: srlw a0, a4, a0
+; RV64I-ZALRSC-NEXT: slli a0, a0, 48
+; RV64I-ZALRSC-NEXT: srai a0, a0, 48
+; RV64I-ZALRSC-NEXT: ret
%1 = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic
%2 = extractvalue { i16, i1 } %1, 0
ret i16 %2
@@ -4082,6 +6034,33 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16
; RV32IA-NEXT: seqz a0, a1
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val1:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a3, a0, -4
+; RV32I-ZALRSC-NEXT: slli a0, a0, 3
+; RV32I-ZALRSC-NEXT: lui a4, 16
+; RV32I-ZALRSC-NEXT: addi a4, a4, -1
+; RV32I-ZALRSC-NEXT: sll a5, a4, a0
+; RV32I-ZALRSC-NEXT: and a1, a1, a4
+; RV32I-ZALRSC-NEXT: and a2, a2, a4
+; RV32I-ZALRSC-NEXT: sll a1, a1, a0
+; RV32I-ZALRSC-NEXT: sll a0, a2, a0
+; RV32I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a2, (a3)
+; RV32I-ZALRSC-NEXT: and a4, a2, a5
+; RV32I-ZALRSC-NEXT: bne a4, a1, .LBB50_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV32I-ZALRSC-NEXT: xor a4, a2, a0
+; RV32I-ZALRSC-NEXT: and a4, a4, a5
+; RV32I-ZALRSC-NEXT: xor a4, a2, a4
+; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a3)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB50_1
+; RV32I-ZALRSC-NEXT: .LBB50_3:
+; RV32I-ZALRSC-NEXT: and a2, a2, a5
+; RV32I-ZALRSC-NEXT: xor a1, a1, a2
+; RV32I-ZALRSC-NEXT: seqz a0, a1
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic_val1:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -4121,6 +6100,33 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16
; RV64IA-NEXT: xor a1, a1, a2
; RV64IA-NEXT: seqz a0, a1
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val1:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a3, a0, -4
+; RV64I-ZALRSC-NEXT: slli a0, a0, 3
+; RV64I-ZALRSC-NEXT: lui a4, 16
+; RV64I-ZALRSC-NEXT: addi a4, a4, -1
+; RV64I-ZALRSC-NEXT: sllw a5, a4, a0
+; RV64I-ZALRSC-NEXT: and a1, a1, a4
+; RV64I-ZALRSC-NEXT: and a2, a2, a4
+; RV64I-ZALRSC-NEXT: sllw a1, a1, a0
+; RV64I-ZALRSC-NEXT: sllw a0, a2, a0
+; RV64I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a2, (a3)
+; RV64I-ZALRSC-NEXT: and a4, a2, a5
+; RV64I-ZALRSC-NEXT: bne a4, a1, .LBB50_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV64I-ZALRSC-NEXT: xor a4, a2, a0
+; RV64I-ZALRSC-NEXT: and a4, a4, a5
+; RV64I-ZALRSC-NEXT: xor a4, a2, a4
+; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a3)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB50_1
+; RV64I-ZALRSC-NEXT: .LBB50_3:
+; RV64I-ZALRSC-NEXT: and a2, a2, a5
+; RV64I-ZALRSC-NEXT: xor a1, a1, a2
+; RV64I-ZALRSC-NEXT: seqz a0, a1
+; RV64I-ZALRSC-NEXT: ret
%1 = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic
%2 = extractvalue { i16, i1 } %1, 1
ret i1 %2
@@ -4159,6 +6165,18 @@ define signext i32 @cmpxchg_i32_monotonic_monotonic_val0(ptr %ptr, i32 signext %
; RV32IA-ZACAS-NEXT: mv a0, a1
; RV32IA-ZACAS-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val0:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a0)
+; RV32I-ZALRSC-NEXT: bne a3, a1, .LBB51_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a4, a2, (a0)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB51_1
+; RV32I-ZALRSC-NEXT: .LBB51_3:
+; RV32I-ZALRSC-NEXT: mv a0, a3
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic_val0:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -4190,6 +6208,18 @@ define signext i32 @cmpxchg_i32_monotonic_monotonic_val0(ptr %ptr, i32 signext %
; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-ZACAS-NEXT: mv a0, a1
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val0:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a0)
+; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB51_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a4, a2, (a0)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB51_1
+; RV64I-ZALRSC-NEXT: .LBB51_3:
+; RV64I-ZALRSC-NEXT: mv a0, a3
+; RV64I-ZALRSC-NEXT: ret
%1 = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic
%2 = extractvalue { i32, i1 } %1, 0
ret i32 %2
@@ -4230,6 +6260,19 @@ define i1 @cmpxchg_i32_monotonic_monotonic_val1(ptr %ptr, i32 signext %cmp, i32
; RV32IA-ZACAS-NEXT: seqz a0, a1
; RV32IA-ZACAS-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val1:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a3, (a0)
+; RV32I-ZALRSC-NEXT: bne a3, a1, .LBB52_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a4, a2, (a0)
+; RV32I-ZALRSC-NEXT: bnez a4, .LBB52_1
+; RV32I-ZALRSC-NEXT: .LBB52_3:
+; RV32I-ZALRSC-NEXT: xor a1, a3, a1
+; RV32I-ZALRSC-NEXT: seqz a0, a1
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic_val1:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -4263,6 +6306,19 @@ define i1 @cmpxchg_i32_monotonic_monotonic_val1(ptr %ptr, i32 signext %cmp, i32
; RV64IA-ZACAS-NEXT: xor a1, a3, a1
; RV64IA-ZACAS-NEXT: seqz a0, a1
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val1:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a3, (a0)
+; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB52_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a4, a2, (a0)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB52_1
+; RV64I-ZALRSC-NEXT: .LBB52_3:
+; RV64I-ZALRSC-NEXT: xor a1, a3, a1
+; RV64I-ZALRSC-NEXT: seqz a0, a1
+; RV64I-ZALRSC-NEXT: ret
%1 = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic
%2 = extractvalue { i32, i1 } %1, 1
ret i1 %2
@@ -4304,6 +6360,27 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB53_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB53_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB53_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB53_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xchg_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4339,6 +6416,28 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: li a2, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB53_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB53_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB53_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB53_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -4391,6 +6490,27 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB54_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB54_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: add a3, a0, a2
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB54_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB54_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: addi a2, a0, 1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_add_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4426,6 +6546,28 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: addi a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB54_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB54_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: add a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB54_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB54_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: addi a2, a1, 1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -4479,6 +6621,27 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB55_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB55_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: sub a3, a0, a2
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB55_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB55_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: addi a2, a0, -1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_sub_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4514,6 +6677,28 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: addi a2, a0, -1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB55_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB55_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: sub a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB55_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB55_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: addi a2, a1, -1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -4567,6 +6752,27 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB56_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB56_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: and a3, a0, a2
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB56_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB56_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: andi a2, a0, 1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_and_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4602,6 +6808,28 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: andi a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB56_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB56_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: and a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB56_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB56_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: andi a2, a1, 1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -4685,6 +6913,28 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-ZACAS-NEXT: mv a0, a1
; RV32IA-ZACAS-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB57_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB57_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: and a3, a0, a2
+; RV32I-ZALRSC-NEXT: not a3, a3
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB57_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB57_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: andi a2, a0, 1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_nand_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4750,6 +7000,28 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-ZACAS-NEXT: sw a2, 0(a0)
; RV64IA-ZACAS-NEXT: mv a0, a1
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a1, 1
+; RV64I-ZALRSC-NEXT: mv a1, a0
+; RV64I-ZALRSC-NEXT: beqz a2, .LBB57_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB57_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV64I-ZALRSC-NEXT: and a3, a0, a2
+; RV64I-ZALRSC-NEXT: not a3, a3
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB57_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB57_2: # %else
+; RV64I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV64I-ZALRSC-NEXT: andi a2, a0, 1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -4803,6 +7075,27 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind {
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB58_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB58_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: or a3, a0, a2
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB58_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB58_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: ori a2, a0, 1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_or_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4838,6 +7131,28 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind {
; RV64IA-NEXT: ori a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB58_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB58_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: or a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB58_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB58_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ori a2, a1, 1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -4891,6 +7206,27 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB59_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB59_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: xor a3, a0, a2
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB59_3
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB59_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: xori a2, a0, 1
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_xor_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a1, 1
@@ -4926,6 +7262,28 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: xori a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB59_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB59_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: xor a3, a1, a2
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB59_3
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB59_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: xori a2, a1, 1
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -5007,6 +7365,37 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB60_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB60_5: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: mv a3, a0
+; RV32I-ZALRSC-NEXT: bge a3, a2, .LBB60_7
+; RV32I-ZALRSC-NEXT: # %bb.6: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: .LBB60_7: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB60_5
+; RV32I-ZALRSC-NEXT: # %bb.8: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB60_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: mv a2, a0
+; RV32I-ZALRSC-NEXT: bgtz a0, .LBB60_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %else
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB60_4: # %else
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_max_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -5070,6 +7459,37 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: .LBB60_4: # %else
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a1, 1
+; RV64I-ZALRSC-NEXT: mv a1, a0
+; RV64I-ZALRSC-NEXT: beqz a2, .LBB60_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB60_5: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV64I-ZALRSC-NEXT: mv a3, a0
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB60_7
+; RV64I-ZALRSC-NEXT: # %bb.6: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB60_7: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB60_5
+; RV64I-ZALRSC-NEXT: # %bb.8: # %then
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB60_2: # %else
+; RV64I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV64I-ZALRSC-NEXT: mv a2, a0
+; RV64I-ZALRSC-NEXT: bgtz a0, .LBB60_4
+; RV64I-ZALRSC-NEXT: # %bb.3: # %else
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB60_4: # %else
+; RV64I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -5155,6 +7575,37 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB61_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB61_5: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: mv a3, a0
+; RV32I-ZALRSC-NEXT: bge a2, a3, .LBB61_7
+; RV32I-ZALRSC-NEXT: # %bb.6: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: .LBB61_7: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB61_5
+; RV32I-ZALRSC-NEXT: # %bb.8: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB61_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: mv a2, a0
+; RV32I-ZALRSC-NEXT: blez a0, .LBB61_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %else
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB61_4: # %else
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_min_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -5220,6 +7671,37 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: .LBB61_4: # %else
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a1, 1
+; RV64I-ZALRSC-NEXT: mv a1, a0
+; RV64I-ZALRSC-NEXT: beqz a2, .LBB61_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB61_5: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV64I-ZALRSC-NEXT: mv a3, a0
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB61_7
+; RV64I-ZALRSC-NEXT: # %bb.6: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB61_7: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB61_5
+; RV64I-ZALRSC-NEXT: # %bb.8: # %then
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB61_2: # %else
+; RV64I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV64I-ZALRSC-NEXT: mv a2, a0
+; RV64I-ZALRSC-NEXT: blez a0, .LBB61_4
+; RV64I-ZALRSC-NEXT: # %bb.3: # %else
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB61_4: # %else
+; RV64I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -5290,6 +7772,34 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB62_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB62_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: mv a3, a0
+; RV32I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: .LBB62_5: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB62_3
+; RV32I-ZALRSC-NEXT: # %bb.6: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB62_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: seqz a2, a0
+; RV32I-ZALRSC-NEXT: add a2, a0, a2
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -5347,6 +7857,36 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: add a2, a0, a2
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a1, a1, 1
+; RV64I-ZALRSC-NEXT: beqz a1, .LBB62_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB62_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
+; RV64I-ZALRSC-NEXT: slli a3, a1, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB62_5: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB62_3
+; RV64I-ZALRSC-NEXT: # %bb.6: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB62_2: # %else
+; RV64I-ZALRSC-NEXT: lw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: seqz a2, a1
+; RV64I-ZALRSC-NEXT: add a2, a1, a2
+; RV64I-ZALRSC-NEXT: sw a2, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a1
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -5434,6 +7974,38 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32IA-NEXT: sw a2, 0(a1)
; RV32IA-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: andi a2, a1, 1
+; RV32I-ZALRSC-NEXT: mv a1, a0
+; RV32I-ZALRSC-NEXT: beqz a2, .LBB63_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB63_5: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV32I-ZALRSC-NEXT: mv a3, a0
+; RV32I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7
+; RV32I-ZALRSC-NEXT: # %bb.6: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: .LBB63_7: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB63_5
+; RV32I-ZALRSC-NEXT: # %bb.8: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB63_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV32I-ZALRSC-NEXT: li a3, 1
+; RV32I-ZALRSC-NEXT: mv a2, a0
+; RV32I-ZALRSC-NEXT: bltu a0, a3, .LBB63_4
+; RV32I-ZALRSC-NEXT: # %bb.3: # %else
+; RV32I-ZALRSC-NEXT: li a2, 1
+; RV32I-ZALRSC-NEXT: .LBB63_4: # %else
+; RV32I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -5501,6 +8073,39 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: .LBB63_4: # %else
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: andi a2, a1, 1
+; RV64I-ZALRSC-NEXT: mv a1, a0
+; RV64I-ZALRSC-NEXT: beqz a2, .LBB63_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB63_5: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a0, (a1)
+; RV64I-ZALRSC-NEXT: slli a3, a0, 32
+; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7
+; RV64I-ZALRSC-NEXT: # %bb.6: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB63_7: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB63_5
+; RV64I-ZALRSC-NEXT: # %bb.8: # %then
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB63_2: # %else
+; RV64I-ZALRSC-NEXT: lw a0, 0(a1)
+; RV64I-ZALRSC-NEXT: li a3, 1
+; RV64I-ZALRSC-NEXT: mv a2, a0
+; RV64I-ZALRSC-NEXT: bltu a0, a3, .LBB63_4
+; RV64I-ZALRSC-NEXT: # %bb.3: # %else
+; RV64I-ZALRSC-NEXT: li a2, 1
+; RV64I-ZALRSC-NEXT: .LBB63_4: # %else
+; RV64I-ZALRSC-NEXT: sw a2, 0(a1)
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
@@ -5570,6 +8175,25 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3
; RV32IA-ZACAS-NEXT: lw a0, 0(a0)
; RV32IA-ZACAS-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_crossbb:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: mv a4, a0
+; RV32I-ZALRSC-NEXT: beqz a3, .LBB64_2
+; RV32I-ZALRSC-NEXT: # %bb.1: # %then
+; RV32I-ZALRSC-NEXT: .LBB64_3: # %then
+; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a0, (a4)
+; RV32I-ZALRSC-NEXT: bne a0, a1, .LBB64_5
+; RV32I-ZALRSC-NEXT: # %bb.4: # %then
+; RV32I-ZALRSC-NEXT: # in Loop: Header=BB64_3 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a2, (a4)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB64_3
+; RV32I-ZALRSC-NEXT: .LBB64_5: # %then
+; RV32I-ZALRSC-NEXT: ret
+; RV32I-ZALRSC-NEXT: .LBB64_2: # %else
+; RV32I-ZALRSC-NEXT: lw a0, 0(a4)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_monotonic_crossbb:
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a3, .LBB64_2
@@ -5620,6 +8244,26 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3
; RV64IA-ZACAS-NEXT: .LBB64_2: # %else
; RV64IA-ZACAS-NEXT: lw a0, 0(a0)
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_crossbb:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: beqz a3, .LBB64_2
+; RV64I-ZALRSC-NEXT: # %bb.1: # %then
+; RV64I-ZALRSC-NEXT: .LBB64_3: # %then
+; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a0)
+; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB64_5
+; RV64I-ZALRSC-NEXT: # %bb.4: # %then
+; RV64I-ZALRSC-NEXT: # in Loop: Header=BB64_3 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a4, a2, (a0)
+; RV64I-ZALRSC-NEXT: bnez a4, .LBB64_3
+; RV64I-ZALRSC-NEXT: .LBB64_5: # %then
+; RV64I-ZALRSC-NEXT: sext.w a0, a3
+; RV64I-ZALRSC-NEXT: ret
+; RV64I-ZALRSC-NEXT: .LBB64_2: # %else
+; RV64I-ZALRSC-NEXT: lw a3, 0(a0)
+; RV64I-ZALRSC-NEXT: sext.w a0, a3
+; RV64I-ZALRSC-NEXT: ret
br i1 %c, label %then, label %else
then:
>From 9725241328e4389e0583b6b001ea44ef3a470f6f Mon Sep 17 00:00:00 2001
From: Stephan Lachowsky <slachowsky at apple.com>
Date: Tue, 14 Oct 2025 11:25:57 -0700
Subject: [PATCH 2/3] [RISCV][clang] Enable atomics for 'Zalrsc', not just 'A'
'Zalrsc' only subtargets are atomics capable, ensure the RISCV target exposes
this correctly.
---
clang/lib/Basic/Targets/RISCV.cpp | 5 ++++-
clang/lib/Basic/Targets/RISCV.h | 6 ++++--
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 04da4e637af51..685925b0773dc 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -192,8 +192,11 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__riscv_muldiv");
}
- if (ISAInfo->hasExtension("a")) {
+ // The "a" extension is composed of "zalrsc" and "zaamo"
+ if (ISAInfo->hasExtension("a"))
Builder.defineMacro("__riscv_atomic");
+
+ if (ISAInfo->hasExtension("zalrsc")) {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index d8b0e64c90dd6..85fa4cc07dccf 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -195,7 +195,8 @@ class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
void setMaxAtomicWidth() override {
MaxAtomicPromoteWidth = 128;
- if (ISAInfo->hasExtension("a"))
+ // "a" implies "zalrsc" which is sufficient to inline atomics
+ if (ISAInfo->hasExtension("zalrsc"))
MaxAtomicInlineWidth = 32;
}
};
@@ -225,7 +226,8 @@ class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
void setMaxAtomicWidth() override {
MaxAtomicPromoteWidth = 128;
- if (ISAInfo->hasExtension("a"))
+ // "a" implies "zalrsc" which is sufficient to inline atomics
+ if (ISAInfo->hasExtension("zalrsc"))
MaxAtomicInlineWidth = 64;
}
};
>From d867abdfb899068c6f64a61c0ab1d851fe3fdbe6 Mon Sep 17 00:00:00 2001
From: Stephan Lachowsky <slachowsky at apple.com>
Date: Thu, 16 Oct 2025 01:35:47 -0700
Subject: [PATCH 3/3] [LegalizeTypes][RISCV] Control sign-extend for atomicrmw
input argument
Similar to the argument sign-extend control provided by
getExtendForAtomicCmpSwapArg for `cmpxchg`, this change adds
getExtendForAtomicRMWArg for `atomicrmw <op>`.
This mechanism is used to correct the RISCV code generation when using atomic
pseudo expansions that perform sub-word comparions inside a LR/SC block, and
expect a correctly sign-extended input argument. A shorter instruction
sequence is possible for umin/max by leveraging the fact that two sign-extended
arguments still order correctly during an unsigned comparison.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 6 +
.../SelectionDAG/LegalizeIntegerTypes.cpp | 15 +-
.../RISCV/RISCVExpandAtomicPseudoInsts.cpp | 23 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 19 ++
llvm/lib/Target/RISCV/RISCVISelLowering.h | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 4 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 230 +++++++++---------
llvm/test/CodeGen/RISCV/atomic-signext.ll | 52 ++--
8 files changed, 190 insertions(+), 160 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 73f2c55a71125..64a7563182a98 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2459,6 +2459,12 @@ class LLVM_ABI TargetLoweringBase {
return ISD::ANY_EXTEND;
}
+ /// Returns how the platform's atomic rmw operations expect their input
+ /// argument to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
+ virtual ISD::NodeType getExtendForAtomicRMWArg(unsigned Op) const {
+ return ISD::ANY_EXTEND;
+ }
+
/// @}
/// Returns true if we should normalize
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 88a4a8b16373b..b1776eaae6e86 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -429,7 +429,20 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
- SDValue Op2 = GetPromotedInteger(N->getOperand(2));
+ SDValue Op2 = N->getOperand(2);
+ switch (TLI.getExtendForAtomicRMWArg(N->getOpcode())) {
+ case ISD::SIGN_EXTEND:
+ Op2 = SExtPromotedInteger(Op2);
+ break;
+ case ISD::ZERO_EXTEND:
+ Op2 = ZExtPromotedInteger(Op2);
+ break;
+ case ISD::ANY_EXTEND:
+ Op2 = GetPromotedInteger(Op2);
+ break;
+ default:
+ llvm_unreachable("Invalid atomic op extension");
+ }
SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
N->getMemoryVT(),
N->getChain(), N->getBasePtr(),
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index 31b9bf9c15b69..c703d80db44f7 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -523,17 +523,6 @@ static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
.addReg(ShamtReg);
}
-static void insertZext(const RISCVInstrInfo *TII, DebugLoc DL,
- MachineBasicBlock *MBB, Register ValReg,
- Register SrcReg, int64_t Shamt) {
- BuildMI(MBB, DL, TII->get(RISCV::SLLI), ValReg)
- .addReg(SrcReg)
- .addImm(Shamt);
- BuildMI(MBB, DL, TII->get(RISCV::SRLI), ValReg)
- .addReg(ValReg)
- .addImm(Shamt);
-}
-
static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
DebugLoc DL, MachineBasicBlock *ThisMBB,
MachineBasicBlock *LoopHeadMBB,
@@ -546,9 +535,6 @@ static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &M
Register ScratchReg = MI.getOperand(1).getReg();
Register AddrReg = MI.getOperand(2).getReg();
Register IncrReg = MI.getOperand(3).getReg();
- bool IsUnsigned = BinOp == AtomicRMWInst::UMin ||
- BinOp == AtomicRMWInst::UMax;
- bool Zext = IsUnsigned && STI->is64Bit() && Width == 32;
AtomicOrdering Ordering =
static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
@@ -558,12 +544,9 @@ static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &M
// ifnochangeneeded scratch, incr, .looptail
BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg)
.addReg(AddrReg);
- if (Zext)
- insertZext(TII, DL, LoopHeadMBB, ScratchReg, DestReg, 32);
- else
- BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
- .addReg(DestReg)
- .addImm(0);
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
+ .addReg(DestReg)
+ .addImm(0);
switch (BinOp) {
default:
llvm_unreachable("Unexpected AtomicRMW BinOp");
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1e1b4b785059f..060a297cbb920 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -24483,6 +24483,25 @@ ISD::NodeType RISCVTargetLowering::getExtendForAtomicCmpSwapArg() const {
return Subtarget.hasStdExtZacas() ? ISD::ANY_EXTEND : ISD::SIGN_EXTEND;
}
+ISD::NodeType RISCVTargetLowering::getExtendForAtomicRMWArg(unsigned Op) const {
+ // Zaamo will use amo<op>.w which does not require extension.
+ if (Subtarget.hasStdExtZaamo() || Subtarget.hasForcedAtomics())
+ return ISD::ANY_EXTEND;
+
+ // Zalrsc pseudo expansions with comparison require sign-extension.
+ assert(Subtarget.hasStdExtZalrsc());
+ switch (Op) {
+ case ISD::ATOMIC_LOAD_MIN:
+ case ISD::ATOMIC_LOAD_MAX:
+ case ISD::ATOMIC_LOAD_UMIN:
+ case ISD::ATOMIC_LOAD_UMAX:
+ return ISD::SIGN_EXTEND;
+ default:
+ break;
+ }
+ return ISD::ANY_EXTEND;
+}
+
Register RISCVTargetLowering::getExceptionPointerRegister(
const Constant *PersonalityFn) const {
return RISCV::X10;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 3f81ed74c12ed..9e3e2a9443625 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -245,6 +245,7 @@ class RISCVTargetLowering : public TargetLowering {
}
ISD::NodeType getExtendForAtomicCmpSwapArg() const override;
+ ISD::NodeType getExtendForAtomicRMWArg(unsigned Op) const override;
bool shouldTransformSignedTruncationCheck(EVT XVT,
unsigned KeptBits) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 8b88b2ab89941..6d1040c761736 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -321,11 +321,9 @@ def PseudoAtomicLoadXor32 : PseudoAMO;
let Size = 24 in {
def PseudoAtomicLoadMax32 : PseudoAMO;
def PseudoAtomicLoadMin32 : PseudoAMO;
-} // Size = 24
-let Size = 28 in {
def PseudoAtomicLoadUMax32 : PseudoAMO;
def PseudoAtomicLoadUMin32 : PseudoAMO;
-} // Size = 28
+} // Size = 24
defm : PseudoAMOPat<"atomic_swap_i32", PseudoAtomicSwap32>;
defm : PseudoAMOPat<"atomic_load_add_i32", PseudoAtomicLoadAdd32>;
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index b1e4645c0d27f..26feb8325dec0 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -34893,17 +34893,18 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB165_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB165_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB165_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB165_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB165_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB165_3: # in Loop: Header=BB165_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB165_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
@@ -35017,17 +35018,18 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acquire:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB166_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB166_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB166_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB166_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB166_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB166_3: # in Loop: Header=BB166_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB166_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_acquire:
@@ -35146,17 +35148,18 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_release:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB167_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB167_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB167_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB167_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB167_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB167_3: # in Loop: Header=BB167_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB167_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_release:
@@ -35275,17 +35278,18 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB168_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB168_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB168_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB168_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB168_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB168_3: # in Loop: Header=BB168_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB168_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_acq_rel:
@@ -35404,17 +35408,18 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB169_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB169_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB169_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB169_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB169_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB169_3: # in Loop: Header=BB169_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB169_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_max_i32_seq_cst:
@@ -35528,17 +35533,18 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB170_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB170_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB170_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB170_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB170_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB170_3: # in Loop: Header=BB170_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB170_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
@@ -35652,17 +35658,18 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acquire:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB171_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB171_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB171_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB171_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB171_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB171_3: # in Loop: Header=BB171_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB171_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_acquire:
@@ -35781,17 +35788,18 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_release:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB172_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB172_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB172_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB172_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB172_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB172_3: # in Loop: Header=BB172_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB172_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_release:
@@ -35910,17 +35918,18 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB173_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB173_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB173_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB173_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB173_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB173_3: # in Loop: Header=BB173_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB173_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_acq_rel:
@@ -36039,17 +36048,18 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB174_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB174_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB174_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB174_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB174_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB174_3: # in Loop: Header=BB174_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB174_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_min_i32_seq_cst:
@@ -36163,18 +36173,18 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB175_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB175_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB175_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB175_3: # in Loop: Header=BB175_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB175_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
@@ -36288,18 +36298,18 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB176_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB176_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB176_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB176_3: # in Loop: Header=BB176_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB176_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acquire:
@@ -36418,18 +36428,18 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_release:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB177_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB177_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB177_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB177_3: # in Loop: Header=BB177_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB177_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_release:
@@ -36548,18 +36558,18 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB178_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB178_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB178_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB178_3: # in Loop: Header=BB178_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB178_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel:
@@ -36678,18 +36688,18 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB179_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB179_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB179_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB179_3: # in Loop: Header=BB179_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB179_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst:
@@ -36803,18 +36813,18 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB180_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB180_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB180_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB180_3: # in Loop: Header=BB180_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB180_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
@@ -36928,18 +36938,18 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB181_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB181_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB181_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB181_3: # in Loop: Header=BB181_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB181_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acquire:
@@ -37058,18 +37068,18 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_release:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB182_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB182_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB182_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB182_3: # in Loop: Header=BB182_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB182_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_release:
@@ -37188,18 +37198,18 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB183_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB183_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB183_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB183_3: # in Loop: Header=BB183_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB183_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel:
@@ -37318,18 +37328,18 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB184_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB184_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB184_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB184_3: # in Loop: Header=BB184_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB184_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
;
; RV64IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst:
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index 4b49271735492..7fe5fa7365eb5 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -3874,17 +3874,18 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB32_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB32_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB32_3: # in Loop: Header=BB32_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB32_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b monotonic
ret i32 %1
@@ -3993,17 +3994,18 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: mv a3, a2
-; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB33_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB33_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB33_3: # in Loop: Header=BB33_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB33_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b monotonic
ret i32 %1
@@ -4112,18 +4114,18 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB34_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB34_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB34_3: # in Loop: Header=BB34_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB34_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b monotonic
ret i32 %1
@@ -4232,18 +4234,18 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
; RV64I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
-; RV64I-ZALRSC-NEXT: lr.w a2, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a2, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
-; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB35_3
-; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
+; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB35_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
; RV64I-ZALRSC-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0)
; RV64I-ZALRSC-NEXT: bnez a3, .LBB35_1
; RV64I-ZALRSC-NEXT: # %bb.4:
-; RV64I-ZALRSC-NEXT: mv a0, a2
+; RV64I-ZALRSC-NEXT: mv a0, a1
; RV64I-ZALRSC-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b monotonic
ret i32 %1
@@ -7867,8 +7869,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-ZALRSC-NEXT: .LBB62_3: # %then
; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
-; RV64I-ZALRSC-NEXT: slli a3, a1, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: mv a3, a1
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5
; RV64I-ZALRSC-NEXT: # %bb.4: # %then
; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1
@@ -8084,8 +8085,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-ZALRSC-NEXT: .LBB63_5: # %then
; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-ZALRSC-NEXT: lr.w a0, (a1)
-; RV64I-ZALRSC-NEXT: slli a3, a0, 32
-; RV64I-ZALRSC-NEXT: srli a3, a3, 32
+; RV64I-ZALRSC-NEXT: mv a3, a0
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7
; RV64I-ZALRSC-NEXT: # %bb.6: # %then
; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1
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