[clang] [llvm] Add backend support for Kernel Control-Flow Integrity (PR #163698)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- clang/lib/CodeGen/BackendUtil.cpp llvm/lib/Target/ARM/ARMAsmPrinter.cpp llvm/lib/Target/ARM/ARMAsmPrinter.h llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.h llvm/lib/Target/ARM/ARMTargetMachine.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 295a24792..e028d726e 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1509,23 +1509,21 @@ void ARMAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
   // If we need to spill r3, push it first.
   if (NeedSpillR3) {
     // push {r3}
-    EmitToStreamer(*OutStreamer,
-      MCInstBuilder(ARM::STMDB_UPD)
-        .addReg(ARM::SP)
-        .addReg(ARM::SP)
-        .addImm(ARMCC::AL)
-        .addReg(0)
-        .addReg(ARM::R3));
+    EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STMDB_UPD)
+                                     .addReg(ARM::SP)
+                                     .addReg(ARM::SP)
+                                     .addImm(ARMCC::AL)
+                                     .addReg(0)
+                                     .addReg(ARM::R3));
   }
 
   // ldr scratch, [target, #-(PrefixNops * 4 + 4)]
-  EmitToStreamer(*OutStreamer,
-    MCInstBuilder(ARM::LDRi12)
-      .addReg(ScratchReg)
-      .addReg(AddrReg)
-      .addImm(-(PrefixNops * 4 + 4))
-      .addImm(ARMCC::AL)
-      .addReg(0));
+  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
+                                   .addReg(ScratchReg)
+                                   .addReg(AddrReg)
+                                   .addImm(-(PrefixNops * 4 + 4))
+                                   .addImm(ARMCC::AL)
+                                   .addReg(0));
 
   // Each EOR instruction XORs one byte of the type, shifted to its position.
   for (int i = 0; i < 4; i++) {
@@ -1535,53 +1533,49 @@ void ARMAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
 
     // Encode as ARM modified immediate.
     int SOImmVal = ARM_AM::getSOImmVal(imm);
-    assert(SOImmVal != -1 && "Cannot encode immediate as ARM modified immediate");
+    assert(SOImmVal != -1 &&
+           "Cannot encode immediate as ARM modified immediate");
 
     // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
-    EmitToStreamer(*OutStreamer,
-      MCInstBuilder(ARM::EORri)
-        .addReg(ScratchReg)
-        .addReg(ScratchReg)
-        .addImm(SOImmVal)
-        .addImm(ARMCC::AL)
-        .addReg(0)
-        .addReg(isLast ? ARM::CPSR : 0));
+    EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::EORri)
+                                     .addReg(ScratchReg)
+                                     .addReg(ScratchReg)
+                                     .addImm(SOImmVal)
+                                     .addImm(ARMCC::AL)
+                                     .addReg(0)
+                                     .addReg(isLast ? ARM::CPSR : 0));
   }
 
   // If we spilled r3, restore it immediately after the comparison.
   // This must happen before the branch so r3 is valid on both paths.
   if (NeedSpillR3) {
     // pop {r3}
-    EmitToStreamer(*OutStreamer,
-      MCInstBuilder(ARM::LDMIA_UPD)
-        .addReg(ARM::SP)
-        .addReg(ARM::SP)
-        .addImm(ARMCC::AL)
-        .addReg(0)
-        .addReg(ARM::R3));
+    EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDMIA_UPD)
+                                     .addReg(ARM::SP)
+                                     .addReg(ARM::SP)
+                                     .addImm(ARMCC::AL)
+                                     .addReg(0)
+                                     .addReg(ARM::R3));
   }
 
   // beq .Lpass (branch if types match, i.e., scratch is zero)
   MCSymbol *Pass = OutContext.createTempSymbol();
   EmitToStreamer(*OutStreamer,
-    MCInstBuilder(ARM::Bcc)
-      .addExpr(MCSymbolRefExpr::create(Pass, OutContext))
-      .addImm(ARMCC::EQ)
-      .addReg(ARM::CPSR));
+                 MCInstBuilder(ARM::Bcc)
+                     .addExpr(MCSymbolRefExpr::create(Pass, OutContext))
+                     .addImm(ARMCC::EQ)
+                     .addReg(ARM::CPSR));
 
   // udf #ESR (trap with encoded diagnostic)
   // ESR encoding: 0x8000 | (scratch_reg << 5) | addr_reg.
   // Note: scratch_reg is always 0x1F since the EOR sequence clobbers it
   // and it contains no useful information at trap time.
-  const ARMBaseRegisterInfo *TRI =
-      static_cast<const ARMBaseRegisterInfo *>(
-          MI.getMF()->getSubtarget().getRegisterInfo());
+  const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
+      MI.getMF()->getSubtarget().getRegisterInfo());
   unsigned AddrIndex = TRI->getEncodingValue(AddrReg);
   unsigned ESR = 0x8000 | (31 << 5) | (AddrIndex & 31);
 
-  EmitToStreamer(*OutStreamer,
-    MCInstBuilder(ARM::UDF)
-      .addImm(ESR));
+  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::UDF).addImm(ESR));
 
   OutStreamer->emitLabel(Pass);
 }

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https://github.com/llvm/llvm-project/pull/163698