[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

[Craig Topper via cfe-commits]

================
@@ -285,6 +378,34 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
         .addReg(ScratchReg)
         .addImm(-1);
     break;
+  case AtomicRMWInst::Min:
+    BuildMI(LoopMBB, DL, TII->get(RISCV::MIN), ScratchReg)
+        .addReg(DestReg)
+        .addReg(IncrReg);
+    break;
+  case AtomicRMWInst::Max:
+    BuildMI(LoopMBB, DL, TII->get(RISCV::MAX), ScratchReg)
+        .addReg(DestReg)
+        .addReg(IncrReg);
+    break;
+  case AtomicRMWInst::UMin:
+    if (Zext)
+      BuildMI(LoopMBB, DL, TII->get(RISCV::ADD_UW), ScratchReg)
----------------
topperc wrote:

ADD_UW belong to Zba not Zbb which I don't think you checked for.

add.uw, min(u), max(u), aren't allowed to be in an LR/SC loop by my reading of the ISA manual

"The dynamic
code executed between the LR and SC instructions can only contain instructions from the base ''I''
instruction set, excluding loads, stores, backward jumps, taken backward branches, JALR, FENCE,
and SYSTEM instructions. If the ''C'' extension is supported, then compressed forms of the
aforementioned ''I'' instructions are also permitted."



https://github.com/llvm/llvm-project/pull/163672