[clang] [llvm] [RegisterCoalescer] Improve register allocation for return values by limiting rematerialization (PR #163047)
guan jian via cfe-commits
cfe-commits at lists.llvm.org
Tue Oct 14 19:32:03 PDT 2025
https://github.com/rez5427 updated https://github.com/llvm/llvm-project/pull/163047
>From 269cb630965fcc5283bd0484f8dd71ff83c38fa2 Mon Sep 17 00:00:00 2001
From: rez5427 <guanjian at stu.cdut.edu.cn>
Date: Sun, 12 Oct 2025 00:55:37 +0800
Subject: [PATCH 1/4] [RegisterCoalescer] Improve register allocation for
return values by limiting rematerialization
---
llvm/lib/CodeGen/RegisterCoalescer.cpp | 34 ++++
.../CodeGen/AArch64/aarch64_win64cc_vararg.ll | 9 +-
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 2 +
llvm/test/CodeGen/AArch64/arm64-vector-ext.ll | 23 ++-
llvm/test/CodeGen/AArch64/arm64-vshuffle.ll | 13 +-
llvm/test/CodeGen/AArch64/bitcast.ll | 2 +
llvm/test/CodeGen/AArch64/combine-mul.ll | 2 +
llvm/test/CodeGen/AArch64/ext-narrow-index.ll | 3 +
.../CodeGen/AArch64/fast-isel-const-float.ll | 1 +
llvm/test/CodeGen/AArch64/movi64_sve.ll | 12 ++
llvm/test/CodeGen/AArch64/neon-abd.ll | 1 +
.../AArch64/neon-compare-instructions.ll | 2 +
llvm/test/CodeGen/AArch64/neon-mov.ll | 3 +
.../CodeGen/AArch64/remat-const-float-simd.ll | 1 +
.../AArch64/sve-implicit-zero-filling.ll | 2 +-
...ing-mode-fixed-length-insert-vector-elt.ll | 1 +
.../sve-streaming-mode-test-register-mov.ll | 2 +
llvm/test/CodeGen/AArch64/win64_vararg.ll | 9 +-
llvm/test/CodeGen/RISCV/float-imm.ll | 1 +
llvm/test/CodeGen/RISCV/half-imm.ll | 2 +
llvm/test/CodeGen/RISCV/ret-remat.ll | 16 ++
llvm/test/CodeGen/RISCV/zfhmin-imm.ll | 4 +
.../CodeGen/X86/2006-04-27-ISelFoldingBug.ll | 1 +
.../test/CodeGen/X86/2007-02-16-BranchFold.ll | 1 +
.../X86/2007-10-12-CoalesceExtSubReg.ll | 1 +
.../CodeGen/X86/2007-10-12-SpillerUnfold2.ll | 1 +
.../CodeGen/X86/2007-10-29-ExtendSetCC.ll | 1 +
llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll | 1 +
llvm/test/CodeGen/X86/add.ll | 6 +
llvm/test/CodeGen/X86/addcarry.ll | 3 +-
llvm/test/CodeGen/X86/all-ones-vector.ll | 76 +++----
llvm/test/CodeGen/X86/apx/ccmp.ll | 10 +
llvm/test/CodeGen/X86/apx/ctest.ll | 10 +
llvm/test/CodeGen/X86/apx/imulzu.ll | 1 +
llvm/test/CodeGen/X86/atomic-unordered.ll | 39 ++--
llvm/test/CodeGen/X86/bfloat.ll | 8 +-
.../test/CodeGen/X86/cet_endbr_imm_enhance.ll | 6 +-
llvm/test/CodeGen/X86/cmp.ll | 1 +
.../X86/coalescer-implicit-def-regression.ll | 12 +-
llvm/test/CodeGen/X86/combine-mulo.ll | 1 +
llvm/test/CodeGen/X86/combine-shl.ll | 2 +-
llvm/test/CodeGen/X86/combine-srem.ll | 1 +
llvm/test/CodeGen/X86/combine-subo.ll | 5 +-
llvm/test/CodeGen/X86/combine-urem.ll | 1 +
llvm/test/CodeGen/X86/divmod128.ll | 32 +--
llvm/test/CodeGen/X86/fast-isel-fcmp.ll | 3 +
llvm/test/CodeGen/X86/fast-isel-load-i1.ll | 1 +
...st-and-by-const-from-lshr-in-eqcmp-zero.ll | 1 +
llvm/test/CodeGen/X86/i128-immediate.ll | 2 +-
llvm/test/CodeGen/X86/int-to-fp-demanded.ll | 3 +-
llvm/test/CodeGen/X86/is_fpclass.ll | 2 +
llvm/test/CodeGen/X86/isel-fpclass.ll | 11 +
llvm/test/CodeGen/X86/knownbits-div.ll | 2 +
.../X86/lack-of-signed-truncation-check.ll | 1 +
llvm/test/CodeGen/X86/memcmp-constant.ll | 4 +
.../CodeGen/X86/memcmp-more-load-pairs-x32.ll | 1 +
.../CodeGen/X86/memcmp-more-load-pairs.ll | 1 +
llvm/test/CodeGen/X86/memcmp-x32.ll | 1 +
llvm/test/CodeGen/X86/memcmp.ll | 1 +
llvm/test/CodeGen/X86/negate.ll | 1 +
llvm/test/CodeGen/X86/oddshuffles.ll | 10 +-
llvm/test/CodeGen/X86/oddsubvector.ll | 9 +-
llvm/test/CodeGen/X86/overflow.ll | 2 +-
.../X86/peephole-na-phys-copy-folding.ll | 8 +
llvm/test/CodeGen/X86/pmulh.ll | 2 +-
llvm/test/CodeGen/X86/pr108728.ll | 1 +
llvm/test/CodeGen/X86/pr132844.ll | 10 +-
.../CodeGen/X86/shuffle-combine-crash-2.ll | 4 +-
.../CodeGen/X86/shuffle-combine-crash-3.ll | 1 +
llvm/test/CodeGen/X86/smul-with-overflow.ll | 20 +-
llvm/test/CodeGen/X86/sub-with-overflow.ll | 2 +
llvm/test/CodeGen/X86/subcarry.ll | 3 +-
llvm/test/CodeGen/X86/subreg-to-reg-6.ll | 2 +-
llvm/test/CodeGen/X86/tail-opts.ll | 1 +
llvm/test/CodeGen/X86/tailcall-cgp-dup.ll | 1 +
llvm/test/CodeGen/X86/trunc-to-bool.ll | 1 +
llvm/test/CodeGen/X86/umul-with-carry.ll | 1 +
llvm/test/CodeGen/X86/vec_minmax_sint.ll | 4 +-
llvm/test/CodeGen/X86/vec_minmax_uint.ll | 4 +-
llvm/test/CodeGen/X86/vec_umulo.ll | 8 +-
llvm/test/CodeGen/X86/vector-partial-undef.ll | 4 +-
llvm/test/CodeGen/X86/vector-shift-lut.ll | 192 +++++++++---------
llvm/test/CodeGen/X86/vectorcall.ll | 83 +-------
llvm/test/CodeGen/X86/xaluo.ll | 12 ++
llvm/test/CodeGen/X86/xmulo.ll | 50 +++--
llvm/test/DebugInfo/MIR/X86/regcoalescer.mir | 11 +-
llvm/test/Other/machine-size-remarks.ll | 7 +-
87 files changed, 497 insertions(+), 356 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/ret-remat.ll
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index ebfea8e5581bf..97d16f89a9da3 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1326,6 +1326,40 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
if (!TII->isAsCheapAsAMove(*DefMI))
return false;
+ // Skip rematerialization for physical registers used as return values within
+ // the same basic block to enable better coalescing.
+ if (DstReg.isPhysical()) {
+ MachineBasicBlock *MBB = CopyMI->getParent();
+ if (DefMI->getParent() == MBB) {
+ // Check if there's already an identical instruction before CopyMI
+ // If so, allow rematerialization to avoid redundant instructions
+ bool FoundCopy = false;
+ for (MachineInstr &MI : *MBB) {
+ if (&MI == CopyMI) {
+ FoundCopy = true;
+ continue;
+ }
+
+ // Before CopyMI: check for duplicate instructions
+ if (!FoundCopy && &MI != DefMI &&
+ MI.isIdenticalTo(*DefMI, MachineInstr::IgnoreDefs)) {
+ break; // Found duplicate, allow rematerialization
+ } else if (FoundCopy) {
+ // After CopyMI: check if used as return register
+ // If the register is redefined, it's not a return register
+ if (MI.modifiesRegister(DstReg, TRI))
+ break;
+ // If there's a return instruction that uses this register, skip remat
+ if (MI.isReturn() && MI.readsRegister(DstReg, TRI)) {
+ LLVM_DEBUG(dbgs() << "\tSkip remat for return register: "
+ << printReg(DstReg, TRI) << '\n');
+ return false;
+ }
+ }
+ }
+ }
+ }
+
if (!TII->isReMaterializable(*DefMI))
return false;
diff --git a/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll b/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
index 7d488c9ca2002..ea268ed83f3de 100644
--- a/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
@@ -52,9 +52,8 @@ define win64cc ptr @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64
; CHECK-LABEL: f9:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x0, sp, #24
-; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
;
@@ -78,9 +77,8 @@ define win64cc ptr @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64
; CHECK-LABEL: f8:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: add x8, sp, #16
; CHECK-NEXT: add x0, sp, #16
-; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
;
@@ -104,10 +102,9 @@ define win64cc ptr @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64
; CHECK-LABEL: f7:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x18, [sp, #-32]! // 8-byte Folded Spill
-; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: str x7, [sp, #24]
-; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: ldr x18, [sp], #32 // 8-byte Folded Reload
; CHECK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index e18a5f695ba29..98c3071de3ae8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -2156,6 +2156,7 @@ define <4 x i16> @concat_vector_v4i16_const() {
; CHECK-LABEL: concat_vector_v4i16_const:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %r
@@ -2183,6 +2184,7 @@ define <8 x i8> @concat_vector_v8i8_const() {
; CHECK-LABEL: concat_vector_v8i8_const:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer
ret <8 x i8> %r
diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
index 197a385b0e7cb..91f0fbcd5c46b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
@@ -1,15 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
-;CHECK: @func30
-;CHECK: movi.4h v1, #1
-;CHECK: and.8b v0, v0, v1
-;CHECK: ushll.4s v0, v0, #0
-;CHECK: str q0, [x0]
-;CHECK: ret
-
%T0_30 = type <4 x i1>
%T1_30 = type <4 x i32>
define void @func30(%T0_30 %v0, ptr %p1) {
+; CHECK-LABEL: func30:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi.4h v1, #1
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
%r = zext %T0_30 %v0 to %T1_30
store %T1_30 %r, ptr %p1
ret void
@@ -18,9 +19,11 @@ define void @func30(%T0_30 %v0, ptr %p1) {
; Extend from v1i1 was crashing things (PR20791). Make sure we do something
; sensible instead.
define <1 x i32> @autogen_SD7918() {
-; CHECK-LABEL: autogen_SD7918
-; CHECK: movi.2d v0, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK-LABEL: autogen_SD7918:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi.2d v0, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
%ZE = zext <1 x i1> %I29 to <1 x i32>
ret <1 x i32> %ZE
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
index b225d9a1acaf5..fd0f2433f2c2b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
@@ -1,9 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
define <8 x i1> @test1() {
; CHECK-LABEL: test1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.16b v0, #0
+; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
@@ -58,9 +60,14 @@ bb:
; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0
define <16 x i1> @test4(ptr %ptr, i32 %v) {
-; CHECK-LABEL: _test4:
-; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0 at PAGE
-; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0 at PAGEOFF]
+; CHECK-LABEL: test4:
+; CHECK: ; %bb.0: ; %bb
+; CHECK-NEXT: Lloh0:
+; CHECK-NEXT: adrp x8, lCPI3_0 at PAGE
+; CHECK-NEXT: Lloh1:
+; CHECK-NEXT: ldr q0, [x8, lCPI3_0 at PAGEOFF]
+; CHECK-NEXT: ret
+; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
bb:
%Shuff = shufflevector <16 x i1> zeroinitializer,
<16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index 20f19fddf790a..d462d2269f6bc 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -8,6 +8,7 @@ define <4 x i16> @foo1(<2 x i32> %a) {
; CHECK-SD-LABEL: foo1:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: foo1:
@@ -28,6 +29,7 @@ define <4 x i16> @foo2(<2 x i32> %a) {
; CHECK-SD-LABEL: foo2:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: foo2:
diff --git a/llvm/test/CodeGen/AArch64/combine-mul.ll b/llvm/test/CodeGen/AArch64/combine-mul.ll
index ff6d1a571a084..5d65b21f902b7 100644
--- a/llvm/test/CodeGen/AArch64/combine-mul.ll
+++ b/llvm/test/CodeGen/AArch64/combine-mul.ll
@@ -18,6 +18,7 @@ define <4 x i1> @PR48683_vec(<4 x i32> %x) {
; CHECK-LABEL: PR48683_vec:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%a = mul <4 x i32> %x, %x
%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>
@@ -29,6 +30,7 @@ define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {
; CHECK-LABEL: PR48683_vec_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%a = mul <4 x i32> %x, %x
%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>
diff --git a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
index f62cfef9baf28..017971df99d6e 100644
--- a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
+++ b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
@@ -251,6 +251,7 @@ define <8 x i8> @i8_zero_off22(<16 x i8> %arg1) {
; CHECK-SD-LABEL: i8_zero_off22:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GISEL-LABEL: i8_zero_off22:
@@ -302,6 +303,7 @@ define <4 x i16> @i16_zero_off8(<8 x i16> %arg1) {
; CHECK-LABEL: i16_zero_off8:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
@@ -346,6 +348,7 @@ define <2 x i32> @i32_zero_off4(<4 x i32> %arg1) {
; CHECK-LABEL: i32_zero_off4:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> <i32 4, i32 5>
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
index 4de2c934a672e..fbb71ba1c295f 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
@@ -9,6 +9,7 @@ define float @select_fp_const() {
; GISEL-LABEL: select_fp_const:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: movi v0.2s, #79, lsl #24
+; GISEL-NEXT: // kill: def $s0 killed $s0 killed $d0
; GISEL-NEXT: ret
;
; FISEL-LABEL: select_fp_const:
diff --git a/llvm/test/CodeGen/AArch64/movi64_sve.ll b/llvm/test/CodeGen/AArch64/movi64_sve.ll
index 1d4e00d0c3d10..3253b35d77470 100644
--- a/llvm/test/CodeGen/AArch64/movi64_sve.ll
+++ b/llvm/test/CodeGen/AArch64/movi64_sve.ll
@@ -12,6 +12,7 @@ define <2 x i64> @movi_1_v2i64() {
; SVE-LABEL: movi_1_v2i64:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #1 // =0x1
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <2 x i64> splat (i64 1)
}
@@ -26,6 +27,7 @@ define <2 x i64> @movi_127_v2i64() {
; SVE-LABEL: movi_127_v2i64:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #127 // =0x7f
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <2 x i64> splat (i64 127)
}
@@ -40,6 +42,7 @@ define <2 x i64> @movi_m128_v2i64() {
; SVE-LABEL: movi_m128_v2i64:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #-128 // =0xffffffffffffff80
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <2 x i64> splat (i64 -128)
}
@@ -54,6 +57,7 @@ define <2 x i64> @movi_256_v2i64() {
; SVE-LABEL: movi_256_v2i64:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #256 // =0x100
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <2 x i64> splat (i64 256)
}
@@ -68,6 +72,7 @@ define <2 x i64> @movi_32512_v2i64() {
; SVE-LABEL: movi_32512_v2i64:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #32512 // =0x7f00
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <2 x i64> splat (i64 32512)
}
@@ -82,6 +87,7 @@ define <2 x i64> @movi_m32768_v2i64() {
; SVE-LABEL: movi_m32768_v2i64:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #-32768 // =0xffffffffffff8000
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <2 x i64> splat (i64 -32768)
}
@@ -98,6 +104,7 @@ define <4 x i32> @movi_v4i32_1() {
; SVE-LABEL: movi_v4i32_1:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #127 // =0x7f
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <4 x i32> <i32 127, i32 0, i32 127, i32 0>
}
@@ -112,6 +119,7 @@ define <4 x i32> @movi_v4i32_2() {
; SVE-LABEL: movi_v4i32_2:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #32512 // =0x7f00
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <4 x i32> <i32 32512, i32 0, i32 32512, i32 0>
}
@@ -126,6 +134,7 @@ define <8 x i16> @movi_v8i16_1() {
; SVE-LABEL: movi_v8i16_1:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #127 // =0x7f
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <8 x i16> <i16 127, i16 0, i16 0, i16 0, i16 127, i16 0, i16 0, i16 0>
}
@@ -140,6 +149,7 @@ define <8 x i16> @movi_v8i16_2() {
; SVE-LABEL: movi_v8i16_2:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #32512 // =0x7f00
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <8 x i16> <i16 32512, i16 0, i16 0, i16 0, i16 32512, i16 0, i16 0, i16 0>
}
@@ -154,6 +164,7 @@ define <16 x i8> @movi_v16i8_1() {
; SVE-LABEL: movi_v16i8_1:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #127 // =0x7f
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <16 x i8> <i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}
@@ -168,6 +179,7 @@ define <16 x i8> @movi_v16i8_2() {
; SVE-LABEL: movi_v16i8_2:
; SVE: // %bb.0:
; SVE-NEXT: mov z0.d, #32512 // =0x7f00
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
; SVE-NEXT: ret
ret <16 x i8> <i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}
diff --git a/llvm/test/CodeGen/AArch64/neon-abd.ll b/llvm/test/CodeGen/AArch64/neon-abd.ll
index 314edd2fc81a7..c81438aa2250e 100644
--- a/llvm/test/CodeGen/AArch64/neon-abd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-abd.ll
@@ -525,6 +525,7 @@ define <4 x i16> @combine_sabd_4h_zerosign(<4 x i16> %a, <4 x i16> %b) #0 {
; CHECK-LABEL: combine_sabd_4h_zerosign:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%a.ext = ashr <4 x i16> %a, <i16 7, i16 8, i16 9, i16 10>
%b.ext = ashr <4 x i16> %b, <i16 11, i16 12, i16 13, i16 14>
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 11b3b62ec1c8d..47ceeece0a6e5 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -2482,6 +2482,7 @@ define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
; CHECK-SD-LABEL: fcmal2xfloat:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fcmal2xfloat:
@@ -2535,6 +2536,7 @@ define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
; CHECK-LABEL: fcmnv2xfloat:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%tmp3 = fcmp false <2 x float> %A, %B
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
diff --git a/llvm/test/CodeGen/AArch64/neon-mov.ll b/llvm/test/CodeGen/AArch64/neon-mov.ll
index 5be9394f61b30..4e5b099d62e7f 100644
--- a/llvm/test/CodeGen/AArch64/neon-mov.ll
+++ b/llvm/test/CodeGen/AArch64/neon-mov.ll
@@ -16,6 +16,7 @@ define <8 x i8> @movi8b_0() {
; CHECK-LABEL: movi8b_0:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
ret <8 x i8> zeroinitializer
}
@@ -48,6 +49,7 @@ define <2 x i32> @movi2s_0() {
; CHECK-LABEL: movi2s_0:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
ret <2 x i32> zeroinitializer
}
@@ -417,6 +419,7 @@ define <2 x float> @fmov2s_0() {
; CHECK-LABEL: fmov2s_0:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
ret <2 x float> zeroinitializer
}
diff --git a/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll b/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
index 2a19d258f1adf..6f1b68dbcd667 100644
--- a/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
+++ b/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
@@ -10,6 +10,7 @@ define float @foo() {
; CHECK-NEON-LABEL: foo:
; CHECK-NEON: // %bb.0: // %entry
; CHECK-NEON-NEXT: movi v0.2s, #79, lsl #24
+; CHECK-NEON-NEXT: // kill: def $s0 killed $s0 killed $d0
; CHECK-NEON-NEXT: ret
;
; CHECK-SCALAR-LABEL: foo:
diff --git a/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll b/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
index ebec275c92c52..1bdfac8d6c979 100644
--- a/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
+++ b/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
@@ -195,8 +195,8 @@ define <vscale x 2 x i64> @zero_fill_non_zero_index(<vscale x 2 x i1> %pg, <vsca
define <vscale x 4 x i64> @zero_fill_type_mismatch(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {
; CHECK-LABEL: zero_fill_type_mismatch:
; CHECK: // %bb.0:
-; CHECK-NEXT: uminv d0, p0, z0.d
; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: uminv d0, p0, z0.d
; CHECK-NEXT: ret
%t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
%t2 = insertelement <vscale x 4 x i64> zeroinitializer, i64 %t1, i64 0
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
index ad00e99b704dd..275d13ebfd949 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
@@ -419,6 +419,7 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) {
; CHECK-LABEL: insertelement_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, #5 // =0x5
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: insertelement_v1i64:
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
index 37435e35ceabf..9c7a3d5046d0e 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
@@ -39,6 +39,7 @@ define <2 x i64> @fixed_vec_zero_constant() {
; CHECK-LABEL: fixed_vec_zero_constant:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, #0 // =0x0
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fixed_vec_zero_constant:
@@ -53,6 +54,7 @@ define <2 x double> @fixed_vec_fp_zero_constant() {
; CHECK-LABEL: fixed_vec_fp_zero_constant:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, #0 // =0x0
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fixed_vec_fp_zero_constant:
diff --git a/llvm/test/CodeGen/AArch64/win64_vararg.ll b/llvm/test/CodeGen/AArch64/win64_vararg.ll
index d72dee9021251..f453f887453a0 100644
--- a/llvm/test/CodeGen/AArch64/win64_vararg.ll
+++ b/llvm/test/CodeGen/AArch64/win64_vararg.ll
@@ -32,9 +32,8 @@ define ptr @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i6
; CHECK-LABEL: f9:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x0, sp, #24
-; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
entry:
@@ -48,9 +47,8 @@ define ptr @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i6
; CHECK-LABEL: f8:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: add x8, sp, #16
; CHECK-NEXT: add x0, sp, #16
-; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
entry:
@@ -64,10 +62,9 @@ define ptr @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, ..
; CHECK-LABEL: f7:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #32
-; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: str x7, [sp, #24]
-; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
index 610c72b5f932e..f06acc0a3aa01 100644
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -65,6 +65,7 @@ define float @float_negative_zero(ptr %pf) nounwind {
; CHECKZFINX-LABEL: float_negative_zero:
; CHECKZFINX: # %bb.0:
; CHECKZFINX-NEXT: lui a0, 524288
+; CHECKZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
; CHECKZFINX-NEXT: ret
ret float -0.0
}
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index ec1a7a4dfc4f0..f92efa17b460e 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -120,6 +120,7 @@ define half @half_negative_zero(ptr %pf) nounwind {
; CHECKIZHINX-LABEL: half_negative_zero:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: lui a0, 1048568
+; CHECKIZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: half_negative_zero:
@@ -131,6 +132,7 @@ define half @half_negative_zero(ptr %pf) nounwind {
; CHECKIZHINXMIN-LABEL: half_negative_zero:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: lui a0, 1048568
+; CHECKIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; CHECKIZHINXMIN-NEXT: ret
ret half -0.0
}
diff --git a/llvm/test/CodeGen/RISCV/ret-remat.ll b/llvm/test/CodeGen/RISCV/ret-remat.ll
new file mode 100644
index 0000000000000..c4381e235bbfd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/ret-remat.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr=+m,+a,+f,+d,+c < %s | FileCheck %s
+
+ at bytes1 = external hidden global i32
+
+define i8 @cast_and_load_1() {
+; CHECK-LABEL: cast_and_load_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, %hi(bytes1)
+; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: sw a0, %lo(bytes1)(a1)
+; CHECK-NEXT: ret
+ store i32 42, ptr @bytes1, align 4
+ %l = load i8, ptr @bytes1, align 1
+ ret i8 %l
+}
diff --git a/llvm/test/CodeGen/RISCV/zfhmin-imm.ll b/llvm/test/CodeGen/RISCV/zfhmin-imm.ll
index 7b3efd6fb8f2b..5be46f78491e2 100644
--- a/llvm/test/CodeGen/RISCV/zfhmin-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zfhmin-imm.ll
@@ -75,11 +75,13 @@ define half @f16_negative_zero(ptr %pf) nounwind {
; RV32IZHINXMIN-LABEL: f16_negative_zero:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: lui a0, 1048568
+; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV32IZHINXMIN-NEXT: ret
;
; RV32IZDINXZHINXMIN-LABEL: f16_negative_zero:
; RV32IZDINXZHINXMIN: # %bb.0:
; RV32IZDINXZHINXMIN-NEXT: lui a0, 1048568
+; RV32IZDINXZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV32IZDINXZHINXMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: f16_negative_zero:
@@ -97,11 +99,13 @@ define half @f16_negative_zero(ptr %pf) nounwind {
; RV64IZHINXMIN-LABEL: f16_negative_zero:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: lui a0, 1048568
+; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV64IZHINXMIN-NEXT: ret
;
; RV64IZDINXZHINXMIN-LABEL: f16_negative_zero:
; RV64IZDINXZHINXMIN: # %bb.0:
; RV64IZDINXZHINXMIN-NEXT: lui a0, 1048568
+; RV64IZDINXZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV64IZDINXZHINXMIN-NEXT: ret
ret half -0.0
}
diff --git a/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll b/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
index e6f28c2057f77..bef7603c53b55 100644
--- a/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
+++ b/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
@@ -29,6 +29,7 @@ define i1 @loadAndRLEsource_no_exit_2E_1_label_2E_0(i32 %tmp.21.reload, i32 %tmp
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_2: ## %codeRepl5.exitStub
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
newFuncRoot:
diff --git a/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll b/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll
index 206574eeae2ae..8cc4dfcbd528b 100644
--- a/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll
+++ b/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll
@@ -90,6 +90,7 @@ define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(ptr %l_addr.01.0.i2.i.i929, ptr %tm
; CHECK-NEXT: LBB0_3: ## %NewDefault
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
index cfb3e508576dd..1a9f6dba64267 100644
--- a/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -21,6 +21,7 @@ define signext i16 @f(ptr %bp, ptr %ss) {
; CHECK-NEXT: jb .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
index 6ebb97d63e7c6..53ea8c0576c50 100644
--- a/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
+++ b/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
@@ -16,6 +16,7 @@ define signext i16 @t(ptr %qmatrix, ptr %dct, ptr %acBaseTable, ptr %acExtTabl
; CHECK-NEXT: jb .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
entry:
br label %cond_next127
diff --git a/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
index 503afa8803a43..8704a676954bb 100644
--- a/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
+++ b/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
@@ -7,6 +7,7 @@ define signext i16 @t() {
; CHECK-NEXT: movswl 0, %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
entry:
%tmp180 = load i16, ptr null, align 2 ; <i16> [#uses=3]
diff --git a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
index b32afdc2214e0..31395ca16e6ac 100644
--- a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -83,6 +83,7 @@ define i16 @SQLDriversW(ptr %henv, i16 zeroext %fDir, ptr %szDrvDesc, i16 signe
; CHECK-NEXT: addl $48, %esp
; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: LBB0_2: ## %bb
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll
index 079294ef09bdb..fdd743843b8e5 100644
--- a/llvm/test/CodeGen/X86/add.ll
+++ b/llvm/test/CodeGen/X86/add.ll
@@ -136,6 +136,7 @@ define i1 @test4(i32 %v1, i32 %v2, ptr %X) nounwind {
; X86-NEXT: movl $0, (%eax)
; X86-NEXT: .LBB5_2: # %overflow
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LINUX-LABEL: test4:
@@ -146,6 +147,7 @@ define i1 @test4(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-LINUX-NEXT: movl $0, (%rdx)
; X64-LINUX-NEXT: .LBB5_2: # %overflow
; X64-LINUX-NEXT: xorl %eax, %eax
+; X64-LINUX-NEXT: # kill: def $al killed $al killed $eax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test4:
@@ -156,6 +158,7 @@ define i1 @test4(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-WIN32-NEXT: movl $0, (%r8)
; X64-WIN32-NEXT: .LBB5_2: # %overflow
; X64-WIN32-NEXT: xorl %eax, %eax
+; X64-WIN32-NEXT: # kill: def $al killed $al killed $eax
; X64-WIN32-NEXT: retq
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -182,6 +185,7 @@ define i1 @test5(i32 %v1, i32 %v2, ptr %X) nounwind {
; X86-NEXT: movl $0, (%eax)
; X86-NEXT: .LBB6_2: # %carry
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LINUX-LABEL: test5:
@@ -192,6 +196,7 @@ define i1 @test5(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-LINUX-NEXT: movl $0, (%rdx)
; X64-LINUX-NEXT: .LBB6_2: # %carry
; X64-LINUX-NEXT: xorl %eax, %eax
+; X64-LINUX-NEXT: # kill: def $al killed $al killed $eax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test5:
@@ -202,6 +207,7 @@ define i1 @test5(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-WIN32-NEXT: movl $0, (%r8)
; X64-WIN32-NEXT: .LBB6_2: # %carry
; X64-WIN32-NEXT: xorl %eax, %eax
+; X64-WIN32-NEXT: # kill: def $al killed $al killed $eax
; X64-WIN32-NEXT: retq
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll
index 97894db1188e2..1f3ab806329e8 100644
--- a/llvm/test/CodeGen/X86/addcarry.ll
+++ b/llvm/test/CodeGen/X86/addcarry.ll
@@ -607,8 +607,9 @@ define { i64, i64, i1 } @addcarry_2x64_and_reversed(i64 %x0, i64 %x1, i64 %y0, i
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
-; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: movq %rsi, %rdx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
diff --git a/llvm/test/CodeGen/X86/all-ones-vector.ll b/llvm/test/CodeGen/X86/all-ones-vector.ll
index d624f6c13e367..f4ceb79026c33 100644
--- a/llvm/test/CodeGen/X86/all-ones-vector.ll
+++ b/llvm/test/CodeGen/X86/all-ones-vector.ll
@@ -92,7 +92,7 @@ define <32 x i8> @allones_v32i8() nounwind {
; SSE-LABEL: allones_v32i8:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v32i8:
@@ -112,7 +112,7 @@ define <16 x i16> @allones_v16i16() nounwind {
; SSE-LABEL: allones_v16i16:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v16i16:
@@ -132,7 +132,7 @@ define <8 x i32> @allones_v8i32() nounwind {
; SSE-LABEL: allones_v8i32:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v8i32:
@@ -152,7 +152,7 @@ define <4 x i64> @allones_v4i64() nounwind {
; SSE-LABEL: allones_v4i64:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v4i64:
@@ -172,7 +172,7 @@ define <4 x double> @allones_v4f64() nounwind {
; SSE-LABEL: allones_v4f64:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v4f64:
@@ -192,7 +192,7 @@ define <4 x double> @allones_v4f64_optsize() nounwind optsize {
; SSE-LABEL: allones_v4f64_optsize:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v4f64_optsize:
@@ -212,7 +212,7 @@ define <8 x float> @allones_v8f32() nounwind {
; SSE-LABEL: allones_v8f32:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v8f32:
@@ -232,7 +232,7 @@ define <8 x float> @allones_v8f32_optsize() nounwind optsize {
; SSE-LABEL: allones_v8f32_optsize:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v8f32_optsize:
@@ -252,9 +252,9 @@ define <64 x i8> @allones_v64i8() nounwind {
; SSE-LABEL: allones_v64i8:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v64i8:
@@ -267,12 +267,12 @@ define <64 x i8> @allones_v64i8() nounwind {
; AVX2-LABEL: allones_v64i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: allones_v64i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
+; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1
; AVX512-NEXT: ret{{[l|q]}}
ret <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
}
@@ -281,9 +281,9 @@ define <32 x i16> @allones_v32i16() nounwind {
; SSE-LABEL: allones_v32i16:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v32i16:
@@ -296,12 +296,12 @@ define <32 x i16> @allones_v32i16() nounwind {
; AVX2-LABEL: allones_v32i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: allones_v32i16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
+; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1
; AVX512-NEXT: ret{{[l|q]}}
ret <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
}
@@ -310,9 +310,9 @@ define <16 x i32> @allones_v16i32() nounwind {
; SSE-LABEL: allones_v16i32:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v16i32:
@@ -325,12 +325,12 @@ define <16 x i32> @allones_v16i32() nounwind {
; AVX2-LABEL: allones_v16i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: allones_v16i32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
+; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1
; AVX512-NEXT: ret{{[l|q]}}
ret <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
}
@@ -339,9 +339,9 @@ define <8 x i64> @allones_v8i64() nounwind {
; SSE-LABEL: allones_v8i64:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v8i64:
@@ -354,12 +354,12 @@ define <8 x i64> @allones_v8i64() nounwind {
; AVX2-LABEL: allones_v8i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: allones_v8i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
+; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1
; AVX512-NEXT: ret{{[l|q]}}
ret <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
}
@@ -368,9 +368,9 @@ define <8 x double> @allones_v8f64() nounwind {
; SSE-LABEL: allones_v8f64:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v8f64:
@@ -383,12 +383,12 @@ define <8 x double> @allones_v8f64() nounwind {
; AVX2-LABEL: allones_v8f64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: allones_v8f64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
+; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1
; AVX512-NEXT: ret{{[l|q]}}
ret <8 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff>
}
@@ -397,9 +397,9 @@ define <16 x float> @allones_v16f32() nounwind {
; SSE-LABEL: allones_v16f32:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: ret{{[l|q]}}
;
; AVX1-LABEL: allones_v16f32:
@@ -412,12 +412,12 @@ define <16 x float> @allones_v16f32() nounwind {
; AVX2-LABEL: allones_v16f32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: allones_v16f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
+; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1
; AVX512-NEXT: ret{{[l|q]}}
ret <16 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
}
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index 4c58c8a980314..b18a2d7418158 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -97,6 +97,7 @@ define i8 @ccmp8rr_sf(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8rr_sf:
@@ -109,6 +110,7 @@ define i8 @ccmp8rr_sf(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
@@ -135,6 +137,7 @@ define i8 @ccmp8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8rr_none:
@@ -147,6 +150,7 @@ define i8 @ccmp8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
@@ -380,6 +384,7 @@ define i8 @ccmp8ri_zf_double(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8ri_zf_double:
@@ -393,6 +398,7 @@ define i8 @ccmp8ri_zf_double(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; NDD-NEXT: .LBB9_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
@@ -423,6 +429,7 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8ri_zf_double_p:
@@ -439,6 +446,7 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; NDD-NEXT: .LBB10_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
@@ -469,6 +477,7 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; CHECK-NEXT: .LBB11_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8ri_zf_double_np:
@@ -485,6 +494,7 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; NDD-NEXT: .LBB11_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
diff --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll
index 5f3ec8a19d0a4..e431736e83b73 100644
--- a/llvm/test/CodeGen/X86/apx/ctest.ll
+++ b/llvm/test/CodeGen/X86/apx/ctest.ll
@@ -49,6 +49,7 @@ define i8 @ctest8rr_zf_double(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi)
; CHECK-NEXT: .LBB1_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_zf_double:
@@ -61,6 +62,7 @@ define i8 @ctest8rr_zf_double(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi)
; NDD-NEXT: .LBB1_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
@@ -90,6 +92,7 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi)
; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_zf_double_p:
@@ -105,6 +108,7 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi)
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
@@ -134,6 +138,7 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi)
; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_zf_double_np:
@@ -149,6 +154,7 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi)
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
@@ -210,6 +216,7 @@ define i8 @ctest8rr_sf_2(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx)
; CHECK-NEXT: .LBB5_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_sf_2:
@@ -221,6 +228,7 @@ define i8 @ctest8rr_sf_2(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx)
; NDD-NEXT: .LBB5_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp sgt i8 %a, 0
@@ -246,6 +254,7 @@ define i8 @ctest8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx)
; CHECK-NEXT: .LBB6_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_none:
@@ -257,6 +266,7 @@ define i8 @ctest8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx)
; NDD-NEXT: .LBB6_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
diff --git a/llvm/test/CodeGen/X86/apx/imulzu.ll b/llvm/test/CodeGen/X86/apx/imulzu.ll
index 9a4a63750a1db..e8e6efa0357b5 100644
--- a/llvm/test/CodeGen/X86/apx/imulzu.ll
+++ b/llvm/test/CodeGen/X86/apx/imulzu.ll
@@ -208,6 +208,7 @@ define i16 @mul0_16(i16 %A) {
; CHECK-LABEL: mul0_16:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%mul = mul i16 %A, 0
ret i16 %mul
diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll
index e8e0ee0b7ef49..133dbca10a396 100644
--- a/llvm/test/CodeGen/X86/atomic-unordered.ll
+++ b/llvm/test/CodeGen/X86/atomic-unordered.ll
@@ -2318,32 +2318,19 @@ define i16 @load_combine(ptr %p) {
}
define i1 @fold_cmp_over_fence(ptr %p, i32 %v1) {
-; CHECK-O0-LABEL: fold_cmp_over_fence:
-; CHECK-O0: # %bb.0:
-; CHECK-O0-NEXT: movl (%rdi), %eax
-; CHECK-O0-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
-; CHECK-O0-NEXT: cmpl %eax, %esi
-; CHECK-O0-NEXT: jne .LBB116_2
-; CHECK-O0-NEXT: # %bb.1: # %taken
-; CHECK-O0-NEXT: movb $1, %al
-; CHECK-O0-NEXT: retq
-; CHECK-O0-NEXT: .LBB116_2: # %untaken
-; CHECK-O0-NEXT: xorl %eax, %eax
-; CHECK-O0-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-O0-NEXT: retq
-;
-; CHECK-O3-LABEL: fold_cmp_over_fence:
-; CHECK-O3: # %bb.0:
-; CHECK-O3-NEXT: movl (%rdi), %eax
-; CHECK-O3-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
-; CHECK-O3-NEXT: cmpl %eax, %esi
-; CHECK-O3-NEXT: jne .LBB116_2
-; CHECK-O3-NEXT: # %bb.1: # %taken
-; CHECK-O3-NEXT: movb $1, %al
-; CHECK-O3-NEXT: retq
-; CHECK-O3-NEXT: .LBB116_2: # %untaken
-; CHECK-O3-NEXT: xorl %eax, %eax
-; CHECK-O3-NEXT: retq
+; CHECK-LABEL: fold_cmp_over_fence:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl %eax, %esi
+; CHECK-NEXT: jne .LBB116_2
+; CHECK-NEXT: # %bb.1: # %taken
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB116_2: # %untaken
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
%v2 = load atomic i32, ptr %p unordered, align 4
fence seq_cst
%cmp = icmp eq i32 %v1, %v2
diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll
index 684e2921b789e..170774b3612a0 100644
--- a/llvm/test/CodeGen/X86/bfloat.ll
+++ b/llvm/test/CodeGen/X86/bfloat.ll
@@ -815,9 +815,9 @@ define <32 x bfloat> @pr63017() {
; SSE2-LABEL: pr63017:
; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm0, %xmm0
-; SSE2-NEXT: xorps %xmm1, %xmm1
-; SSE2-NEXT: xorps %xmm2, %xmm2
-; SSE2-NEXT: xorps %xmm3, %xmm3
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: retq
;
; F16-LABEL: pr63017:
@@ -828,7 +828,7 @@ define <32 x bfloat> @pr63017() {
; AVXNC-LABEL: pr63017:
; AVXNC: # %bb.0:
; AVXNC-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; AVXNC-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVXNC-NEXT: vmovaps %ymm0, %ymm1
; AVXNC-NEXT: retq
ret <32 x bfloat> zeroinitializer
}
diff --git a/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll b/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
index 98d315ad14e68..87c1ccbe891f5 100644
--- a/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
+++ b/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll
@@ -74,10 +74,10 @@ define dso_local nonnull ptr @foo3() local_unnamed_addr #0 {
; CHECK-LABEL: foo3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: endbr64
-; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105
-; CHECK-NEXT: notl %eax
-; CHECK-NEXT: andl %eax, czx(%rip)
; CHECK-NEXT: movl $czx, %eax
+; CHECK-NEXT: movl $217112837, %ecx # imm = 0xCF0E105
+; CHECK-NEXT: notl %ecx
+; CHECK-NEXT: andl %ecx, czx(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i32, ptr @czx, align 4
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index ed3f0e0f0aa71..392263dc8c49d 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -66,6 +66,7 @@ define i8 @test2b(i8 %X, ptr %y) nounwind {
; CHECK-NEXT: retq # encoding: [0xc3]
; CHECK-NEXT: .LBB2_2: # %ReturnBlock
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i8, ptr %y
diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
index 66ba54f3e318e..f07a2a9819d0d 100644
--- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
+++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
@@ -21,19 +21,19 @@ define i1 @_ZN4llvm8LLParser17parseDIEnumeratorERPNS_6MDNodeEb(i32 %arg) {
; CHECK-NEXT: .LBB0_4: # %if.then.i.i
; CHECK-NEXT: movb $1, %dl
; CHECK-NEXT: testb %dl, %dl
-; CHECK-NEXT: je .LBB0_6
-; CHECK-NEXT: .LBB0_7: # %do.end
+; CHECK-NEXT: je .LBB0_7
+; CHECK-NEXT: .LBB0_6: # %do.end
; CHECK-NEXT: movq %rcx, 0
; CHECK-NEXT: movb %al, 0
+; CHECK-NEXT: .LBB0_7: # %if.then8
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: testb %dl, %dl
-; CHECK-NEXT: jne .LBB0_7
-; CHECK-NEXT: .LBB0_6: # %if.then8
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: retq
+; CHECK-NEXT: jne .LBB0_6
+; CHECK-NEXT: jmp .LBB0_7
entry:
switch i32 %arg, label %if.then.i.i [
i32 1, label %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
diff --git a/llvm/test/CodeGen/X86/combine-mulo.ll b/llvm/test/CodeGen/X86/combine-mulo.ll
index 896269a288f56..0c722e09888ac 100644
--- a/llvm/test/CodeGen/X86/combine-mulo.ll
+++ b/llvm/test/CodeGen/X86/combine-mulo.ll
@@ -97,6 +97,7 @@ define { i32, i1 } @combine_smul_nsw(i32 %a, i32 %b) {
; CHECK-NEXT: andl $524287, %eax # imm = 0x7FFFF
; CHECK-NEXT: imull %edi, %eax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%aa = and i32 %a, 4095 ; 0xfff
%bb = and i32 %b, 524287; 0x7ffff
diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll
index 1ce10c3708d58..9e42d4afdcc70 100644
--- a/llvm/test/CodeGen/X86/combine-shl.ll
+++ b/llvm/test/CodeGen/X86/combine-shl.ll
@@ -285,7 +285,7 @@ define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) {
; SSE-LABEL: combine_vec_shl_ext_shl1:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
-; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_ext_shl1:
diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll
index 4b01c16a6324e..20a6522654e97 100644
--- a/llvm/test/CodeGen/X86/combine-srem.ll
+++ b/llvm/test/CodeGen/X86/combine-srem.ll
@@ -429,6 +429,7 @@ define i1 @bool_srem(i1 %x, i1 %y) {
; CHECK-LABEL: bool_srem:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%r = srem i1 %x, %y
ret i1 %r
diff --git a/llvm/test/CodeGen/X86/combine-subo.ll b/llvm/test/CodeGen/X86/combine-subo.ll
index 5e4bba6e0fd35..57aa323ee1a76 100644
--- a/llvm/test/CodeGen/X86/combine-subo.ll
+++ b/llvm/test/CodeGen/X86/combine-subo.ll
@@ -162,6 +162,7 @@ define { i32, i1 } @combine_usub_nuw(i32 %a, i32 %b) {
; CHECK-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
; CHECK-NEXT: subl %esi, %eax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%aa = or i32 %a, 2147483648
%bb = and i32 %b, 2147483647
@@ -202,13 +203,13 @@ define { <4 x i8>, <4 x i1> } @always_usub_const_vector() nounwind {
; SSE-LABEL: always_usub_const_vector:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: always_usub_const_vector:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vmovdqa %xmm0, %xmm1
; AVX-NEXT: retq
%x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> <i8 0, i8 0, i8 0, i8 0>, <4 x i8> <i8 1, i8 1, i8 1, i8 1>)
ret { <4 x i8>, <4 x i1> } %x
diff --git a/llvm/test/CodeGen/X86/combine-urem.ll b/llvm/test/CodeGen/X86/combine-urem.ll
index 715d5c7b28f11..ca49ed6c71532 100644
--- a/llvm/test/CodeGen/X86/combine-urem.ll
+++ b/llvm/test/CodeGen/X86/combine-urem.ll
@@ -488,6 +488,7 @@ define i1 @bool_urem(i1 %x, i1 %y) {
; CHECK-LABEL: bool_urem:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%r = urem i1 %x, %y
ret i1 %r
diff --git a/llvm/test/CodeGen/X86/divmod128.ll b/llvm/test/CodeGen/X86/divmod128.ll
index 3796dd796eaf9..3d24ffc1bca3c 100644
--- a/llvm/test/CodeGen/X86/divmod128.ll
+++ b/llvm/test/CodeGen/X86/divmod128.ll
@@ -141,8 +141,8 @@ define i128 @urem_i128_3(i128 %x) nounwind {
; X86-64-NEXT: shrq %rdx
; X86-64-NEXT: leaq (%rdx,%rdx,2), %rax
; X86-64-NEXT: subq %rax, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_3:
@@ -155,8 +155,8 @@ define i128 @urem_i128_3(i128 %x) nounwind {
; WIN64-NEXT: shrq %rdx
; WIN64-NEXT: leaq (%rdx,%rdx,2), %rax
; WIN64-NEXT: subq %rax, %rcx
-; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 3
@@ -174,8 +174,8 @@ define i128 @urem_i128_5(i128 %x) nounwind {
; X86-64-NEXT: shrq $2, %rdx
; X86-64-NEXT: leaq (%rdx,%rdx,4), %rax
; X86-64-NEXT: subq %rax, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_5:
@@ -188,8 +188,8 @@ define i128 @urem_i128_5(i128 %x) nounwind {
; WIN64-NEXT: shrq $2, %rdx
; WIN64-NEXT: leaq (%rdx,%rdx,4), %rax
; WIN64-NEXT: subq %rax, %rcx
-; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 5
@@ -208,8 +208,8 @@ define i128 @urem_i128_15(i128 %x) nounwind {
; X86-64-NEXT: leaq (%rdx,%rdx,4), %rax
; X86-64-NEXT: leaq (%rax,%rax,2), %rax
; X86-64-NEXT: subq %rax, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_15:
@@ -223,8 +223,8 @@ define i128 @urem_i128_15(i128 %x) nounwind {
; WIN64-NEXT: leaq (%rdx,%rdx,4), %rax
; WIN64-NEXT: leaq (%rax,%rax,2), %rax
; WIN64-NEXT: subq %rax, %rcx
-; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 15
@@ -244,8 +244,8 @@ define i128 @urem_i128_17(i128 %x) nounwind {
; X86-64-NEXT: shrq $4, %rdx
; X86-64-NEXT: addq %rax, %rdx
; X86-64-NEXT: subq %rdx, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_17:
@@ -260,8 +260,8 @@ define i128 @urem_i128_17(i128 %x) nounwind {
; WIN64-NEXT: shrq $4, %rdx
; WIN64-NEXT: addq %rax, %rdx
; WIN64-NEXT: subq %rdx, %rcx
-; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 17
@@ -282,8 +282,8 @@ define i128 @urem_i128_255(i128 %x) nounwind {
; X86-64-NEXT: subq %rax, %rdx
; X86-64-NEXT: addq %rsi, %rdi
; X86-64-NEXT: adcq %rdx, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_255:
@@ -300,8 +300,8 @@ define i128 @urem_i128_255(i128 %x) nounwind {
; WIN64-NEXT: subq %rax, %rdx
; WIN64-NEXT: addq %rcx, %r8
; WIN64-NEXT: adcq %rdx, %r8
-; WIN64-NEXT: movq %r8, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %r8, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 255
@@ -321,8 +321,8 @@ define i128 @urem_i128_257(i128 %x) nounwind {
; X86-64-NEXT: shrq $8, %rdx
; X86-64-NEXT: addq %rax, %rdx
; X86-64-NEXT: subq %rdx, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_257:
@@ -337,8 +337,8 @@ define i128 @urem_i128_257(i128 %x) nounwind {
; WIN64-NEXT: shrq $8, %rdx
; WIN64-NEXT: addq %rax, %rdx
; WIN64-NEXT: subq %rdx, %rcx
-; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 257
@@ -359,8 +359,8 @@ define i128 @urem_i128_65535(i128 %x) nounwind {
; X86-64-NEXT: subq %rax, %rdx
; X86-64-NEXT: addq %rsi, %rdi
; X86-64-NEXT: adcq %rdx, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_65535:
@@ -377,8 +377,8 @@ define i128 @urem_i128_65535(i128 %x) nounwind {
; WIN64-NEXT: subq %rax, %rdx
; WIN64-NEXT: addq %rcx, %r8
; WIN64-NEXT: adcq %rdx, %r8
-; WIN64-NEXT: movq %r8, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %r8, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 65535
@@ -398,8 +398,8 @@ define i128 @urem_i128_65537(i128 %x) nounwind {
; X86-64-NEXT: shrq $16, %rdx
; X86-64-NEXT: addq %rax, %rdx
; X86-64-NEXT: subq %rdx, %rdi
-; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: xorl %edx, %edx
+; X86-64-NEXT: movq %rdi, %rax
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_65537:
@@ -414,8 +414,8 @@ define i128 @urem_i128_65537(i128 %x) nounwind {
; WIN64-NEXT: shrq $16, %rdx
; WIN64-NEXT: addq %rax, %rdx
; WIN64-NEXT: subq %rdx, %rcx
-; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: xorl %edx, %edx
+; WIN64-NEXT: movq %rcx, %rax
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 65537
diff --git a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
index b9ef3154cd1c3..19bf6c3b61e9c 100644
--- a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
@@ -584,6 +584,7 @@ define zeroext i1 @fcmp_ogt2(float %x) {
; SDAG-LABEL: fcmp_ogt2:
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: fcmp_ogt2:
@@ -678,6 +679,7 @@ define zeroext i1 @fcmp_olt2(float %x) {
; SDAG-LABEL: fcmp_olt2:
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: fcmp_olt2:
@@ -772,6 +774,7 @@ define zeroext i1 @fcmp_one2(float %x) {
; SDAG-LABEL: fcmp_one2:
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: fcmp_one2:
diff --git a/llvm/test/CodeGen/X86/fast-isel-load-i1.ll b/llvm/test/CodeGen/X86/fast-isel-load-i1.ll
index 34ce8810251e0..e48558f3f4c2d 100644
--- a/llvm/test/CodeGen/X86/fast-isel-load-i1.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-load-i1.ll
@@ -8,6 +8,7 @@ define i1 @test_i1(ptr %b) {
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %in
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_2: # %out
; CHECK-NEXT: movb $1, %al
diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index 9121cf2d654a3..c509e05165b25 100644
--- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -849,6 +849,7 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: ret{{[l|q]}}
%t0 = lshr i8 24, %y
%t1 = and i8 %t0, %x
diff --git a/llvm/test/CodeGen/X86/i128-immediate.ll b/llvm/test/CodeGen/X86/i128-immediate.ll
index 96c05a3a32128..738448299e761 100644
--- a/llvm/test/CodeGen/X86/i128-immediate.ll
+++ b/llvm/test/CodeGen/X86/i128-immediate.ll
@@ -5,7 +5,7 @@ define i128 @__addvti3() {
; CHECK-LABEL: __addvti3:
; CHECK: # %bb.0:
; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: movq $-1, %rdx
+; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: retq
ret i128 -1
}
diff --git a/llvm/test/CodeGen/X86/int-to-fp-demanded.ll b/llvm/test/CodeGen/X86/int-to-fp-demanded.ll
index cdde03fb0534b..baf6e2982fdac 100644
--- a/llvm/test/CodeGen/X86/int-to-fp-demanded.ll
+++ b/llvm/test/CodeGen/X86/int-to-fp-demanded.ll
@@ -261,8 +261,9 @@ define <2 x i16> @uitofp_signbit_only_fail_bad_width2(i32 %i_in) nounwind {
; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: movl $32768, %eax # imm = 0x8000
; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: # kill: def $dx killed $dx killed $edx
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index 97136dafa6c2c..f20dd90d9b7ff 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -1636,11 +1636,13 @@ define i1 @isnone_f(float %x) {
; X86-LABEL: isnone_f:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LABEL: isnone_f:
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
diff --git a/llvm/test/CodeGen/X86/isel-fpclass.ll b/llvm/test/CodeGen/X86/isel-fpclass.ll
index df04b673d8223..e16a6d650060d 100644
--- a/llvm/test/CodeGen/X86/isel-fpclass.ll
+++ b/llvm/test/CodeGen/X86/isel-fpclass.ll
@@ -10,11 +10,13 @@ define i1 @isnone_f(float %x) nounwind {
; X86-LABEL: isnone_f:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LABEL: isnone_f:
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-FASTISEL-LABEL: isnone_f:
@@ -22,6 +24,7 @@ define i1 @isnone_f(float %x) nounwind {
; X86-FASTISEL-NEXT: flds {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstp %st(0)
; X86-FASTISEL-NEXT: xorl %eax, %eax
+; X86-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X86-FASTISEL-NEXT: retl
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
@@ -405,11 +408,13 @@ define i1 @isnone_d(double %x) nounwind {
; X86-LABEL: isnone_d:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LABEL: isnone_d:
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-FASTISEL-LABEL: isnone_d:
@@ -417,6 +422,7 @@ define i1 @isnone_d(double %x) nounwind {
; X86-FASTISEL-NEXT: fldl {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstp %st(0)
; X86-FASTISEL-NEXT: xorl %eax, %eax
+; X86-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X86-FASTISEL-NEXT: retl
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 0)
@@ -449,11 +455,13 @@ define i1 @isnone_f80(x86_fp80 %x) nounwind {
; X86-LABEL: isnone_f80:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-SDAGISEL-LABEL: isnone_f80:
; X64-SDAGISEL: # %bb.0: # %entry
; X64-SDAGISEL-NEXT: xorl %eax, %eax
+; X64-SDAGISEL-NEXT: # kill: def $al killed $al killed $eax
; X64-SDAGISEL-NEXT: retq
;
; X86-FASTISEL-LABEL: isnone_f80:
@@ -461,6 +469,7 @@ define i1 @isnone_f80(x86_fp80 %x) nounwind {
; X86-FASTISEL-NEXT: fldt {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstp %st(0)
; X86-FASTISEL-NEXT: xorl %eax, %eax
+; X86-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X86-FASTISEL-NEXT: retl
;
; X64-FASTISEL-LABEL: isnone_f80:
@@ -468,11 +477,13 @@ define i1 @isnone_f80(x86_fp80 %x) nounwind {
; X64-FASTISEL-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-FASTISEL-NEXT: fstp %st(0)
; X64-FASTISEL-NEXT: xorl %eax, %eax
+; X64-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X64-FASTISEL-NEXT: retq
;
; X64-GISEL-LABEL: isnone_f80:
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: xorl %eax, %eax
+; X64-GISEL-NEXT: # kill: def $al killed $al killed $eax
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 0)
diff --git a/llvm/test/CodeGen/X86/knownbits-div.ll b/llvm/test/CodeGen/X86/knownbits-div.ll
index 02e20a9010cc6..698f56e93884a 100644
--- a/llvm/test/CodeGen/X86/knownbits-div.ll
+++ b/llvm/test/CodeGen/X86/knownbits-div.ll
@@ -5,6 +5,7 @@ define i8 @sdiv_neg_neg_high_bits(i8 %x, i8 %y) {
; CHECK-LABEL: sdiv_neg_neg_high_bits:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%num = or i8 %x, 128
%denum = or i8 %y, 131
@@ -45,6 +46,7 @@ define i8 @udiv_exact_even_odd(i8 %x, i8 %y) {
; CHECK-LABEL: udiv_exact_even_odd:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%num = and i8 %x, -2
%denum = or i8 %y, 1
diff --git a/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll b/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
index 7bef94cca0d35..35e6a04cff653 100644
--- a/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
+++ b/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
@@ -641,6 +641,7 @@ define i1 @add_ugtcmp_bad_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: add_ugtcmp_bad_i16_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: ret{{[l|q]}}
%tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ugt i16 %tmp0, -1 ; when we +1 it, it will wrap to 0
diff --git a/llvm/test/CodeGen/X86/memcmp-constant.ll b/llvm/test/CodeGen/X86/memcmp-constant.ll
index 2059b8f804082..d828ba1ee3518 100644
--- a/llvm/test/CodeGen/X86/memcmp-constant.ll
+++ b/llvm/test/CodeGen/X86/memcmp-constant.ll
@@ -19,6 +19,7 @@ define i1 @length4_same_lt() nounwind {
; CHECK-LABEL: length4_same_lt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str1, i64 4) nounwind
%c = icmp slt i32 %m, 0
@@ -29,6 +30,7 @@ define i1 @length4_same_gt() nounwind {
; CHECK-LABEL: length4_same_gt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str1, i64 4) nounwind
%c = icmp sgt i32 %m, 0
@@ -79,6 +81,7 @@ define i1 @length4_gt() nounwind {
; CHECK-LABEL: length4_gt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str2, i64 4) nounwind
%c = icmp sgt i32 %m, 0
@@ -99,6 +102,7 @@ define i1 @length4_ge() nounwind {
; CHECK-LABEL: length4_ge:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str2, i64 4) nounwind
%c = icmp sge i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
index 7d1422d3c961e..55600502b992e 100644
--- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
+++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
@@ -35,6 +35,7 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X86-LABEL: length0_lt:
; X86: # %bb.0:
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
index 3a3824a4ffe83..68ad6dc25eab1 100644
--- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
+++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
@@ -41,6 +41,7 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X64-LABEL: length0_lt:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp-x32.ll b/llvm/test/CodeGen/X86/memcmp-x32.ll
index 28e732be9191d..633f614f9a1a7 100644
--- a/llvm/test/CodeGen/X86/memcmp-x32.ll
+++ b/llvm/test/CodeGen/X86/memcmp-x32.ll
@@ -34,6 +34,7 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X86-LABEL: length0_lt:
; X86: # %bb.0:
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp.ll b/llvm/test/CodeGen/X86/memcmp.ll
index 9e713bfa6c392..2571a7b7f1501 100644
--- a/llvm/test/CodeGen/X86/memcmp.ll
+++ b/llvm/test/CodeGen/X86/memcmp.ll
@@ -40,6 +40,7 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X64-LABEL: length0_lt:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/negate.ll b/llvm/test/CodeGen/X86/negate.ll
index 38751d954b05e..b5cda9dfaee2f 100644
--- a/llvm/test/CodeGen/X86/negate.ll
+++ b/llvm/test/CodeGen/X86/negate.ll
@@ -23,6 +23,7 @@ define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
; CHECK-LABEL: negate_zero_or_minsigned_nsw:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%signbit = and i8 %x, 128
%neg = sub nsw i8 0, %signbit
diff --git a/llvm/test/CodeGen/X86/oddshuffles.ll b/llvm/test/CodeGen/X86/oddshuffles.ll
index 4b0f75df83a76..c42ffa27185f7 100644
--- a/llvm/test/CodeGen/X86/oddshuffles.ll
+++ b/llvm/test/CodeGen/X86/oddshuffles.ll
@@ -2190,11 +2190,11 @@ define <16 x i32> @splat_v3i32(ptr %ptr) {
; SSE2: # %bb.0:
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: xorps %xmm1, %xmm1
-; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,0,1]
+; SSE2-NEXT: xorps %xmm2, %xmm2
+; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,0,1]
; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: xorps %xmm1, %xmm1
-; SSE2-NEXT: xorps %xmm3, %xmm3
+; SSE2-NEXT: movaps %xmm1, %xmm3
; SSE2-NEXT: retq
;
; SSE42-LABEL: splat_v3i32:
@@ -2205,7 +2205,7 @@ define <16 x i32> @splat_v3i32(ptr %ptr) {
; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1],xmm2[2,3,4,5,6,7]
; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,0,1]
-; SSE42-NEXT: xorps %xmm3, %xmm3
+; SSE42-NEXT: movdqa %xmm1, %xmm3
; SSE42-NEXT: retq
;
; AVX1-LABEL: splat_v3i32:
diff --git a/llvm/test/CodeGen/X86/oddsubvector.ll b/llvm/test/CodeGen/X86/oddsubvector.ll
index 5df1867f73c8e..458ddbba14744 100644
--- a/llvm/test/CodeGen/X86/oddsubvector.ll
+++ b/llvm/test/CodeGen/X86/oddsubvector.ll
@@ -123,17 +123,16 @@ define <16 x i32> @PR42819(ptr %a0) {
; SSE-NEXT: movdqu (%rdi), %xmm3
; SSE-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7,8,9,10,11]
; SSE-NEXT: xorps %xmm0, %xmm0
-; SSE-NEXT: xorps %xmm1, %xmm1
-; SSE-NEXT: xorps %xmm2, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: retq
;
; AVX-LABEL: PR42819:
; AVX: # %bb.0:
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = mem[0,0,1,2]
-; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm0[5,6,7]
+; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3,4],ymm1[5,6,7]
; AVX-NEXT: retq
;
; AVX512-LABEL: PR42819:
diff --git a/llvm/test/CodeGen/X86/overflow.ll b/llvm/test/CodeGen/X86/overflow.ll
index 5900e7674cd0e..f3768718c2b2d 100644
--- a/llvm/test/CodeGen/X86/overflow.ll
+++ b/llvm/test/CodeGen/X86/overflow.ll
@@ -57,8 +57,8 @@ define i128 @mulhioverflow(i64 %a, i64 %b, i64 %c) nounwind {
; X64-NEXT: mulq %rsi
; X64-NEXT: andl $1, %ecx
; X64-NEXT: addq %rdx, %rcx
-; X64-NEXT: movq %rcx, %rax
; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: movq %rcx, %rax
; X64-NEXT: retq
%1 = zext i64 %a to i128
%2 = zext i64 %b to i128
diff --git a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
index f3741dc202dc5..8751211ee14aa 100644
--- a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
+++ b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
@@ -22,6 +22,7 @@ define i1 @plus_one() nounwind {
; CHECK32-NEXT: je .LBB0_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB0_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -37,6 +38,7 @@ define i1 @plus_one() nounwind {
; CHECK64-NEXT: je .LBB0_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB0_2: # %exit
; CHECK64-NEXT: movb $1, %al
@@ -70,6 +72,7 @@ define i1 @plus_forty_two() nounwind {
; CHECK32-NEXT: je .LBB1_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB1_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -85,6 +88,7 @@ define i1 @plus_forty_two() nounwind {
; CHECK64-NEXT: je .LBB1_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB1_2: # %exit
; CHECK64-NEXT: movb $1, %al
@@ -118,6 +122,7 @@ define i1 @minus_one() nounwind {
; CHECK32-NEXT: je .LBB2_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB2_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -133,6 +138,7 @@ define i1 @minus_one() nounwind {
; CHECK64-NEXT: je .LBB2_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB2_2: # %exit
; CHECK64-NEXT: movb $1, %al
@@ -166,6 +172,7 @@ define i1 @minus_forty_two() nounwind {
; CHECK32-NEXT: je .LBB3_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB3_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -181,6 +188,7 @@ define i1 @minus_forty_two() nounwind {
; CHECK64-NEXT: je .LBB3_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB3_2: # %exit
; CHECK64-NEXT: movb $1, %al
diff --git a/llvm/test/CodeGen/X86/pmulh.ll b/llvm/test/CodeGen/X86/pmulh.ll
index ead7110ae5790..1827682092819 100644
--- a/llvm/test/CodeGen/X86/pmulh.ll
+++ b/llvm/test/CodeGen/X86/pmulh.ll
@@ -2857,7 +2857,7 @@ define <16 x i16> @and_mulhuw_v16i16_shift31(<16 x i32> %a, <16 x i32> %b) {
; SSE-LABEL: and_mulhuw_v16i16_shift31:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
-; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: and_mulhuw_v16i16_shift31:
diff --git a/llvm/test/CodeGen/X86/pr108728.ll b/llvm/test/CodeGen/X86/pr108728.ll
index 75a661891e726..23c7eff837853 100644
--- a/llvm/test/CodeGen/X86/pr108728.ll
+++ b/llvm/test/CodeGen/X86/pr108728.ll
@@ -5,6 +5,7 @@ define i8 @PR108728(i1 %a0) {
; CHECK-LABEL: PR108728:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%sel = select i1 %a0, i8 0, i8 1
%not = xor i8 %sel, -1
diff --git a/llvm/test/CodeGen/X86/pr132844.ll b/llvm/test/CodeGen/X86/pr132844.ll
index dc9f006d93d12..43d12bb721080 100644
--- a/llvm/test/CodeGen/X86/pr132844.ll
+++ b/llvm/test/CodeGen/X86/pr132844.ll
@@ -4,13 +4,13 @@
define { ptr, i8 } @PR132844(<4 x ptr> %0, <4 x ptr> %1) {
; CHECK-LABEL: PR132844:
; CHECK: # %bb.0:
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
-; CHECK-NEXT: vinsertf128 $1, 16, %ymm2, %ymm2
-; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3],ymm0[4,5],ymm2[6,7]
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vinsertf128 $1, 16, %ymm0, %ymm0
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%3 = alloca [35 x ptr], i32 0, align 16
diff --git a/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll b/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll
index c449ec5d3f10b..1f209495d8366 100644
--- a/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll
+++ b/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll
@@ -6,13 +6,13 @@ define <4 x i64> @fold_movsd_zero() {
; X86-LABEL: fold_movsd_zero:
; X86: # %bb.0:
; X86-NEXT: xorps %xmm0, %xmm0
-; X86-NEXT: xorps %xmm1, %xmm1
+; X86-NEXT: movaps %xmm0, %xmm1
; X86-NEXT: retl
;
; X64-LABEL: fold_movsd_zero:
; X64: # %bb.0:
; X64-NEXT: xorps %xmm0, %xmm0
-; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: movaps %xmm0, %xmm1
; X64-NEXT: retq
%insert = insertelement <4 x i64> zeroinitializer, i64 0, i32 0
%shuffle = shufflevector <4 x i64> %insert, <4 x i64> zeroinitializer, <4 x i32> <i32 3, i32 5, i32 7, i32 1>
diff --git a/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll b/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
index 854a36489dfab..d79b07854cae0 100644
--- a/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
+++ b/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
@@ -13,6 +13,7 @@ define i1 @dont_hit_assert(i24 signext %d) {
; CHECK-LABEL: dont_hit_assert:
; CHECK: # %bb.0: # %for.cond
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
for.cond:
%t0 = insertelement <8 x i24> zeroinitializer, i24 1, i32 0
diff --git a/llvm/test/CodeGen/X86/smul-with-overflow.ll b/llvm/test/CodeGen/X86/smul-with-overflow.ll
index df167338268c4..4884a0775443c 100644
--- a/llvm/test/CodeGen/X86/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/smul-with-overflow.ll
@@ -16,6 +16,7 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind {
; X86-NEXT: movl $no, (%esp)
; X86-NEXT: calll printf at PLT
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: addl $12, %esp
; X86-NEXT: retl
; X86-NEXT: .LBB0_1: # %normal
@@ -28,16 +29,17 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind {
;
; X64-LABEL: test1:
; X64: # %bb.0: # %entry
-; X64-NEXT: pushq %rax
+; X64-NEXT: pushq %rbx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: imull %esi, %eax
; X64-NEXT: jno .LBB0_1
; X64-NEXT: # %bb.2: # %overflow
+; X64-NEXT: xorl %ebx, %ebx
; X64-NEXT: movl $no, %edi
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: popq %rcx
+; X64-NEXT: movl %ebx, %eax
+; X64-NEXT: popq %rbx
; X64-NEXT: retq
; X64-NEXT: .LBB0_1: # %normal
; X64-NEXT: movl $ok, %edi
@@ -45,7 +47,7 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
; X64-NEXT: movb $1, %al
-; X64-NEXT: popq %rcx
+; X64-NEXT: popq %rbx
; X64-NEXT: retq
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -73,6 +75,7 @@ define i1 @test2(i32 %v1, i32 %v2) nounwind {
; X86-NEXT: movl $no, (%esp)
; X86-NEXT: calll printf at PLT
; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: addl $12, %esp
; X86-NEXT: retl
; X86-NEXT: .LBB1_2: # %normal
@@ -85,16 +88,17 @@ define i1 @test2(i32 %v1, i32 %v2) nounwind {
;
; X64-LABEL: test2:
; X64: # %bb.0: # %entry
-; X64-NEXT: pushq %rax
+; X64-NEXT: pushq %rbx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: imull %esi, %eax
; X64-NEXT: jno .LBB1_2
; X64-NEXT: # %bb.1: # %overflow
+; X64-NEXT: xorl %ebx, %ebx
; X64-NEXT: movl $no, %edi
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: popq %rcx
+; X64-NEXT: movl %ebx, %eax
+; X64-NEXT: popq %rbx
; X64-NEXT: retq
; X64-NEXT: .LBB1_2: # %normal
; X64-NEXT: movl $ok, %edi
@@ -102,7 +106,7 @@ define i1 @test2(i32 %v1, i32 %v2) nounwind {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
; X64-NEXT: movb $1, %al
-; X64-NEXT: popq %rcx
+; X64-NEXT: popq %rbx
; X64-NEXT: retq
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
diff --git a/llvm/test/CodeGen/X86/sub-with-overflow.ll b/llvm/test/CodeGen/X86/sub-with-overflow.ll
index d3bd3b1cdf0ac..f9a43f7f18edf 100644
--- a/llvm/test/CodeGen/X86/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/sub-with-overflow.ll
@@ -15,6 +15,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: movl $no, (%esp)
; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
@@ -51,6 +52,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: movl $no, (%esp)
; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_1: # %normal
diff --git a/llvm/test/CodeGen/X86/subcarry.ll b/llvm/test/CodeGen/X86/subcarry.ll
index 7d5db07c0172a..2f3774f38a8c6 100644
--- a/llvm/test/CodeGen/X86/subcarry.ll
+++ b/llvm/test/CodeGen/X86/subcarry.ll
@@ -282,8 +282,9 @@ define { i64, i64, i1 } @subcarry_2x64_and_reversed(i64 %x0, i64 %x1, i64 %y0, i
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: sbbq %rcx, %rsi
-; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: movq %rsi, %rdx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
diff --git a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
index f0dc17b556613..71731f91351ca 100644
--- a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
+++ b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
@@ -7,10 +7,10 @@ define i64 @foo() nounwind {
; CHECK-NEXT: cmpl $12, 0
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb65
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1: # %bb56
entry:
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index d9ab2f7d1f5fb..e911daab4b06d 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -196,6 +196,7 @@ define i1 @dont_merge_oddly(ptr %result) nounwind {
; CHECK-NEXT: jbe .LBB2_2
; CHECK-NEXT: .LBB2_4: # %bb26
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
entry:
%tmp4 = getelementptr float, ptr %result, i32 2
diff --git a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
index ecbbaf3ab362d..0d770ba1f6529 100644
--- a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
+++ b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
@@ -137,6 +137,7 @@ define zeroext i1 @zext_i1(i1 %k) {
; CHECK-NEXT: je _foo_i1 ## TAILCALL
; CHECK-NEXT: ## %bb.1: ## %land.end
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
entry:
br i1 %k, label %land.end, label %land.rhs
diff --git a/llvm/test/CodeGen/X86/trunc-to-bool.ll b/llvm/test/CodeGen/X86/trunc-to-bool.ll
index 5a5d057597465..1800eb157603b 100644
--- a/llvm/test/CodeGen/X86/trunc-to-bool.ll
+++ b/llvm/test/CodeGen/X86/trunc-to-bool.ll
@@ -26,6 +26,7 @@ define i1 @test2(i32 %val, i32 %mask) nounwind {
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_2: # %ret_false
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retl
entry:
%shifted = ashr i32 %val, %mask
diff --git a/llvm/test/CodeGen/X86/umul-with-carry.ll b/llvm/test/CodeGen/X86/umul-with-carry.ll
index 787ce2fc57d73..0106e9a3e8d63 100644
--- a/llvm/test/CodeGen/X86/umul-with-carry.ll
+++ b/llvm/test/CodeGen/X86/umul-with-carry.ll
@@ -17,6 +17,7 @@ define i1 @func(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
; CHECK-NEXT: pushl %eax
diff --git a/llvm/test/CodeGen/X86/vec_minmax_sint.ll b/llvm/test/CodeGen/X86/vec_minmax_sint.ll
index 853e29b8acfcd..214e536e17e6d 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_sint.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_sint.ll
@@ -1565,8 +1565,8 @@ define <2 x i64> @max_gt_v2i64c() {
define <4 x i64> @max_gt_v4i64c() {
; SSE-LABEL: max_gt_v4i64c:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: retq
;
; AVX1-LABEL: max_gt_v4i64c:
@@ -1727,8 +1727,8 @@ define <2 x i64> @max_ge_v2i64c() {
define <4 x i64> @max_ge_v4i64c() {
; SSE-LABEL: max_ge_v4i64c:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: retq
;
; AVX1-LABEL: max_ge_v4i64c:
diff --git a/llvm/test/CodeGen/X86/vec_minmax_uint.ll b/llvm/test/CodeGen/X86/vec_minmax_uint.ll
index 9b4da3f9b817f..7a5fb11286251 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_uint.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_uint.ll
@@ -1677,8 +1677,8 @@ define <2 x i64> @max_gt_v2i64c() {
define <4 x i64> @max_gt_v4i64c() {
; SSE-LABEL: max_gt_v4i64c:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: retq
;
; AVX1-LABEL: max_gt_v4i64c:
@@ -1839,8 +1839,8 @@ define <2 x i64> @max_ge_v2i64c() {
define <4 x i64> @max_ge_v4i64c() {
; SSE-LABEL: max_ge_v4i64c:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
; SSE-NEXT: retq
;
; AVX1-LABEL: max_ge_v4i64c:
diff --git a/llvm/test/CodeGen/X86/vec_umulo.ll b/llvm/test/CodeGen/X86/vec_umulo.ll
index 62db6d234d301..131317595a4c7 100644
--- a/llvm/test/CodeGen/X86/vec_umulo.ll
+++ b/llvm/test/CodeGen/X86/vec_umulo.ll
@@ -2857,8 +2857,8 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind {
; SSE-NEXT: pand %xmm1, %xmm0
; SSE-NEXT: pslld $31, %xmm0
; SSE-NEXT: movmskps %xmm0, %eax
-; SSE-NEXT: movb %al, (%rdi)
; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: movb %al, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: umulo_v4i1:
@@ -2866,8 +2866,8 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind {
; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpslld $31, %xmm0, %xmm0
; AVX-NEXT: vmovmskps %xmm0, %eax
-; AVX-NEXT: movb %al, (%rdi)
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: movb %al, (%rdi)
; AVX-NEXT: retq
;
; AVX512F-LABEL: umulo_v4i1:
@@ -2875,9 +2875,9 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind {
; AVX512F-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpslld $31, %xmm0, %xmm0
; AVX512F-NEXT: vptestmd %xmm0, %xmm0, %k0
+; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: movb %al, (%rdi)
-; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: umulo_v4i1:
@@ -2885,9 +2885,9 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind {
; AVX512BW-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpslld $31, %xmm0, %xmm0
; AVX512BW-NEXT: vptestmd %xmm0, %xmm0, %k0
+; AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512BW-NEXT: kmovd %k0, %eax
; AVX512BW-NEXT: movb %al, (%rdi)
-; AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512BW-NEXT: retq
%t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)
%val = extractvalue {<4 x i1>, <4 x i1>} %t, 0
diff --git a/llvm/test/CodeGen/X86/vector-partial-undef.ll b/llvm/test/CodeGen/X86/vector-partial-undef.ll
index 7c12e5295257c..dd6afa65ed203 100644
--- a/llvm/test/CodeGen/X86/vector-partial-undef.ll
+++ b/llvm/test/CodeGen/X86/vector-partial-undef.ll
@@ -80,7 +80,7 @@ define <4 x i64> @and_undef_elts(<2 x i64> %x) {
; SSE-LABEL: and_undef_elts:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
-; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: and_undef_elts:
@@ -99,7 +99,7 @@ define <4 x i64> @or_undef_elts(<2 x i64> %x) {
; SSE-LABEL: or_undef_elts:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: or_undef_elts:
diff --git a/llvm/test/CodeGen/X86/vector-shift-lut.ll b/llvm/test/CodeGen/X86/vector-shift-lut.ll
index 0bf2006090893..cd98553514c97 100644
--- a/llvm/test/CodeGen/X86/vector-shift-lut.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-lut.ll
@@ -1358,98 +1358,98 @@ define <32 x i8> @perlane_ashr_v32i8(<32 x i8> %a) nounwind {
define <64 x i8> @perlane_shl_v64i8(<64 x i8> %a) nounwind {
; SSE2-LABEL: perlane_shl_v64i8:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa %xmm0, %xmm1
-; SSE2-NEXT: psllw $5, %xmm1
-; SSE2-NEXT: pxor %xmm5, %xmm5
-; SSE2-NEXT: pxor %xmm4, %xmm4
-; SSE2-NEXT: pcmpgtb %xmm1, %xmm4
-; SSE2-NEXT: movdqa %xmm4, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm4
+; SSE2-NEXT: psllw $5, %xmm4
+; SSE2-NEXT: xorps %xmm1, %xmm1
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm4, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
-; SSE2-NEXT: por %xmm0, %xmm4
-; SSE2-NEXT: paddb %xmm1, %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; SSE2-NEXT: por %xmm0, %xmm6
+; SSE2-NEXT: paddb %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
+; SSE2-NEXT: pcmpgtb %xmm4, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm7
-; SSE2-NEXT: pandn %xmm4, %xmm7
-; SSE2-NEXT: psllw $2, %xmm4
-; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; SSE2-NEXT: pandn %xmm6, %xmm7
+; SSE2-NEXT: psllw $2, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; SSE2-NEXT: pand %xmm5, %xmm0
; SSE2-NEXT: pand %xmm6, %xmm0
-; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0
-; SSE2-NEXT: paddb %xmm1, %xmm1
-; SSE2-NEXT: pxor %xmm4, %xmm4
-; SSE2-NEXT: pcmpgtb %xmm1, %xmm4
-; SSE2-NEXT: movdqa %xmm4, %xmm1
-; SSE2-NEXT: pandn %xmm0, %xmm1
+; SSE2-NEXT: paddb %xmm4, %xmm4
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm4, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm4
+; SSE2-NEXT: pandn %xmm0, %xmm4
; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: por %xmm1, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
+; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: psllw $5, %xmm3
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm3, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm4
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE2-NEXT: por %xmm4, %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: paddb %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtb %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm7
-; SSE2-NEXT: pandn %xmm1, %xmm7
-; SSE2-NEXT: psllw $2, %xmm1
+; SSE2-NEXT: pandn %xmm6, %xmm7
+; SSE2-NEXT: psllw $2, %xmm6
+; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm4
-; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: por %xmm7, %xmm4
; SSE2-NEXT: paddb %xmm3, %xmm3
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm3, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm3
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm3
; SSE2-NEXT: pandn %xmm4, %xmm3
; SSE2-NEXT: paddb %xmm4, %xmm4
-; SSE2-NEXT: pand %xmm1, %xmm4
+; SSE2-NEXT: pand %xmm6, %xmm4
; SSE2-NEXT: por %xmm3, %xmm4
; SSE2-NEXT: psllw $5, %xmm2
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; SSE2-NEXT: pand %xmm1, %xmm7
-; SSE2-NEXT: paddb %xmm1, %xmm7
-; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE2-NEXT: psubb %xmm1, %xmm7
+; SSE2-NEXT: pxor %xmm3, %xmm3
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm3
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
+; SSE2-NEXT: pand %xmm3, %xmm6
+; SSE2-NEXT: paddb %xmm3, %xmm6
+; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE2-NEXT: psubb %xmm3, %xmm6
; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: pcmpgtb %xmm2, %xmm3
-; SSE2-NEXT: movdqa %xmm3, %xmm1
-; SSE2-NEXT: pandn %xmm7, %xmm1
-; SSE2-NEXT: psllw $2, %xmm7
+; SSE2-NEXT: movdqa %xmm3, %xmm7
+; SSE2-NEXT: pandn %xmm6, %xmm7
+; SSE2-NEXT: psllw $2, %xmm6
+; SSE2-NEXT: pand %xmm5, %xmm3
; SSE2-NEXT: pand %xmm6, %xmm3
-; SSE2-NEXT: pand %xmm7, %xmm3
-; SSE2-NEXT: por %xmm1, %xmm3
+; SSE2-NEXT: por %xmm7, %xmm3
; SSE2-NEXT: paddb %xmm2, %xmm2
+; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtb %xmm2, %xmm5
-; SSE2-NEXT: movdqa %xmm5, %xmm1
-; SSE2-NEXT: pandn %xmm3, %xmm1
+; SSE2-NEXT: movdqa %xmm5, %xmm2
+; SSE2-NEXT: pandn %xmm3, %xmm2
; SSE2-NEXT: paddb %xmm3, %xmm3
; SSE2-NEXT: pand %xmm5, %xmm3
-; SSE2-NEXT: por %xmm1, %xmm3
-; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: por %xmm2, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm4, %xmm3
; SSE2-NEXT: retq
;
; SSE41-LABEL: perlane_shl_v64i8:
; SSE41: # %bb.0:
-; SSE41-NEXT: movq {{.*#+}} xmm4 = [7,14,28,56,112,224,192,128,0,0,0,0,0,0,0,0]
-; SSE41-NEXT: pshufb %xmm0, %xmm4
-; SSE41-NEXT: movq {{.*#+}} xmm5 = [1,2,4,8,16,32,64,128,0,0,0,0,0,0,0,0]
-; SSE41-NEXT: pshufb %xmm2, %xmm5
-; SSE41-NEXT: movq {{.*#+}} xmm6 = [2,4,8,16,32,64,128,0,0,0,0,0,0,0,0,0]
-; SSE41-NEXT: pshufb %xmm3, %xmm6
+; SSE41-NEXT: movq {{.*#+}} xmm6 = [7,14,28,56,112,224,192,128,0,0,0,0,0,0,0,0]
+; SSE41-NEXT: pshufb %xmm0, %xmm6
+; SSE41-NEXT: movq {{.*#+}} xmm4 = [1,2,4,8,16,32,64,128,0,0,0,0,0,0,0,0]
+; SSE41-NEXT: pshufb %xmm2, %xmm4
+; SSE41-NEXT: movq {{.*#+}} xmm5 = [2,4,8,16,32,64,128,0,0,0,0,0,0,0,0,0]
+; SSE41-NEXT: pshufb %xmm3, %xmm5
; SSE41-NEXT: xorps %xmm1, %xmm1
-; SSE41-NEXT: movdqa %xmm4, %xmm0
-; SSE41-NEXT: movdqa %xmm5, %xmm2
-; SSE41-NEXT: movdqa %xmm6, %xmm3
+; SSE41-NEXT: movdqa %xmm6, %xmm0
+; SSE41-NEXT: movdqa %xmm4, %xmm2
+; SSE41-NEXT: movdqa %xmm5, %xmm3
; SSE41-NEXT: retq
;
; AVX1-LABEL: perlane_shl_v64i8:
@@ -1690,61 +1690,61 @@ define <64 x i8> @perlane_ashr_v64i8(<64 x i8> %a) nounwind {
; SSE2-LABEL: perlane_ashr_v64i8:
; SSE2: # %bb.0:
; SSE2-NEXT: psllw $5, %xmm1
-; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: pcmpgtb %xmm1, %xmm4
; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: paddb %xmm1, %xmm5
-; SSE2-NEXT: pxor %xmm4, %xmm4
-; SSE2-NEXT: pxor %xmm6, %xmm6
-; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
-; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: pandn %xmm0, %xmm6
+; SSE2-NEXT: xorps %xmm0, %xmm0
+; SSE2-NEXT: pxor %xmm7, %xmm7
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm7
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: pandn %xmm4, %xmm7
; SSE2-NEXT: paddb %xmm5, %xmm5
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm5, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pandn %xmm6, %xmm5
-; SSE2-NEXT: psrlw $1, %xmm6
-; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; SSE2-NEXT: pand %xmm0, %xmm1
+; SSE2-NEXT: movdqa %xmm1, %xmm4
+; SSE2-NEXT: pandn %xmm7, %xmm4
+; SSE2-NEXT: psrlw $1, %xmm7
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm6, %xmm1
-; SSE2-NEXT: por %xmm5, %xmm1
+; SSE2-NEXT: pand %xmm7, %xmm1
+; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: psllw $5, %xmm2
-; SSE2-NEXT: pxor %xmm5, %xmm5
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm5
-; SSE2-NEXT: paddb %xmm2, %xmm2
-; SSE2-NEXT: pxor %xmm6, %xmm6
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm6
-; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
-; SSE2-NEXT: pandn %xmm5, %xmm6
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtb %xmm2, %xmm5
-; SSE2-NEXT: movdqa %xmm5, %xmm2
-; SSE2-NEXT: pandn %xmm6, %xmm2
-; SSE2-NEXT: psrlw $1, %xmm6
-; SSE2-NEXT: pand %xmm0, %xmm5
-; SSE2-NEXT: pand %xmm6, %xmm5
-; SSE2-NEXT: por %xmm2, %xmm5
+; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: pandn %xmm4, %xmm5
+; SSE2-NEXT: paddb %xmm2, %xmm2
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
+; SSE2-NEXT: movdqa %xmm4, %xmm2
+; SSE2-NEXT: pandn %xmm5, %xmm2
+; SSE2-NEXT: psrlw $1, %xmm5
+; SSE2-NEXT: pand %xmm6, %xmm4
+; SSE2-NEXT: pand %xmm5, %xmm4
+; SSE2-NEXT: por %xmm2, %xmm4
; SSE2-NEXT: psllw $5, %xmm3
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpgtb %xmm3, %xmm2
; SSE2-NEXT: paddb %xmm3, %xmm3
-; SSE2-NEXT: pxor %xmm6, %xmm6
-; SSE2-NEXT: pcmpgtb %xmm3, %xmm6
+; SSE2-NEXT: pxor %xmm7, %xmm7
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm7
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE2-NEXT: pandn %xmm2, %xmm6
+; SSE2-NEXT: pandn %xmm2, %xmm7
; SSE2-NEXT: paddb %xmm3, %xmm3
-; SSE2-NEXT: pcmpgtb %xmm3, %xmm4
-; SSE2-NEXT: movdqa %xmm4, %xmm2
-; SSE2-NEXT: pandn %xmm6, %xmm2
-; SSE2-NEXT: psrlw $1, %xmm6
-; SSE2-NEXT: pand %xmm0, %xmm4
-; SSE2-NEXT: pand %xmm6, %xmm4
-; SSE2-NEXT: por %xmm2, %xmm4
-; SSE2-NEXT: pxor %xmm0, %xmm0
+; SSE2-NEXT: pxor %xmm5, %xmm5
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm2
-; SSE2-NEXT: movdqa %xmm4, %xmm3
+; SSE2-NEXT: pandn %xmm7, %xmm2
+; SSE2-NEXT: psrlw $1, %xmm7
+; SSE2-NEXT: pand %xmm6, %xmm5
+; SSE2-NEXT: pand %xmm7, %xmm5
+; SSE2-NEXT: por %xmm2, %xmm5
+; SSE2-NEXT: movdqa %xmm4, %xmm2
+; SSE2-NEXT: movdqa %xmm5, %xmm3
; SSE2-NEXT: retq
;
; SSE41-LABEL: perlane_ashr_v64i8:
diff --git a/llvm/test/CodeGen/X86/vectorcall.ll b/llvm/test/CodeGen/X86/vectorcall.ll
index 07446c6a7bfa4..07d906ce9960e 100644
--- a/llvm/test/CodeGen/X86/vectorcall.ll
+++ b/llvm/test/CodeGen/X86/vectorcall.ll
@@ -1,35 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=i686-pc-win32 -mattr=+sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=X86
; RUN: llc -mtriple=x86_64-pc-win32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=X64
; Test integer arguments.
define x86_vectorcallcc i32 @test_int_1() {
-; CHECK-LABEL: {{^}}test_int_1@@0:
-; CHECK: xorl %eax, %eax
ret i32 0
}
define x86_vectorcallcc i32 @test_int_2(i32 inreg %a) {
-; X86-LABEL: {{^}}test_int_2@@4:
-; X64-LABEL: {{^}}test_int_2@@8:
-; CHECK: movl %ecx, %eax
ret i32 %a
}
define x86_vectorcallcc i32 @test_int_3(i64 inreg %a) {
-; X86-LABEL: {{^}}test_int_3@@8:
-; X64-LABEL: {{^}}test_int_3@@8:
-; X86: movl %ecx, %eax
-; X64: movq %rcx, %rax
%at = trunc i64 %a to i32
ret i32 %at
}
define x86_vectorcallcc i32 @test_int_4(i32 inreg %a, i32 inreg %b) {
-; X86-LABEL: {{^}}test_int_4@@8:
-; X86: leal (%ecx,%edx), %eax
-; X64-LABEL: {{^}}test_int_4@@16:
-; X64: leal (%rcx,%rdx), %eax
%s = add i32 %a, %b
ret i32 %s
}
@@ -40,23 +28,14 @@ define x86_vectorcallcc i32 @"\01test_int_5"(i32, i32) {
}
define x86_vectorcallcc double @test_fp_1(double %a, double %b) {
-; CHECK-LABEL: {{^}}test_fp_1@@16:
-; CHECK: movaps %xmm1, %xmm0
ret double %b
}
define x86_vectorcallcc double @test_fp_2(double, double, double, double, double, double, double %r) {
-; CHECK-LABEL: {{^}}test_fp_2@@56:
-; CHECK: movsd {{[0-9]+\(%[re]sp\)}}, %xmm0
ret double %r
}
define x86_vectorcallcc {double, double, double, double} @test_fp_3() {
-; CHECK-LABEL: {{^}}test_fp_3@@0:
-; CHECK: xorps %xmm0
-; CHECK: xorps %xmm1
-; CHECK: xorps %xmm2
-; CHECK: xorps %xmm3
ret {double, double, double, double}
{ double 0.0, double 0.0, double 0.0, double 0.0 }
}
@@ -64,26 +43,15 @@ define x86_vectorcallcc {double, double, double, double} @test_fp_3() {
; FIXME: Returning via x87 isn't compatible, but its hard to structure the
; tablegen any other way.
define x86_vectorcallcc {double, double, double, double, double} @test_fp_4() {
-; CHECK-LABEL: {{^}}test_fp_4@@0:
-; CHECK: fldz
-; CHECK: xorps %xmm0
-; CHECK: xorps %xmm1
-; CHECK: xorps %xmm2
-; CHECK: xorps %xmm3
ret {double, double, double, double, double}
{ double 0.0, double 0.0, double 0.0, double 0.0, double 0.0 }
}
define x86_vectorcallcc <16 x i8> @test_vec_1(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: {{^}}test_vec_1@@32:
-; CHECK: movaps %xmm1, %xmm0
ret <16 x i8> %b
}
define x86_vectorcallcc <16 x i8> @test_vec_2(double, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> %r) {
-; CHECK-LABEL: {{^}}test_vec_2@@104:
-; X64: movq {{[0-9]*}}(%rsp), %rax
-; CHECK: movaps (%{{rax|ecx}}), %xmm0
ret <16 x i8> %r
}
@@ -93,10 +61,6 @@ define x86_vectorcallcc <16 x i8> @test_vec_2(double, <16 x i8>, <16 x i8>, <16
%struct.HVA2 = type { <4 x float>, <4 x float> }
define x86_vectorcallcc <4 x float> @test_mixed_1(i32 %a, %struct.HVA4 inreg %bb, i32 %c) {
-; CHECK-LABEL: test_mixed_1
-; CHECK: movaps %xmm1, 16(%{{(e|r)}}sp)
-; CHECK: movaps %xmm1, %xmm0
-; CHECK: ret{{q|l}}
entry:
%b = alloca %struct.HVA4, align 16
store %struct.HVA4 %bb, ptr %b, align 16
@@ -106,10 +70,6 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_2(%struct.HVA4 inreg %a, ptr %b, <4 x float> %c) {
-; CHECK-LABEL: test_mixed_2
-; X86: movaps %xmm0, (%esp)
-; X64: movaps %xmm2, %xmm0
-; CHECK: ret{{[ql]}}
entry:
%c.addr = alloca <4 x float>, align 16
store <4 x float> %c, ptr %c.addr, align 16
@@ -118,19 +78,12 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_3(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, ptr %f) {
-; CHECK-LABEL: test_mixed_3
-; CHECK: movaps (%{{[re][ac]}}x), %xmm0
-; CHECK: ret{{[ql]}}
entry:
%0 = load <4 x float>, ptr %f, align 16
ret <4 x float> %0
}
define x86_vectorcallcc <4 x float> @test_mixed_4(%struct.HVA4 inreg %a, ptr %bb, <4 x float> %c) {
-; CHECK-LABEL: test_mixed_4
-; X86: movaps 16(%eax), %xmm0
-; X64: movaps 16(%rdx), %xmm0
-; CHECK: ret{{[ql]}}
entry:
%y4 = getelementptr inbounds %struct.HVA2, ptr %bb, i32 0, i32 1
%0 = load <4 x float>, ptr %y4, align 16
@@ -138,10 +91,6 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_5(%struct.HVA3 inreg %a, ptr %b, <4 x float> %c, %struct.HVA2 inreg %dd) {
-; CHECK-LABEL: test_mixed_5
-; CHECK-DAG: movaps %xmm{{[0,5]}}, 16(%{{(e|r)}}sp)
-; CHECK-DAG: movaps %xmm5, %xmm0
-; CHECK: ret{{[ql]}}
entry:
%d = alloca %struct.HVA2, align 16
store %struct.HVA2 %dd, ptr %d, align 16
@@ -151,12 +100,6 @@ entry:
}
define x86_vectorcallcc %struct.HVA4 @test_mixed_6(%struct.HVA4 inreg %a, ptr %b) {
-; CHECK-LABEL: test_mixed_6
-; CHECK: movaps (%{{[re]}}sp), %xmm0
-; CHECK: movaps 16(%{{[re]}}sp), %xmm1
-; CHECK: movaps 32(%{{[re]}}sp), %xmm2
-; CHECK: movaps 48(%{{[re]}}sp), %xmm3
-; CHECK: ret{{[ql]}}
entry:
%retval = alloca %struct.HVA4, align 16
call void @llvm.memcpy.p0.p0.i32(ptr align 16 %retval, ptr align 16 %b, i32 64, i1 false)
@@ -169,14 +112,6 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado
declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1)
define x86_vectorcallcc void @test_mixed_7(ptr noalias sret(%struct.HVA5) %agg.result) {
-; CHECK-LABEL: test_mixed_7@@0
-; X64: mov{{[ql]}} %rcx, %rax
-; CHECK: movaps %xmm{{[0-9]}}, 64(%{{rcx|eax}})
-; CHECK: movaps %xmm{{[0-9]}}, 48(%{{rcx|eax}})
-; CHECK: movaps %xmm{{[0-9]}}, 32(%{{rcx|eax}})
-; CHECK: movaps %xmm{{[0-9]}}, 16(%{{rcx|eax}})
-; CHECK: movaps %xmm{{[0-9]}}, (%{{rcx|eax}})
-; CHECK: ret{{[ql]}}
entry:
%a = alloca %struct.HVA5, align 16
call void @llvm.memset.p0.i64(ptr align 16 %a, i8 0, i64 80, i1 false)
@@ -185,10 +120,6 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_8(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, i32 %e, <4 x float> %f) {
-; CHECK-LABEL: test_mixed_8
-; X86: movaps %xmm4, %xmm0
-; X64: movaps %xmm5, %xmm0
-; CHECK: ret{{[ql]}}
entry:
%f.addr = alloca <4 x float>, align 16
store <4 x float> %f, ptr %f.addr, align 16
@@ -200,17 +131,13 @@ entry:
declare x86_vectorcallcc double @test_mixed_9_callee(%struct.HFA4 %x, double %y)
define x86_vectorcallcc double @test_mixed_9_caller(%struct.HFA4 inreg %b) {
-; CHECK-LABEL: test_mixed_9_caller
-; CHECK: movaps %xmm3, %xmm4
-; CHECK: movaps %xmm2, %xmm3
-; CHECK: movaps %xmm1, %xmm2
; X32: movasd %xmm0, %xmm1
-; X64: movap{{d|s}} %xmm5, %xmm1
-; CHECK: call{{l|q}} test_mixed_9_callee@@40
-; CHECK: addsd {{.*}}, %xmm0
-; CHECK: ret{{l|q}}
entry:
%call = call x86_vectorcallcc double @test_mixed_9_callee(%struct.HFA4 inreg %b, double 3.000000e+00)
%add = fadd double 1.000000e+00, %call
ret double %add
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
+; X64: {{.*}}
+; X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll
index c2a8002c949ce..914b2f7e1ff69 100644
--- a/llvm/test/CodeGen/X86/xaluo.ll
+++ b/llvm/test/CodeGen/X86/xaluo.ll
@@ -647,6 +647,7 @@ define zeroext i1 @saddobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB31_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: saddobri32:
@@ -684,6 +685,7 @@ define zeroext i1 @saddobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB32_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: saddobri64:
@@ -721,6 +723,7 @@ define zeroext i1 @uaddobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB33_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: uaddobri32:
@@ -758,6 +761,7 @@ define zeroext i1 @uaddobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB34_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: uaddobri64:
@@ -795,6 +799,7 @@ define zeroext i1 @ssubobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB35_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: ssubobri32:
@@ -832,6 +837,7 @@ define zeroext i1 @ssubobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB36_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: ssubobri64:
@@ -869,6 +875,7 @@ define zeroext i1 @usubobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB37_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: usubobri32:
@@ -906,6 +913,7 @@ define zeroext i1 @usubobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB38_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: usubobri64:
@@ -940,6 +948,7 @@ define {i64, i1} @saddoovf(i64 %a, i64 %b) {
; CHECK-NEXT: shrq $31, %rsi
; CHECK-NEXT: leaq (%rsi,%rdi), %rax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%1 = ashr i64 %a, 17
%2 = lshr i64 %b, 31
@@ -954,6 +963,7 @@ define {i64, i1} @ssuboovf(i64 %a, i64 %b) {
; CHECK-NEXT: shrq $22, %rsi
; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%1 = and i64 %a, 65535
%2 = lshr i64 %b, 22
@@ -968,6 +978,7 @@ define {i64, i1} @uaddoovf(i64 %a, i64 %b) {
; CHECK-NEXT: movzbl %sil, %eax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%1 = and i64 %a, 255
%2 = and i64 %b, 255
@@ -981,6 +992,7 @@ define {i64, i1} @usuboovf(i64 %a, i64 %b) {
; CHECK-NEXT: movq %rsi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%t0 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %a)
%v0 = extractvalue {i64, i1} %t0, 0
diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll
index a076d0d762aa3..1387361e4f0c9 100644
--- a/llvm/test/CodeGen/X86/xmulo.ll
+++ b/llvm/test/CodeGen/X86/xmulo.ll
@@ -8,15 +8,17 @@
define {i64, i1} @t1() nounwind {
; CHECK-LABEL: t1:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl $72, %eax
; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl $72, %eax
+; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
;
; WIN32-LABEL: t1:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl $72, %eax
-; WIN32-NEXT: xorl %edx, %edx
; WIN32-NEXT: xorl %ecx, %ecx
+; WIN32-NEXT: movl $72, %eax
+; WIN32-NEXT: movl %ecx, %edx
+; WIN32-NEXT: # kill: def $cl killed $cl killed $ecx
; WIN32-NEXT: retl
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 8)
ret {i64, i1} %1
@@ -26,14 +28,14 @@ define {i64, i1} @t2() nounwind {
; CHECK-LABEL: t2:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: retq
;
; WIN32-LABEL: t2:
; WIN32: # %bb.0:
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: xorl %edx, %edx
-; WIN32-NEXT: xorl %ecx, %ecx
+; WIN32-NEXT: movl %eax, %edx
+; WIN32-NEXT: movl %eax, %ecx
; WIN32-NEXT: retl
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 0)
ret {i64, i1} %1
@@ -737,6 +739,7 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB15_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri8:
@@ -767,6 +770,7 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB15_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri8:
@@ -779,6 +783,7 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB15_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 %v1, i8 %v2)
%val = extractvalue {i8, i1} %t, 0
@@ -802,6 +807,7 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB16_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri16:
@@ -829,6 +835,7 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB16_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri16:
@@ -841,6 +848,7 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB16_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %v1, i16 %v2)
%val = extractvalue {i16, i1} %t, 0
@@ -864,6 +872,7 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB17_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri32:
@@ -889,6 +898,7 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB17_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri32:
@@ -901,6 +911,7 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB17_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -924,6 +935,7 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB18_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri64:
@@ -949,6 +961,7 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB18_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri64:
@@ -999,9 +1012,9 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: xorl %eax, %esi
; WIN32-NEXT: orl %edx, %esi
; WIN32-NEXT: jne LBB18_1
-; WIN32-NEXT: # %bb.3: # %continue
+; WIN32-NEXT: # %bb.2: # %continue
; WIN32-NEXT: movb $1, %al
-; WIN32-NEXT: LBB18_2: # %overflow
+; WIN32-NEXT: LBB18_3: # %continue
; WIN32-NEXT: addl $4, %esp
; WIN32-NEXT: popl %esi
; WIN32-NEXT: popl %edi
@@ -1010,7 +1023,8 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB18_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: jmp LBB18_2
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
+; WIN32-NEXT: jmp LBB18_3
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -1035,6 +1049,7 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB19_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri8:
@@ -1065,6 +1080,7 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB19_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri8:
@@ -1077,6 +1093,7 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB19_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %v1, i8 %v2)
%val = extractvalue {i8, i1} %t, 0
@@ -1102,6 +1119,7 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB20_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri16:
@@ -1132,6 +1150,7 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB20_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri16:
@@ -1144,6 +1163,7 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB20_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %v1, i16 %v2)
%val = extractvalue {i16, i1} %t, 0
@@ -1168,6 +1188,7 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB21_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri32:
@@ -1195,6 +1216,7 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB21_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri32:
@@ -1207,6 +1229,7 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB21_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -1231,6 +1254,7 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB22_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
+; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri64:
@@ -1258,6 +1282,7 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB22_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
+; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri64:
@@ -1290,9 +1315,9 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: orb %ch, %al
; WIN32-NEXT: subb $1, %al
; WIN32-NEXT: je LBB22_1
-; WIN32-NEXT: # %bb.3: # %continue
+; WIN32-NEXT: # %bb.2: # %continue
; WIN32-NEXT: movb $1, %al
-; WIN32-NEXT: LBB22_2: # %overflow
+; WIN32-NEXT: LBB22_3: # %continue
; WIN32-NEXT: popl %esi
; WIN32-NEXT: popl %edi
; WIN32-NEXT: popl %ebx
@@ -1300,7 +1325,8 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB22_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: jmp LBB22_2
+; WIN32-NEXT: # kill: def $al killed $al killed $eax
+; WIN32-NEXT: jmp LBB22_3
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
index 30c3bd27b0a2a..f10b9fdaa6b0e 100644
--- a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
+++ b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -start-before=register-coalescer -stop-after=register-coalescer | FileCheck %s
--- |
@@ -40,6 +41,12 @@ registers:
- { id: 0, class: gr32, preferred-register: '' }
body: |
bb.0.entry:
+ ; CHECK-LABEL: name: main
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, debug-location !DILocation(line: 14, column: 11, scope: <0x{{[0-9a-f]+}}>)
+ ; CHECK-NEXT: DBG_VALUE [[MOV32r0_]], $noreg, <0x{{[0-9a-f]+}}>, !DIExpression(), debug-location !DILocation(line: 13, column: 7, scope: <0x{{[0-9a-f]+}}>)
+ ; CHECK-NEXT: DBG_VALUE [[MOV32r0_]], $noreg, <0x{{[0-9a-f]+}}>, !DIExpression(), debug-location !DILocation(line: 16, column: 3, scope: <0x{{[0-9a-f]+}}>)
+ ; CHECK-NEXT: $eax = COPY [[MOV32r0_]], debug-location !DILocation(line: 16, column: 3, scope: <0x{{[0-9a-f]+}}>)
+ ; CHECK-NEXT: RET 0, killed $eax, debug-location !DILocation(line: 16, column: 3, scope: <0x{{[0-9a-f]+}}>)
%0 = MOV32r0 implicit-def dead $eflags, debug-location !20
DBG_VALUE %0, _, !18, !DIExpression(), debug-location !21
DBG_VALUE %0, _, !19, !DIExpression(), debug-location !22
@@ -47,7 +54,3 @@ body: |
RET 0, killed $eax, debug-location !22
...
-
-# CHECK: $eax = MOV32r0
-# CHECK-NEXT: DBG_VALUE $eax
-# CHECK-NEXT: DBG_VALUE $eax
diff --git a/llvm/test/Other/machine-size-remarks.ll b/llvm/test/Other/machine-size-remarks.ll
index 90d081ea8a60c..20c7a21c6c0e4 100644
--- a/llvm/test/Other/machine-size-remarks.ll
+++ b/llvm/test/Other/machine-size-remarks.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; REQUIRES: x86-registered-target
; RUN: llc -mtriple x86_64-apple-darwin %s -pass-remarks-analysis='size-info'\
; RUN: -pass-remarks-output=%t.yaml -o /dev/null < %s 2> %t; \
@@ -15,7 +16,7 @@
; CHECK: remark: <unknown>:0:0: X86 DAG->DAG Instruction Selection: Function:
; CHECK-SAME: main: MI Instruction count changed from 0
; CHECK-SAME: to [[INIT:[1-9][0-9]*]]; Delta: [[INIT]]
-; CHECK-NEXT: remark: <unknown>:0:0: Register Coalescer: Function: main:
+; CHECK-NEXT: remark: <unknown>:0:0: Virtual Register Rewriter: Function: main:
; CHECK-SAME: MI Instruction count changed from [[INIT]] to
; CHECK-SAME: [[FINAL:[1-9][0-9]*]];
; CHECK-SAME: Delta: [[DELTA:-?[1-9][0-9]*]]
@@ -39,7 +40,7 @@
; CHECK-NEXT: Name: FunctionMISizeChange
; CHECK-NEXT: Function: main
; CHECK-NEXT: Args:
-; CHECK-NEXT: - Pass: Register Coalescer
+; CHECK-NEXT: - Pass: Virtual Register Rewriter
; CHECK-NEXT: - String: ': Function: '
; CHECK-NEXT: - Function: main
; CHECK-NEXT: - String: ': '
@@ -57,3 +58,5 @@ entry:
}
attributes #0 = { noinline nounwind optnone ssp uwtable }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
>From 813479a407727ad7c924ac69b40b7bb7cb263c45 Mon Sep 17 00:00:00 2001
From: rez5427 <guanjian at stu.cdut.edu.cn>
Date: Mon, 13 Oct 2025 22:00:59 +0800
Subject: [PATCH 2/4] update tests
---
clang/test/CodeGen/msp430-abi-complex.c | 2 +-
llvm/lib/CodeGen/RegisterCoalescer.cpp | 30 +
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 978 +-----------------
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 1 +
.../AMDGPU/llvm.amdgcn.bitreplicate.ll | 10 -
.../AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll | 31 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll | 10 -
...st-and-by-const-from-lshr-in-eqcmp-zero.ll | 40 +-
...ist-and-by-const-from-shl-in-eqcmp-zero.ll | 40 +-
llvm/test/CodeGen/ARM/readcyclecounter.ll | 8 +-
llvm/test/CodeGen/ARM/select_const.ll | 4 +-
.../CodeGen/AVR/calling-conv/c/return_aggr.ll | 29 +-
llvm/test/CodeGen/BPF/BTF/filename.ll | 17 +
llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll | 19 +
llvm/test/CodeGen/BPF/fi_ri.ll | 19 +-
llvm/test/CodeGen/BPF/inlineasm-wreg.ll | 22 +-
llvm/test/CodeGen/BPF/rodata_1.ll | 22 +-
llvm/test/CodeGen/BPF/rodata_2.ll | 28 +-
.../CodeGen/LoongArch/calling-conv-lp64d.ll | 1 +
llvm/test/CodeGen/LoongArch/double-imm.ll | 1 +
llvm/test/CodeGen/LoongArch/float-imm-vldi.ll | 512 +++++++++
llvm/test/CodeGen/Mips/cmov.ll | 654 ++++++++++++
llvm/test/CodeGen/Mips/llvm-ir/and.ll | 164 +--
llvm/test/CodeGen/Mips/mips64-f128.ll | 24 +-
llvm/test/CodeGen/Mips/readcyclecounter.ll | 13 +-
.../CodeGen/PowerPC/2008-05-01-ppc_fp128.ll | 12 +
.../PowerPC/2008-07-15-SignExtendInreg.ll | 9 +
llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll | 6 +
llvm/test/CodeGen/PowerPC/aix-dwarf.ll | 13 +-
llvm/test/CodeGen/PowerPC/llc_default_cpu.ll | 76 ++
.../test/CodeGen/PowerPC/register-pressure.ll | 47 +-
llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll | 98 +-
.../CodeGen/X86/2006-04-27-ISelFoldingBug.ll | 1 -
.../test/CodeGen/X86/2007-02-16-BranchFold.ll | 1 -
.../X86/2007-10-12-CoalesceExtSubReg.ll | 1 -
.../CodeGen/X86/2007-10-12-SpillerUnfold2.ll | 1 -
.../CodeGen/X86/2007-10-29-ExtendSetCC.ll | 1 -
llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll | 1 -
llvm/test/CodeGen/X86/add.ll | 6 -
llvm/test/CodeGen/X86/addcarry.ll | 3 +-
llvm/test/CodeGen/X86/apx/ccmp.ll | 10 -
llvm/test/CodeGen/X86/apx/ctest.ll | 10 -
llvm/test/CodeGen/X86/apx/imulzu.ll | 1 -
llvm/test/CodeGen/X86/atomic-unordered.ll | 39 +-
llvm/test/CodeGen/X86/cmp.ll | 1 -
.../X86/coalescer-implicit-def-regression.ll | 12 +-
llvm/test/CodeGen/X86/combine-mulo.ll | 1 -
llvm/test/CodeGen/X86/combine-srem.ll | 1 -
llvm/test/CodeGen/X86/combine-subo.ll | 1 -
llvm/test/CodeGen/X86/combine-urem.ll | 1 -
llvm/test/CodeGen/X86/divmod128.ll | 32 +-
llvm/test/CodeGen/X86/fast-isel-fcmp.ll | 3 -
llvm/test/CodeGen/X86/fast-isel-load-i1.ll | 1 -
...st-and-by-const-from-lshr-in-eqcmp-zero.ll | 1 -
llvm/test/CodeGen/X86/i128-immediate.ll | 2 +-
llvm/test/CodeGen/X86/int-to-fp-demanded.ll | 3 +-
llvm/test/CodeGen/X86/is_fpclass.ll | 2 -
llvm/test/CodeGen/X86/isel-fpclass.ll | 11 -
llvm/test/CodeGen/X86/knownbits-div.ll | 2 -
.../X86/lack-of-signed-truncation-check.ll | 1 -
llvm/test/CodeGen/X86/memcmp-constant.ll | 4 -
.../CodeGen/X86/memcmp-more-load-pairs-x32.ll | 1 -
.../CodeGen/X86/memcmp-more-load-pairs.ll | 1 -
llvm/test/CodeGen/X86/memcmp-x32.ll | 1 -
llvm/test/CodeGen/X86/memcmp.ll | 1 -
llvm/test/CodeGen/X86/negate.ll | 1 -
llvm/test/CodeGen/X86/overflow.ll | 2 +-
.../X86/peephole-na-phys-copy-folding.ll | 8 -
llvm/test/CodeGen/X86/pr108728.ll | 1 -
llvm/test/CodeGen/X86/pr132844.ll | 10 +-
llvm/test/CodeGen/X86/pr61348.ll | 15 +-
.../CodeGen/X86/shuffle-combine-crash-3.ll | 1 -
llvm/test/CodeGen/X86/smul-with-overflow.ll | 20 +-
llvm/test/CodeGen/X86/sub-with-overflow.ll | 2 -
llvm/test/CodeGen/X86/subcarry.ll | 3 +-
llvm/test/CodeGen/X86/subreg-to-reg-6.ll | 2 +-
llvm/test/CodeGen/X86/tail-opts.ll | 1 -
llvm/test/CodeGen/X86/tailcall-cgp-dup.ll | 1 -
llvm/test/CodeGen/X86/trunc-to-bool.ll | 1 -
llvm/test/CodeGen/X86/umul-with-carry.ll | 1 -
llvm/test/CodeGen/X86/xaluo.ll | 12 -
llvm/test/CodeGen/X86/xmulo.ll | 50 +-
llvm/test/DebugInfo/ARM/constant-dbgloc.ll | 3 +
llvm/test/DebugInfo/MIR/X86/regcoalescer.mir | 9 +-
llvm/test/DebugInfo/XCOFF/empty-prolog.ll | 3 +-
llvm/test/DebugInfo/XCOFF/empty.ll | 20 +
llvm/test/DebugInfo/XCOFF/explicit-section.ll | 25 +
.../test/DebugInfo/XCOFF/function-sections.ll | 5 +-
...dgpu_generated_funcs.ll.generated.expected | 31 +-
...pu_generated_funcs.ll.nogenerated.expected | 31 +-
.../arm_generated_funcs.ll.generated.expected | 17 +-
...rm_generated_funcs.ll.nogenerated.expected | 17 +-
...p430_generated_funcs.ll.generated.expected | 4 +-
...30_generated_funcs.ll.nogenerated.expected | 4 +-
.../ppc_generated_funcs.ll.generated.expected | 56 +-
...pc_generated_funcs.ll.nogenerated.expected | 56 +-
temp | 178 ++++
97 files changed, 2052 insertions(+), 1636 deletions(-)
create mode 100644 temp
diff --git a/clang/test/CodeGen/msp430-abi-complex.c b/clang/test/CodeGen/msp430-abi-complex.c
index faafcd2cde3f8..8fc0d6d97ce64 100644
--- a/clang/test/CodeGen/msp430-abi-complex.c
+++ b/clang/test/CodeGen/msp430-abi-complex.c
@@ -202,7 +202,7 @@ float _Complex complex_float_res(void) {
// CHECK-DAG: clr r12
// CHECK-DAG: mov #16256, r13
__imag__ res = -1;
-// CHECK-DAG: clr r14
+// CHECK-DAG: mov r12, r14
// CHECK-DAG: mov #-16512, r15
return res;
// CHECK: ret
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 97d16f89a9da3..a02edc0d82487 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1328,6 +1328,8 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
// Skip rematerialization for physical registers used as return values within
// the same basic block to enable better coalescing.
+
+
if (DstReg.isPhysical()) {
MachineBasicBlock *MBB = CopyMI->getParent();
if (DefMI->getParent() == MBB) {
@@ -1351,6 +1353,34 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
break;
// If there's a return instruction that uses this register, skip remat
if (MI.isReturn() && MI.readsRegister(DstReg, TRI)) {
+ // Exception: if DefMI is moving a constant and SrcReg has no other uses
+ // (besides copies), rematerialization is beneficial to eliminate the def
+ if (DefMI->isMoveImmediate()) {
+ // Quick check: if there's only one use and it's this copy, definitely remat
+ if (MRI->hasOneNonDBGUse(SrcReg)) {
+ LLVM_DEBUG(dbgs() << "\tAllow remat: single use constant move\n");
+ break;
+ }
+
+ // Check all uses to see if they're all copies
+ bool OnlyUsedByCopies = true;
+ unsigned UseCount = 0;
+ for (const MachineOperand &MO : MRI->use_operands(SrcReg)) {
+ const MachineInstr *UseMI = MO.getParent(); // 改为 const
+ if (!UseMI->isCopy() && !UseMI->isSubregToReg()) {
+ OnlyUsedByCopies = false;
+ break;
+ }
+ UseCount++;
+ }
+
+ if (OnlyUsedByCopies && UseCount > 0) {
+ LLVM_DEBUG(dbgs() << "\tAllow remat: constant move only used by "
+ << UseCount << " copies\n");
+ break; // Allow rematerialization
+ }
+ }
+
LLVM_DEBUG(dbgs() << "\tSkip remat for return register: "
<< printReg(DstReg, TRI) << '\n');
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 4df82946343b5..56cb36294c055 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=amdgpu-attributor -mcpu=kaveri -mattr=-promote-alloca < %s | llc | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
; RUN: opt -passes=amdgpu-attributor -mcpu=gfx900 -mattr=-promote-alloca < %s | llc | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
@@ -416,1174 +417,201 @@ define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast_1(ptr addrspa
}
define <2 x ptr addrspace(5)> @addrspacecast_v2p0_to_v2p5(<2 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v2p0_to_v2p5:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(5)>
ret <2 x ptr addrspace(5)> %cast
}
define <3 x ptr addrspace(5)> @addrspacecast_v3p0_to_v3p5(<3 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v3p0_to_v3p5:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(5)>
ret <3 x ptr addrspace(5)> %cast
}
define <4 x ptr addrspace(5)> @addrspacecast_v4p0_to_v4p5(<4 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v4p0_to_v4p5:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(5)>
ret <4 x ptr addrspace(5)> %cast
}
define <8 x ptr addrspace(5)> @addrspacecast_v8p0_to_v8p5(<8 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v8p0_to_v8p5:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
-; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15]
-; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(5)>
ret <8 x ptr addrspace(5)> %cast
}
define <16 x ptr addrspace(5)> @addrspacecast_v16p0_to_v16p5(<16 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v16p0_to_v16p5:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
-; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15]
-; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[16:17]
-; HSA-NEXT: v_cndmask_b32_e32 v8, -1, v16, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19]
-; HSA-NEXT: v_cndmask_b32_e32 v9, -1, v18, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[20:21]
-; HSA-NEXT: v_cndmask_b32_e32 v10, -1, v20, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[22:23]
-; HSA-NEXT: v_cndmask_b32_e32 v11, -1, v22, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[24:25]
-; HSA-NEXT: v_cndmask_b32_e32 v12, -1, v24, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[26:27]
-; HSA-NEXT: v_cndmask_b32_e32 v13, -1, v26, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[28:29]
-; HSA-NEXT: v_cndmask_b32_e32 v14, -1, v28, vcc
-; HSA-NEXT: s_waitcnt vmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[30:31]
-; HSA-NEXT: v_cndmask_b32_e32 v15, -1, v30, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(5)>
ret <16 x ptr addrspace(5)> %cast
}
define <2 x ptr> @addrspacecast_v2p5_to_v2p0(<2 x ptr addrspace(5)> %ptr) {
-; CI-LABEL: addrspacecast_v2p5_to_v2p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x11
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v3, s4
-; CI-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v4
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v2p5_to_v2p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v4
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr addrspace(5)> %ptr to <2 x ptr>
ret <2 x ptr> %cast
}
define <3 x ptr> @addrspacecast_v3p5_to_v3p0(<3 x ptr addrspace(5)> %ptr) {
-; CI-LABEL: addrspacecast_v3p5_to_v3p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x11
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v5, s4
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v7
-; CI-NEXT: v_mov_b32_e32 v2, v6
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v3p5_to_v3p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v5, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v7
-; GFX9-NEXT: v_mov_b32_e32 v2, v6
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <3 x ptr addrspace(5)> %ptr to <3 x ptr>
ret <3 x ptr> %cast
}
define <4 x ptr> @addrspacecast_v4p5_to_v4p0(<4 x ptr addrspace(5)> %ptr) {
-; CI-LABEL: addrspacecast_v4p5_to_v4p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x11
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v7, s4
-; CI-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v10
-; CI-NEXT: v_mov_b32_e32 v2, v8
-; CI-NEXT: v_mov_b32_e32 v3, v9
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v4p5_to_v4p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v7, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v10
-; GFX9-NEXT: v_mov_b32_e32 v2, v8
-; GFX9-NEXT: v_mov_b32_e32 v3, v9
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr addrspace(5)> %ptr to <4 x ptr>
ret <4 x ptr> %cast
}
define <8 x ptr> @addrspacecast_v8p5_to_v8p0(<8 x ptr addrspace(5)> %ptr) {
-; CI-LABEL: addrspacecast_v8p5_to_v8p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x11
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v15, s4
-; CI-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4
-; CI-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; CI-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5
-; CI-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc
-; CI-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6
-; CI-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc
-; CI-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7
-; CI-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc
-; CI-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v22
-; CI-NEXT: v_mov_b32_e32 v2, v16
-; CI-NEXT: v_mov_b32_e32 v3, v17
-; CI-NEXT: v_mov_b32_e32 v4, v18
-; CI-NEXT: v_mov_b32_e32 v5, v19
-; CI-NEXT: v_mov_b32_e32 v6, v20
-; CI-NEXT: v_mov_b32_e32 v7, v21
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v8p5_to_v8p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v15, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v22
-; GFX9-NEXT: v_mov_b32_e32 v2, v16
-; GFX9-NEXT: v_mov_b32_e32 v3, v17
-; GFX9-NEXT: v_mov_b32_e32 v4, v18
-; GFX9-NEXT: v_mov_b32_e32 v5, v19
-; GFX9-NEXT: v_mov_b32_e32 v6, v20
-; GFX9-NEXT: v_mov_b32_e32 v7, v21
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr addrspace(5)> %ptr to <8 x ptr>
ret <8 x ptr> %cast
}
define <16 x ptr> @addrspacecast_v16p5_to_v16p0(<16 x ptr addrspace(5)> %ptr) {
-; CI-LABEL: addrspacecast_v16p5_to_v16p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x11
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v31, s4
-; CI-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v34, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v39, 0, v31, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
-; CI-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
-; CI-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
-; CI-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
-; CI-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; CI-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
-; CI-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
-; CI-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
-; CI-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
-; CI-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
-; CI-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
-; CI-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
-; CI-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
-; CI-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
-; CI-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[6:7]
-; CI-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[8:9]
-; CI-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[10:11]
-; CI-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[12:13]
-; CI-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[14:15]
-; CI-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[16:17]
-; CI-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[18:19]
-; CI-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[20:21]
-; CI-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[22:23]
-; CI-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[24:25]
-; CI-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[26:27]
-; CI-NEXT: v_mov_b32_e32 v1, v49
-; CI-NEXT: v_mov_b32_e32 v2, v34
-; CI-NEXT: v_mov_b32_e32 v3, v39
-; CI-NEXT: v_mov_b32_e32 v4, v35
-; CI-NEXT: v_mov_b32_e32 v5, v32
-; CI-NEXT: v_mov_b32_e32 v6, v36
-; CI-NEXT: v_mov_b32_e32 v8, v48
-; CI-NEXT: v_mov_b32_e32 v10, v37
-; CI-NEXT: v_mov_b32_e32 v12, v33
-; CI-NEXT: v_mov_b32_e32 v14, v38
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v16p5_to_v16p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v31, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v34, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v39, 0, v31, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
-; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
-; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
-; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
-; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
-; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
-; GFX9-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
-; GFX9-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[10:11]
-; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[14:15]
-; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[16:17]
-; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[18:19]
-; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[20:21]
-; GFX9-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[22:23]
-; GFX9-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[24:25]
-; GFX9-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[26:27]
-; GFX9-NEXT: v_mov_b32_e32 v1, v49
-; GFX9-NEXT: v_mov_b32_e32 v2, v34
-; GFX9-NEXT: v_mov_b32_e32 v3, v39
-; GFX9-NEXT: v_mov_b32_e32 v4, v35
-; GFX9-NEXT: v_mov_b32_e32 v5, v32
-; GFX9-NEXT: v_mov_b32_e32 v6, v36
-; GFX9-NEXT: v_mov_b32_e32 v8, v48
-; GFX9-NEXT: v_mov_b32_e32 v10, v37
-; GFX9-NEXT: v_mov_b32_e32 v12, v33
-; GFX9-NEXT: v_mov_b32_e32 v14, v38
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr addrspace(5)> %ptr to <16 x ptr>
ret <16 x ptr> %cast
}
define <2 x ptr addrspace(3)> @addrspacecast_v2p0_to_v2p3(<2 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v2p0_to_v2p3:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(3)>
ret <2 x ptr addrspace(3)> %cast
}
define <3 x ptr addrspace(3)> @addrspacecast_v3p0_to_v3p3(<3 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v3p0_to_v3p3:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(3)>
ret <3 x ptr addrspace(3)> %cast
}
define <4 x ptr addrspace(3)> @addrspacecast_v4p0_to_v4p3(<4 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v4p0_to_v4p3:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(3)>
ret <4 x ptr addrspace(3)> %cast
}
define <8 x ptr addrspace(3)> @addrspacecast_v8p0_to_v8p3(<8 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v8p0_to_v8p3:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
-; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15]
-; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(3)>
ret <8 x ptr addrspace(3)> %cast
}
define <16 x ptr addrspace(3)> @addrspacecast_v16p0_to_v16p3(<16 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v16p0_to_v16p3:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
-; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15]
-; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[16:17]
-; HSA-NEXT: v_cndmask_b32_e32 v8, -1, v16, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19]
-; HSA-NEXT: v_cndmask_b32_e32 v9, -1, v18, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[20:21]
-; HSA-NEXT: v_cndmask_b32_e32 v10, -1, v20, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[22:23]
-; HSA-NEXT: v_cndmask_b32_e32 v11, -1, v22, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[24:25]
-; HSA-NEXT: v_cndmask_b32_e32 v12, -1, v24, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[26:27]
-; HSA-NEXT: v_cndmask_b32_e32 v13, -1, v26, vcc
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[28:29]
-; HSA-NEXT: v_cndmask_b32_e32 v14, -1, v28, vcc
-; HSA-NEXT: s_waitcnt vmcnt(0)
-; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[30:31]
-; HSA-NEXT: v_cndmask_b32_e32 v15, -1, v30, vcc
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(3)>
ret <16 x ptr addrspace(3)> %cast
}
define <2 x ptr> @addrspacecast_v2p3_to_v2p0(<2 x ptr addrspace(3)> %ptr) {
-; CI-LABEL: addrspacecast_v2p3_to_v2p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x10
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v3, s4
-; CI-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v4
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v2p3_to_v2p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v4
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr addrspace(3)> %ptr to <2 x ptr>
ret <2 x ptr> %cast
}
define <3 x ptr> @addrspacecast_v3p3_to_v3p0(<3 x ptr addrspace(3)> %ptr) {
-; CI-LABEL: addrspacecast_v3p3_to_v3p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x10
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v5, s4
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v7
-; CI-NEXT: v_mov_b32_e32 v2, v6
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v3p3_to_v3p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v5, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v7
-; GFX9-NEXT: v_mov_b32_e32 v2, v6
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <3 x ptr addrspace(3)> %ptr to <3 x ptr>
ret <3 x ptr> %cast
}
define <4 x ptr> @addrspacecast_v4p3_to_v4p0(<4 x ptr addrspace(3)> %ptr) {
-; CI-LABEL: addrspacecast_v4p3_to_v4p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x10
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v7, s4
-; CI-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v10
-; CI-NEXT: v_mov_b32_e32 v2, v8
-; CI-NEXT: v_mov_b32_e32 v3, v9
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v4p3_to_v4p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v7, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v10
-; GFX9-NEXT: v_mov_b32_e32 v2, v8
-; GFX9-NEXT: v_mov_b32_e32 v3, v9
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr addrspace(3)> %ptr to <4 x ptr>
ret <4 x ptr> %cast
}
define <8 x ptr> @addrspacecast_v8p3_to_v8p0(<8 x ptr addrspace(3)> %ptr) {
-; CI-LABEL: addrspacecast_v8p3_to_v8p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x10
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v15, s4
-; CI-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4
-; CI-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; CI-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5
-; CI-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc
-; CI-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6
-; CI-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc
-; CI-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7
-; CI-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc
-; CI-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
-; CI-NEXT: v_mov_b32_e32 v1, v22
-; CI-NEXT: v_mov_b32_e32 v2, v16
-; CI-NEXT: v_mov_b32_e32 v3, v17
-; CI-NEXT: v_mov_b32_e32 v4, v18
-; CI-NEXT: v_mov_b32_e32 v5, v19
-; CI-NEXT: v_mov_b32_e32 v6, v20
-; CI-NEXT: v_mov_b32_e32 v7, v21
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v8p3_to_v8p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v15, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v22
-; GFX9-NEXT: v_mov_b32_e32 v2, v16
-; GFX9-NEXT: v_mov_b32_e32 v3, v17
-; GFX9-NEXT: v_mov_b32_e32 v4, v18
-; GFX9-NEXT: v_mov_b32_e32 v5, v19
-; GFX9-NEXT: v_mov_b32_e32 v6, v20
-; GFX9-NEXT: v_mov_b32_e32 v7, v21
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr addrspace(3)> %ptr to <8 x ptr>
ret <8 x ptr> %cast
}
define <16 x ptr> @addrspacecast_v16p3_to_v16p0(<16 x ptr addrspace(3)> %ptr) {
-; CI-LABEL: addrspacecast_v16p3_to_v16p0:
-; CI: ; %bb.0:
-; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: s_load_dword s4, s[6:7], 0x10
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v31, s4
-; CI-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; CI-NEXT: v_cndmask_b32_e32 v34, 0, v1, vcc
-; CI-NEXT: v_cndmask_b32_e32 v39, 0, v31, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; CI-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
-; CI-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
-; CI-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
-; CI-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
-; CI-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; CI-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
-; CI-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
-; CI-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
-; CI-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
-; CI-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
-; CI-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
-; CI-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
-; CI-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
-; CI-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
-; CI-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[6:7]
-; CI-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[8:9]
-; CI-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[10:11]
-; CI-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[12:13]
-; CI-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[14:15]
-; CI-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[16:17]
-; CI-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[18:19]
-; CI-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[20:21]
-; CI-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[22:23]
-; CI-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[24:25]
-; CI-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[26:27]
-; CI-NEXT: v_mov_b32_e32 v1, v49
-; CI-NEXT: v_mov_b32_e32 v2, v34
-; CI-NEXT: v_mov_b32_e32 v3, v39
-; CI-NEXT: v_mov_b32_e32 v4, v35
-; CI-NEXT: v_mov_b32_e32 v5, v32
-; CI-NEXT: v_mov_b32_e32 v6, v36
-; CI-NEXT: v_mov_b32_e32 v8, v48
-; CI-NEXT: v_mov_b32_e32 v10, v37
-; CI-NEXT: v_mov_b32_e32 v12, v33
-; CI-NEXT: v_mov_b32_e32 v14, v38
-; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: addrspacecast_v16p3_to_v16p0:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
-; GFX9-NEXT: v_mov_b32_e32 v31, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v34, 0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v39, 0, v31, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
-; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
-; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
-; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
-; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
-; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
-; GFX9-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
-; GFX9-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[10:11]
-; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[14:15]
-; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[16:17]
-; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[18:19]
-; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[20:21]
-; GFX9-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[22:23]
-; GFX9-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[24:25]
-; GFX9-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[26:27]
-; GFX9-NEXT: v_mov_b32_e32 v1, v49
-; GFX9-NEXT: v_mov_b32_e32 v2, v34
-; GFX9-NEXT: v_mov_b32_e32 v3, v39
-; GFX9-NEXT: v_mov_b32_e32 v4, v35
-; GFX9-NEXT: v_mov_b32_e32 v5, v32
-; GFX9-NEXT: v_mov_b32_e32 v6, v36
-; GFX9-NEXT: v_mov_b32_e32 v8, v48
-; GFX9-NEXT: v_mov_b32_e32 v10, v37
-; GFX9-NEXT: v_mov_b32_e32 v12, v33
-; GFX9-NEXT: v_mov_b32_e32 v14, v38
-; GFX9-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr addrspace(3)> %ptr to <16 x ptr>
ret <16 x ptr> %cast
}
define <2 x ptr addrspace(1)> @addrspacecast_v2p0_to_v2p1(<2 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v2p0_to_v2p1:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(1)>
ret <2 x ptr addrspace(1)> %cast
}
define <3 x ptr addrspace(1)> @addrspacecast_v3p0_to_v3p1(<3 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v3p0_to_v3p1:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(1)>
ret <3 x ptr addrspace(1)> %cast
}
define <4 x ptr addrspace(1)> @addrspacecast_v4p0_to_v4p1(<4 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v4p0_to_v4p1:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(1)>
ret <4 x ptr addrspace(1)> %cast
}
define <8 x ptr addrspace(1)> @addrspacecast_v8p0_to_v8p1(<8 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v8p0_to_v8p1:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(1)>
ret <8 x ptr addrspace(1)> %cast
}
define <16 x ptr addrspace(1)> @addrspacecast_v16p0_to_v16p1(<16 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v16p0_to_v16p1:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; HSA-NEXT: s_waitcnt vmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(1)>
ret <16 x ptr addrspace(1)> %cast
}
define <2 x ptr> @addrspacecast_v2p1_to_v2p0(<2 x ptr addrspace(1)> %ptr) {
-; HSA-LABEL: addrspacecast_v2p1_to_v2p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr addrspace(1)> %ptr to <2 x ptr>
ret <2 x ptr> %cast
}
define <1 x ptr> @addrspacecast_v1p1_to_v1p0(<1 x ptr addrspace(1)> %ptr) {
-; HSA-LABEL: addrspacecast_v1p1_to_v1p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <1 x ptr addrspace(1)> %ptr to <1 x ptr>
ret <1 x ptr> %cast
}
define <4 x ptr> @addrspacecast_v4p1_to_v4p0(<4 x ptr addrspace(1)> %ptr) {
-; HSA-LABEL: addrspacecast_v4p1_to_v4p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr addrspace(1)> %ptr to <4 x ptr>
ret <4 x ptr> %cast
}
define <8 x ptr> @addrspacecast_v8p1_to_v8p0(<8 x ptr addrspace(1)> %ptr) {
-; HSA-LABEL: addrspacecast_v8p1_to_v8p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr addrspace(1)> %ptr to <8 x ptr>
ret <8 x ptr> %cast
}
define <16 x ptr> @addrspacecast_v16p1_to_v16p0(<16 x ptr addrspace(1)> %ptr) {
-; HSA-LABEL: addrspacecast_v16p1_to_v16p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; HSA-NEXT: s_waitcnt vmcnt(0)
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr addrspace(1)> %ptr to <16 x ptr>
ret <16 x ptr> %cast
}
define <2 x ptr addrspace(6)> @addrspacecast_v2p0_to_v2p6(<2 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v2p0_to_v2p6:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v1, v2
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(6)>
ret <2 x ptr addrspace(6)> %cast
}
define <3 x ptr addrspace(6)> @addrspacecast_v3p0_to_v3p6(<3 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v3p0_to_v3p6:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v1, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v4
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(6)>
ret <3 x ptr addrspace(6)> %cast
}
define <4 x ptr addrspace(6)> @addrspacecast_v4p0_to_v4p6(<4 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v4p0_to_v4p6:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v3, v6
-; HSA-NEXT: v_mov_b32_e32 v1, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v4
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(6)>
ret <4 x ptr addrspace(6)> %cast
}
define <8 x ptr addrspace(6)> @addrspacecast_v8p0_to_v8p6(<8 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v8p0_to_v8p6:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v7, v14
-; HSA-NEXT: v_mov_b32_e32 v5, v10
-; HSA-NEXT: v_mov_b32_e32 v3, v6
-; HSA-NEXT: v_mov_b32_e32 v1, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v4
-; HSA-NEXT: v_mov_b32_e32 v4, v8
-; HSA-NEXT: v_mov_b32_e32 v6, v12
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(6)>
ret <8 x ptr addrspace(6)> %cast
}
define <16 x ptr addrspace(6)> @addrspacecast_v16p0_to_v16p6(<16 x ptr> %ptr) {
-; HSA-LABEL: addrspacecast_v16p0_to_v16p6:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v15, v30
-; HSA-NEXT: v_mov_b32_e32 v13, v26
-; HSA-NEXT: v_mov_b32_e32 v11, v22
-; HSA-NEXT: v_mov_b32_e32 v9, v18
-; HSA-NEXT: v_mov_b32_e32 v7, v14
-; HSA-NEXT: v_mov_b32_e32 v5, v10
-; HSA-NEXT: v_mov_b32_e32 v3, v6
-; HSA-NEXT: v_mov_b32_e32 v1, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v4
-; HSA-NEXT: v_mov_b32_e32 v4, v8
-; HSA-NEXT: v_mov_b32_e32 v6, v12
-; HSA-NEXT: v_mov_b32_e32 v8, v16
-; HSA-NEXT: v_mov_b32_e32 v10, v20
-; HSA-NEXT: v_mov_b32_e32 v12, v24
-; HSA-NEXT: v_mov_b32_e32 v14, v28
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(6)>
ret <16 x ptr addrspace(6)> %cast
}
define <2 x ptr> @addrspacecast_v2p6_to_v2p0(<2 x ptr addrspace(6)> %ptr) {
-; HSA-LABEL: addrspacecast_v2p6_to_v2p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v2, v1
-; HSA-NEXT: v_mov_b32_e32 v1, 0
-; HSA-NEXT: v_mov_b32_e32 v3, 0
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <2 x ptr addrspace(6)> %ptr to <2 x ptr>
ret <2 x ptr> %cast
}
define <1 x ptr> @addrspacecast_v1p6_to_v1p0(<1 x ptr addrspace(6)> %ptr) {
-; HSA-LABEL: addrspacecast_v1p6_to_v1p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v1, 0
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <1 x ptr addrspace(6)> %ptr to <1 x ptr>
ret <1 x ptr> %cast
}
define <4 x ptr> @addrspacecast_v4p6_to_v4p0(<4 x ptr addrspace(6)> %ptr) {
-; HSA-LABEL: addrspacecast_v4p6_to_v4p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v6, v3
-; HSA-NEXT: v_mov_b32_e32 v4, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v1
-; HSA-NEXT: v_mov_b32_e32 v1, 0
-; HSA-NEXT: v_mov_b32_e32 v3, 0
-; HSA-NEXT: v_mov_b32_e32 v5, 0
-; HSA-NEXT: v_mov_b32_e32 v7, 0
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <4 x ptr addrspace(6)> %ptr to <4 x ptr>
ret <4 x ptr> %cast
}
define <8 x ptr> @addrspacecast_v8p6_to_v8p0(<8 x ptr addrspace(6)> %ptr) {
-; HSA-LABEL: addrspacecast_v8p6_to_v8p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v14, v7
-; HSA-NEXT: v_mov_b32_e32 v12, v6
-; HSA-NEXT: v_mov_b32_e32 v10, v5
-; HSA-NEXT: v_mov_b32_e32 v8, v4
-; HSA-NEXT: v_mov_b32_e32 v6, v3
-; HSA-NEXT: v_mov_b32_e32 v4, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v1
-; HSA-NEXT: v_mov_b32_e32 v1, 0
-; HSA-NEXT: v_mov_b32_e32 v3, 0
-; HSA-NEXT: v_mov_b32_e32 v5, 0
-; HSA-NEXT: v_mov_b32_e32 v7, 0
-; HSA-NEXT: v_mov_b32_e32 v9, 0
-; HSA-NEXT: v_mov_b32_e32 v11, 0
-; HSA-NEXT: v_mov_b32_e32 v13, 0
-; HSA-NEXT: v_mov_b32_e32 v15, 0
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <8 x ptr addrspace(6)> %ptr to <8 x ptr>
ret <8 x ptr> %cast
}
define <16 x ptr> @addrspacecast_v16p6_to_v16p0(<16 x ptr addrspace(6)> %ptr) {
-; HSA-LABEL: addrspacecast_v16p6_to_v16p0:
-; HSA: ; %bb.0:
-; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; HSA-NEXT: v_mov_b32_e32 v28, v14
-; HSA-NEXT: v_mov_b32_e32 v24, v12
-; HSA-NEXT: v_mov_b32_e32 v20, v10
-; HSA-NEXT: v_mov_b32_e32 v16, v8
-; HSA-NEXT: v_mov_b32_e32 v14, v7
-; HSA-NEXT: v_mov_b32_e32 v12, v6
-; HSA-NEXT: v_mov_b32_e32 v10, v5
-; HSA-NEXT: v_mov_b32_e32 v8, v4
-; HSA-NEXT: v_mov_b32_e32 v6, v3
-; HSA-NEXT: v_mov_b32_e32 v4, v2
-; HSA-NEXT: v_mov_b32_e32 v2, v1
-; HSA-NEXT: v_mov_b32_e32 v1, 0
-; HSA-NEXT: v_mov_b32_e32 v3, 0
-; HSA-NEXT: v_mov_b32_e32 v5, 0
-; HSA-NEXT: v_mov_b32_e32 v7, 0
-; HSA-NEXT: v_mov_b32_e32 v18, v9
-; HSA-NEXT: v_mov_b32_e32 v22, v11
-; HSA-NEXT: v_mov_b32_e32 v26, v13
-; HSA-NEXT: v_mov_b32_e32 v30, v15
-; HSA-NEXT: v_mov_b32_e32 v9, 0
-; HSA-NEXT: v_mov_b32_e32 v11, 0
-; HSA-NEXT: v_mov_b32_e32 v13, 0
-; HSA-NEXT: v_mov_b32_e32 v15, 0
-; HSA-NEXT: v_mov_b32_e32 v17, 0
-; HSA-NEXT: v_mov_b32_e32 v19, 0
-; HSA-NEXT: v_mov_b32_e32 v21, 0
-; HSA-NEXT: v_mov_b32_e32 v23, 0
-; HSA-NEXT: v_mov_b32_e32 v25, 0
-; HSA-NEXT: v_mov_b32_e32 v27, 0
-; HSA-NEXT: v_mov_b32_e32 v29, 0
-; HSA-NEXT: v_mov_b32_e32 v31, 0
-; HSA-NEXT: s_setpc_b64 s[30:31]
%cast = addrspacecast <16 x ptr addrspace(6)> %ptr to <16 x ptr>
ret <16 x ptr> %cast
}
@@ -1598,3 +626,7 @@ attributes #3 = { nounwind "amdgpu-32bit-address-high-bits"="0xffff8000" }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CI: {{.*}}
+; GFX9: {{.*}}
+; HSA: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 833be2066cd54..0efe09371bd6f 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -4453,6 +4453,7 @@ define float @v_fmul_0_fsub_0_safe_infloop_regression(float %arg) {
; SI-NSZ-NEXT: s_brev_b32 s4, 1
; SI-NSZ-NEXT: v_fma_f32 v0, v0, s4, 0
; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+;
; FIXME: utils/update_llc_test_checks.py will generate redundant VI
; labels, remove them, they will cause test failure.
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
index 631fdc7406918..fc4459925afbd 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
@@ -17,22 +17,12 @@ entry:
}
define i64 @test_s_bitreplicate_constant_zero() {
-; GFX11-LABEL: test_s_bitreplicate_constant_zero:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%br = call i64 @llvm.amdgcn.s.bitreplicate(i32 0)
ret i64 %br
}
define i64 @test_s_bitreplicate_constant_neg_one() {
-; GFX11-LABEL: test_s_bitreplicate_constant_neg_one:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, -1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%br = call i64 @llvm.amdgcn.s.bitreplicate(i32 -1)
ret i64 %br
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
index d9f2fc55709a6..f47aac14bff3a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
@@ -341,16 +341,27 @@ define { i32, <3 x i32> } @global_load_tr6_b96_vaddr_no_align2_requirement(ptr a
}
define { i32, <3 x i32> } @global_load_tr6_b96_saddr_no_align2_requirement(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
-; GFX1250-LABEL: global_load_tr6_b96_saddr_no_align2_requirement:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2
-; GFX1250-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-SDAG-LABEL: global_load_tr6_b96_saddr_no_align2_requirement:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-SDAG-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v3, v4
+; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: global_load_tr6_b96_saddr_no_align2_requirement:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-GISEL-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1) %gep)
%insert0 = insertvalue { i32, <3 x i32> } poison, i32 0, 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
index c9f4acaa20f76..3a4b2102e7946 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
@@ -96,21 +96,11 @@ define i64 @test_s_wqm_constant_i64() {
}
define i64 @test_s_wqm_constant_zero_i64() {
-; GFX11-LABEL: test_s_wqm_constant_zero_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 0)
ret i64 %br
}
define i64 @test_s_wqm_constant_neg_one_i64() {
-; GFX11-LABEL: test_s_wqm_constant_neg_one_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, -1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 -1)
ret i64 %br
}
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index 7cc623fb0a616..79da8726fdde7 100644
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -560,20 +560,20 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM6-LABEL: vec_4xi32_nonsplat_eq:
; ARM6: @ %bb.0:
-; ARM6-NEXT: ldr r12, [sp, #4]
+; ARM6-NEXT: push {r11, lr}
+; ARM6-NEXT: ldr r12, [sp, #12]
; ARM6-NEXT: mov r0, #1
+; ARM6-NEXT: mov lr, #65280
+; ARM6-NEXT: orr lr, lr, #16711680
; ARM6-NEXT: bic r1, r0, r1, lsl r12
-; ARM6-NEXT: ldr r12, [sp, #8]
-; ARM6-NEXT: mov r0, #65280
-; ARM6-NEXT: orr r0, r0, #16711680
-; ARM6-NEXT: and r0, r0, r2, lsl r12
-; ARM6-NEXT: clz r0, r0
-; ARM6-NEXT: lsr r2, r0, #5
-; ARM6-NEXT: ldr r0, [sp, #12]
-; ARM6-NEXT: mvn r0, r3, lsl r0
-; ARM6-NEXT: lsr r3, r0, #31
-; ARM6-NEXT: mov r0, #1
-; ARM6-NEXT: bx lr
+; ARM6-NEXT: ldr r12, [sp, #16]
+; ARM6-NEXT: and r2, lr, r2, lsl r12
+; ARM6-NEXT: ldr r12, [sp, #20]
+; ARM6-NEXT: clz r2, r2
+; ARM6-NEXT: mvn r3, r3, lsl r12
+; ARM6-NEXT: lsr r2, r2, #5
+; ARM6-NEXT: lsr r3, r3, #31
+; ARM6-NEXT: pop {r11, pc}
;
; ARM78-LABEL: vec_4xi32_nonsplat_eq:
; ARM78: @ %bb.0:
@@ -656,16 +656,14 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
; ARM6: @ %bb.0:
-; ARM6-NEXT: push {r11, lr}
-; ARM6-NEXT: ldr r2, [sp, #12]
-; ARM6-NEXT: mov lr, #1
-; ARM6-NEXT: ldr r12, [sp, #8]
-; ARM6-NEXT: bic r1, lr, r1, lsl r2
-; ARM6-NEXT: ldr r2, [sp, #20]
-; ARM6-NEXT: bic r0, lr, r0, lsl r12
-; ARM6-NEXT: bic r3, lr, r3, lsl r2
+; ARM6-NEXT: ldr r12, [sp]
; ARM6-NEXT: mov r2, #1
-; ARM6-NEXT: pop {r11, pc}
+; ARM6-NEXT: bic r0, r2, r0, lsl r12
+; ARM6-NEXT: ldr r12, [sp, #4]
+; ARM6-NEXT: bic r1, r2, r1, lsl r12
+; ARM6-NEXT: ldr r12, [sp, #12]
+; ARM6-NEXT: bic r3, r2, r3, lsl r12
+; ARM6-NEXT: bx lr
;
; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
; ARM78: @ %bb.0:
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index a8421ae9a6a89..335dc797e2a5e 100644
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -576,20 +576,20 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM6-LABEL: vec_4xi32_nonsplat_eq:
; ARM6: @ %bb.0:
-; ARM6-NEXT: ldr r12, [sp, #4]
+; ARM6-NEXT: push {r11, lr}
+; ARM6-NEXT: ldr r12, [sp, #12]
; ARM6-NEXT: mov r0, #1
+; ARM6-NEXT: mov lr, #65280
+; ARM6-NEXT: orr lr, lr, #16711680
; ARM6-NEXT: bic r1, r0, r1, lsr r12
-; ARM6-NEXT: ldr r12, [sp, #8]
-; ARM6-NEXT: mov r0, #65280
-; ARM6-NEXT: orr r0, r0, #16711680
-; ARM6-NEXT: and r0, r0, r2, lsr r12
-; ARM6-NEXT: clz r0, r0
-; ARM6-NEXT: lsr r2, r0, #5
-; ARM6-NEXT: ldr r0, [sp, #12]
-; ARM6-NEXT: mvn r0, r3, lsr r0
-; ARM6-NEXT: lsr r3, r0, #31
-; ARM6-NEXT: mov r0, #1
-; ARM6-NEXT: bx lr
+; ARM6-NEXT: ldr r12, [sp, #16]
+; ARM6-NEXT: and r2, lr, r2, lsr r12
+; ARM6-NEXT: ldr r12, [sp, #20]
+; ARM6-NEXT: clz r2, r2
+; ARM6-NEXT: mvn r3, r3, lsr r12
+; ARM6-NEXT: lsr r2, r2, #5
+; ARM6-NEXT: lsr r3, r3, #31
+; ARM6-NEXT: pop {r11, pc}
;
; ARM78-LABEL: vec_4xi32_nonsplat_eq:
; ARM78: @ %bb.0:
@@ -670,16 +670,14 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
; ARM6: @ %bb.0:
-; ARM6-NEXT: push {r11, lr}
-; ARM6-NEXT: ldr r2, [sp, #12]
-; ARM6-NEXT: mov lr, #1
-; ARM6-NEXT: ldr r12, [sp, #8]
-; ARM6-NEXT: bic r1, lr, r1, lsr r2
-; ARM6-NEXT: ldr r2, [sp, #20]
-; ARM6-NEXT: bic r0, lr, r0, lsr r12
-; ARM6-NEXT: bic r3, lr, r3, lsr r2
+; ARM6-NEXT: ldr r12, [sp]
; ARM6-NEXT: mov r2, #1
-; ARM6-NEXT: pop {r11, pc}
+; ARM6-NEXT: bic r0, r2, r0, lsr r12
+; ARM6-NEXT: ldr r12, [sp, #4]
+; ARM6-NEXT: bic r1, r2, r1, lsr r12
+; ARM6-NEXT: ldr r12, [sp, #12]
+; ARM6-NEXT: bic r3, r2, r3, lsr r12
+; ARM6-NEXT: bx lr
;
; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
; ARM78: @ %bb.0:
diff --git a/llvm/test/CodeGen/ARM/readcyclecounter.ll b/llvm/test/CodeGen/ARM/readcyclecounter.ll
index 7ed49ff95deca..9a49aa63a0700 100644
--- a/llvm/test/CodeGen/ARM/readcyclecounter.ll
+++ b/llvm/test/CodeGen/ARM/readcyclecounter.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s
; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
@@ -17,9 +18,8 @@ define i64 @get_count() {
; As usual, exact registers only sort of matter but the cycle-count had better
; end up in r0 in the end.
-; CHECK: mrc p15, #0, r0, c9, c13, #0
-; CHECK: {{movs?}} r1, #0
-; CHECK-NO-PERFMON: {{movs?}} r0, #0
-; CHECK-NO-PERFMON: {{movs?}} r1, #0
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
+; CHECK-NO-PERFMON: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/select_const.ll b/llvm/test/CodeGen/ARM/select_const.ll
index 180daa12e7c52..9419e212d52c1 100644
--- a/llvm/test/CodeGen/ARM/select_const.ll
+++ b/llvm/test/CodeGen/ARM/select_const.ll
@@ -766,7 +766,7 @@ define i64 @func(i64 %arg) {
; ARM-NEXT: adds r0, r0, #1
; ARM-NEXT: mov r2, #0
; ARM-NEXT: adcs r0, r1, #0
-; ARM-NEXT: mov r1, #0
+; ARM-NEXT: mov r1, r2
; ARM-NEXT: adcs r0, r2, #0
; ARM-NEXT: movne r0, #8
; ARM-NEXT: mov pc, lr
@@ -776,7 +776,7 @@ define i64 @func(i64 %arg) {
; THUMB2-NEXT: adds r0, #1
; THUMB2-NEXT: mov.w r2, #0
; THUMB2-NEXT: adcs r0, r1, #0
-; THUMB2-NEXT: mov.w r1, #0
+; THUMB2-NEXT: mov r1, r2
; THUMB2-NEXT: adcs r0, r2, #0
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #8
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
index 6f154a9afffae..0945ae0e4e918 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
@@ -1,14 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: ret_struct_i8_i16_i8
define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
+; CHECK-LABEL: ret_struct_i8_i16_i8:
+; CHECK: ; %bb.0: ; %start
+; CHECK-NEXT: ldi r22, 64
+; CHECK-NEXT: ldi r18, 0
+; CHECK-NEXT: ldi r19, 4
+; CHECK-NEXT: ldi r25, 11
+; CHECK-NEXT: mov r23, r18
+; CHECK-NEXT: mov r24, r19
+; CHECK-NEXT: ret
start:
; for some reason the i16 is loaded to r24:r25
; and then moved to r23:r24
- ; CHECK: ldi r22, 64
- ; CHECK-NEXT: r23,
- ; CHECK-NEXT: r24,
- ; CHECK-NEXT: r25, 11
%0 = insertvalue {i8, i16, i8} undef, i8 64, 0
%1 = insertvalue {i8, i16, i8} %0, i16 1024, 1
%2 = insertvalue {i8, i16, i8} %1, i8 11, 2
@@ -17,13 +23,16 @@ start:
; CHECK-LABEL: ret_struct_i32_i16
define { i32, i16 } @ret_struct_i32_i16() {
+; CHECK-LABEL: ret_struct_i32_i16:
+; CHECK: ; %bb.0: ; %start
+; CHECK-NEXT: ldi r18, 4
+; CHECK-NEXT: ldi r19, 3
+; CHECK-NEXT: ldi r20, 2
+; CHECK-NEXT: ldi r21, 1
+; CHECK-NEXT: ldi r22, 0
+; CHECK-NEXT: ldi r23, 8
+; CHECK-NEXT: ret
start:
- ; CHECK: ldi r18, 4
- ; CHECK-NEXT: ldi r19, 3
- ; CHECK-NEXT: ldi r20, 2
- ; CHECK-NEXT: ldi r21, 1
- ; CHECK-NEXT: ldi r22, 0
- ; CHECK-NEXT: ldi r23, 8
%0 = insertvalue { i32, i16 } undef, i32 16909060, 0
%1 = insertvalue { i32, i16 } %0, i16 2048, 1
ret { i32, i16} %1
diff --git a/llvm/test/CodeGen/BPF/BTF/filename.ll b/llvm/test/CodeGen/BPF/BTF/filename.ll
index ae08aea71b2cb..022a6fb9ac974 100644
--- a/llvm/test/CodeGen/BPF/BTF/filename.ll
+++ b/llvm/test/CodeGen/BPF/BTF/filename.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
; RUN: llc -mtriple=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
@@ -8,6 +9,22 @@
; Function Attrs: norecurse nounwind readnone uwtable
define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 {
+; CHECK-LABEL: test:
+; CHECK: .Ltest$local:
+; CHECK-NEXT: .type .Ltest$local, at function
+; CHECK-NEXT: .Lfunc_begin0:
+; CHECK-NEXT: .file 1 "/home/yhs/ttmp" "/home/yhs/ttmp/t.c"
+; CHECK-NEXT: .loc 1 1 0 # /home/yhs/ttmp/t.c:1:0
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: w0 = 0
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .loc 1 1 14 prologue_end # /home/yhs/ttmp/t.c:1:14
+; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: exit
+; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Ltmp4:
ret i32 0, !dbg !11
}
diff --git a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
index f9439e606ae87..728e0354d33c8 100644
--- a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
+++ b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
; RUN: llc -mtriple=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
@@ -8,6 +9,24 @@
; Function Attrs: nounwind readnone
define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 {
+; CHECK-LABEL: f1:
+; CHECK: .Lf1$local:
+; CHECK-NEXT: .type .Lf1$local, at function
+; CHECK-NEXT: .Lfunc_begin0:
+; CHECK-NEXT: .file 1 "/DNE" "t.c"
+; CHECK-NEXT: .loc 1 1 0 # t.c:1:0
+; CHECK-NEXT: .cfi_sections .debug_frame
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: #DEBUG_VALUE: f1:a1 <- $w1
+; CHECK-NEXT: w0 = 0
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .loc 1 1 18 prologue_end # t.c:1:18
+; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: exit
+; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Ltmp4:
call void @llvm.dbg.value(metadata i32 %0, metadata !12, metadata !DIExpression()), !dbg !13
ret i32 0, !dbg !14
}
diff --git a/llvm/test/CodeGen/BPF/fi_ri.ll b/llvm/test/CodeGen/BPF/fi_ri.ll
index 8d60d29b52726..cc9943c4812bc 100644
--- a/llvm/test/CodeGen/BPF/fi_ri.ll
+++ b/llvm/test/CodeGen/BPF/fi_ri.ll
@@ -1,19 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpf -mcpu=v1 | FileCheck %s
%struct.key_t = type { i32, [16 x i8] }
; Function Attrs: nounwind uwtable
define i32 @test() #0 {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: r6 = 0
+; CHECK-NEXT: *(u32 *)(r10 - 8) = r6
+; CHECK-NEXT: *(u64 *)(r10 - 16) = r6
+; CHECK-NEXT: *(u64 *)(r10 - 24) = r6
+; CHECK-NEXT: r1 = r10
+; CHECK-NEXT: r1 += -20
+; CHECK-NEXT: call test1
+; CHECK-NEXT: r0 = r6
+; CHECK-NEXT: exit
%key = alloca %struct.key_t, align 4
-; CHECK: r1 = 0
-; CHECK: *(u32 *)(r10 - 8) = r1
-; CHECK: *(u64 *)(r10 - 16) = r1
-; CHECK: *(u64 *)(r10 - 24) = r1
call void @llvm.memset.p0.i64(ptr align 4 %key, i8 0, i64 20, i1 false)
-; CHECK: r1 = r10
-; CHECK: r1 += -20
%1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
-; CHECK: call test1
call void @test1(ptr %1) #3
ret i32 0
}
diff --git a/llvm/test/CodeGen/BPF/inlineasm-wreg.ll b/llvm/test/CodeGen/BPF/inlineasm-wreg.ll
index 496a2d909cb7c..96008335afd6f 100644
--- a/llvm/test/CodeGen/BPF/inlineasm-wreg.ll
+++ b/llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -1,18 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
; Test that %w works as input constraint
; CHECK-LABEL: test_inlineasm_w_input_constraint
define dso_local i32 @test_inlineasm_w_input_constraint() {
+; CHECK-LABEL: test_inlineasm_w_input_constraint:
+; CHECK: .Ltest_inlineasm_w_input_constraint$local:
+; CHECK-NEXT: .type .Ltest_inlineasm_w_input_constraint$local, at function
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: w0 = 42
+; CHECK-NEXT: #APP
+; CHECK-NEXT: w0 = w0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: exit
tail call void asm sideeffect "w0 = $0", "w"(i32 42)
-; CHECK: w0 = w1
ret i32 42
}
; Test that %w works as output constraint
; CHECK-LABEL: test_inlineasm_w_output_constraint
define dso_local i32 @test_inlineasm_w_output_constraint() {
+; CHECK-LABEL: test_inlineasm_w_output_constraint:
+; CHECK: .Ltest_inlineasm_w_output_constraint$local:
+; CHECK-NEXT: .type .Ltest_inlineasm_w_output_constraint$local, at function
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: w0 = 42
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: exit
%1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
-; CHECK: w0 = 42
ret i32 %1
}
diff --git a/llvm/test/CodeGen/BPF/rodata_1.ll b/llvm/test/CodeGen/BPF/rodata_1.ll
index 26dd85caa1d21..a6db9deeface6 100644
--- a/llvm/test/CodeGen/BPF/rodata_1.ll
+++ b/llvm/test/CodeGen/BPF/rodata_1.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpfel -mcpu=v1 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -verify-machineinstrs | FileCheck %s
@@ -31,17 +32,24 @@
; Function Attrs: nounwind
define i32 @test() local_unnamed_addr #0 {
; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: r1 = g1 ll
+; CHECK-NEXT: r0 = 0
+; CHECK-NEXT: *(u8 *)(r1 + 1) = r0
+; CHECK-NEXT: *(u8 *)(r1 + 0) = r0
+; CHECK-NEXT: r2 = 1
+; CHECK-NEXT: *(u8 *)(r1 + 2) = r2
+; CHECK-NEXT: r1 = g2 ll
+; CHECK-NEXT: *(u32 *)(r1 + 8) = r2
+; CHECK-NEXT: *(u32 *)(r1 + 4) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 0) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 12) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 16) = r0
+; CHECK-NEXT: exit
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr @g1, ptr @test.t1, i64 3, i1 false)
tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g2, ptr align 4 @test.t2, i64 20, i1 false)
-; CHECK: r1 = g1
-; CHECK: r2 = 0
-; CHECK: *(u8 *)(r1 + 1) = r2
-; CHECK: r3 = 1
-; CHECK: *(u8 *)(r1 + 2) = r3
-; CHECK: r1 = g2
-; CHECK: *(u32 *)(r1 + 8) = r3
ret i32 0
}
; CHECK: .section .rodata,"a", at progbits
diff --git a/llvm/test/CodeGen/BPF/rodata_2.ll b/llvm/test/CodeGen/BPF/rodata_2.ll
index bb7bf4ba8ace7..c8fb758c0c698 100644
--- a/llvm/test/CodeGen/BPF/rodata_2.ll
+++ b/llvm/test/CodeGen/BPF/rodata_2.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpfel -mcpu=v1 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -verify-machineinstrs | FileCheck %s
@@ -29,21 +30,24 @@
; Function Attrs: nounwind
define i32 @test() local_unnamed_addr #0 {
; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: r1 = g ll
+; CHECK-NEXT: r2 = 3
+; CHECK-NEXT: *(u32 *)(r1 + 24) = r2
+; CHECK-NEXT: r2 = 2
+; CHECK-NEXT: *(u32 *)(r1 + 20) = r2
+; CHECK-NEXT: r2 = 1
+; CHECK-NEXT: *(u32 *)(r1 + 16) = r2
+; CHECK-NEXT: r0 = 0
+; CHECK-NEXT: *(u32 *)(r1 + 28) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 12) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 8) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 4) = r0
+; CHECK-NEXT: *(u32 *)(r1 + 0) = r0
+; CHECK-NEXT: exit
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g, ptr align 4 @test.t2, i64 32, i1 false)
-; CHECK: r1 = g ll
-; CHECK: r2 = 3
-; CHECK: *(u32 *)(r1 + 24) = r2
-; CHECK: r2 = 2
-; CHECK: *(u32 *)(r1 + 20) = r2
-; CHECK: r2 = 1
-; CHECK: *(u32 *)(r1 + 16) = r2
-; CHECK: r2 = 0
-; CHECK: *(u32 *)(r1 + 28) = r2
-; CHECK: *(u32 *)(r1 + 8) = r2
-; CHECK: *(u32 *)(r1 + 4) = r2
-; CHECK: *(u32 *)(r1 + 0) = r2
ret i32 0
}
; CHECK: .section .rodata.cst32,"aM", at progbits,32
diff --git a/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll b/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
index 733c53697b987..97fe01e40e5b2 100644
--- a/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
+++ b/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
@@ -92,6 +92,7 @@ define double @callee_double_ret() nounwind {
; CHECK-LABEL: callee_double_ret:
; CHECK: # %bb.0:
; CHECK-NEXT: vldi $vr0, -912
+; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
; CHECK-NEXT: ret
ret double 1.0
}
diff --git a/llvm/test/CodeGen/LoongArch/double-imm.ll b/llvm/test/CodeGen/LoongArch/double-imm.ll
index 0b715cb18f8ad..ab575a653487e 100644
--- a/llvm/test/CodeGen/LoongArch/double-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/double-imm.ll
@@ -377,6 +377,7 @@ define double @f64_positive_fimm1() nounwind {
; LA64-LABEL: f64_positive_fimm1:
; LA64: # %bb.0:
; LA64-NEXT: vldi $vr0, -912
+; LA64-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
; LA64-NEXT: ret
ret double 1.0
}
diff --git a/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll b/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll
index 551ab6ea44c66..93d27243e66bf 100644
--- a/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll
+++ b/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll
@@ -7,6 +7,8 @@ define dso_local { float, double } @test1() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1280
; CHECK-NEXT: vldi $vr1, -1024
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.0000000000, double 2.0000000000 }
@@ -17,6 +19,8 @@ define dso_local { float, double } @test2() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1279
; CHECK-NEXT: vldi $vr1, -1023
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.1250000000, double 2.1250000000 }
@@ -27,6 +31,8 @@ define dso_local { float, double } @test3() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1278
; CHECK-NEXT: vldi $vr1, -1022
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.2500000000, double 2.2500000000 }
@@ -37,6 +43,8 @@ define dso_local { float, double } @test4() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1277
; CHECK-NEXT: vldi $vr1, -1021
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.3750000000, double 2.3750000000 }
@@ -47,6 +55,8 @@ define dso_local { float, double } @test5() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1276
; CHECK-NEXT: vldi $vr1, -1020
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.5000000000, double 2.5000000000 }
@@ -57,6 +67,8 @@ define dso_local { float, double } @test6() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1275
; CHECK-NEXT: vldi $vr1, -1019
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.6250000000, double 2.6250000000 }
@@ -67,6 +79,8 @@ define dso_local { float, double } @test7() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1274
; CHECK-NEXT: vldi $vr1, -1018
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.7500000000, double 2.7500000000 }
@@ -77,6 +91,8 @@ define dso_local { float, double } @test8() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1273
; CHECK-NEXT: vldi $vr1, -1017
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 2.8750000000, double 2.8750000000 }
@@ -87,6 +103,8 @@ define dso_local { float, double } @test9() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1272
; CHECK-NEXT: vldi $vr1, -1016
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.0000000000, double 3.0000000000 }
@@ -97,6 +115,8 @@ define dso_local { float, double } @test10() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1271
; CHECK-NEXT: vldi $vr1, -1015
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.1250000000, double 3.1250000000 }
@@ -107,6 +127,8 @@ define dso_local { float, double } @test11() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1270
; CHECK-NEXT: vldi $vr1, -1014
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.2500000000, double 3.2500000000 }
@@ -117,6 +139,8 @@ define dso_local { float, double } @test12() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1269
; CHECK-NEXT: vldi $vr1, -1013
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.3750000000, double 3.3750000000 }
@@ -127,6 +151,8 @@ define dso_local { float, double } @test13() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1268
; CHECK-NEXT: vldi $vr1, -1012
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.5000000000, double 3.5000000000 }
@@ -137,6 +163,8 @@ define dso_local { float, double } @test14() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1267
; CHECK-NEXT: vldi $vr1, -1011
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.6250000000, double 3.6250000000 }
@@ -147,6 +175,8 @@ define dso_local { float, double } @test15() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1266
; CHECK-NEXT: vldi $vr1, -1010
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.7500000000, double 3.7500000000 }
@@ -157,6 +187,8 @@ define dso_local { float, double } @test16() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1265
; CHECK-NEXT: vldi $vr1, -1009
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 3.8750000000, double 3.8750000000 }
@@ -167,6 +199,8 @@ define dso_local { float, double } @test17() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1264
; CHECK-NEXT: vldi $vr1, -1008
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 4.0000000000, double 4.0000000000 }
@@ -177,6 +211,8 @@ define dso_local { float, double } @test18() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1263
; CHECK-NEXT: vldi $vr1, -1007
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 4.2500000000, double 4.2500000000 }
@@ -187,6 +223,8 @@ define dso_local { float, double } @test19() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1262
; CHECK-NEXT: vldi $vr1, -1006
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 4.5000000000, double 4.5000000000 }
@@ -197,6 +235,8 @@ define dso_local { float, double } @test20() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1261
; CHECK-NEXT: vldi $vr1, -1005
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 4.7500000000, double 4.7500000000 }
@@ -207,6 +247,8 @@ define dso_local { float, double } @test21() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1260
; CHECK-NEXT: vldi $vr1, -1004
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 5.0000000000, double 5.0000000000 }
@@ -217,6 +259,8 @@ define dso_local { float, double } @test22() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1259
; CHECK-NEXT: vldi $vr1, -1003
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 5.2500000000, double 5.2500000000 }
@@ -227,6 +271,8 @@ define dso_local { float, double } @test23() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1258
; CHECK-NEXT: vldi $vr1, -1002
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 5.5000000000, double 5.5000000000 }
@@ -237,6 +283,8 @@ define dso_local { float, double } @test24() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1257
; CHECK-NEXT: vldi $vr1, -1001
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 5.7500000000, double 5.7500000000 }
@@ -247,6 +295,8 @@ define dso_local { float, double } @test25() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1256
; CHECK-NEXT: vldi $vr1, -1000
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 6.0000000000, double 6.0000000000 }
@@ -257,6 +307,8 @@ define dso_local { float, double } @test26() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1255
; CHECK-NEXT: vldi $vr1, -999
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 6.2500000000, double 6.2500000000 }
@@ -267,6 +319,8 @@ define dso_local { float, double } @test27() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1254
; CHECK-NEXT: vldi $vr1, -998
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 6.5000000000, double 6.5000000000 }
@@ -277,6 +331,8 @@ define dso_local { float, double } @test28() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1253
; CHECK-NEXT: vldi $vr1, -997
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 6.7500000000, double 6.7500000000 }
@@ -287,6 +343,8 @@ define dso_local { float, double } @test29() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1252
; CHECK-NEXT: vldi $vr1, -996
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 7.0000000000, double 7.0000000000 }
@@ -297,6 +355,8 @@ define dso_local { float, double } @test30() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1251
; CHECK-NEXT: vldi $vr1, -995
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 7.2500000000, double 7.2500000000 }
@@ -307,6 +367,8 @@ define dso_local { float, double } @test31() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1250
; CHECK-NEXT: vldi $vr1, -994
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 7.5000000000, double 7.5000000000 }
@@ -317,6 +379,8 @@ define dso_local { float, double } @test32() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1249
; CHECK-NEXT: vldi $vr1, -993
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 7.7500000000, double 7.7500000000 }
@@ -327,6 +391,8 @@ define dso_local { float, double } @test33() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1248
; CHECK-NEXT: vldi $vr1, -992
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 8.0000000000, double 8.0000000000 }
@@ -337,6 +403,8 @@ define dso_local { float, double } @test34() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1247
; CHECK-NEXT: vldi $vr1, -991
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 8.5000000000, double 8.5000000000 }
@@ -347,6 +415,8 @@ define dso_local { float, double } @test35() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1246
; CHECK-NEXT: vldi $vr1, -990
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 9.0000000000, double 9.0000000000 }
@@ -357,6 +427,8 @@ define dso_local { float, double } @test36() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1245
; CHECK-NEXT: vldi $vr1, -989
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 9.5000000000, double 9.5000000000 }
@@ -367,6 +439,8 @@ define dso_local { float, double } @test37() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1244
; CHECK-NEXT: vldi $vr1, -988
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 10.0000000000, double 10.0000000000 }
@@ -377,6 +451,8 @@ define dso_local { float, double } @test38() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1243
; CHECK-NEXT: vldi $vr1, -987
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 10.5000000000, double 10.5000000000 }
@@ -387,6 +463,8 @@ define dso_local { float, double } @test39() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1242
; CHECK-NEXT: vldi $vr1, -986
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 11.0000000000, double 11.0000000000 }
@@ -397,6 +475,8 @@ define dso_local { float, double } @test40() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1241
; CHECK-NEXT: vldi $vr1, -985
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 11.5000000000, double 11.5000000000 }
@@ -407,6 +487,8 @@ define dso_local { float, double } @test41() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1240
; CHECK-NEXT: vldi $vr1, -984
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 12.0000000000, double 12.0000000000 }
@@ -417,6 +499,8 @@ define dso_local { float, double } @test42() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1239
; CHECK-NEXT: vldi $vr1, -983
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 12.5000000000, double 12.5000000000 }
@@ -427,6 +511,8 @@ define dso_local { float, double } @test43() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1238
; CHECK-NEXT: vldi $vr1, -982
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 13.0000000000, double 13.0000000000 }
@@ -437,6 +523,8 @@ define dso_local { float, double } @test44() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1237
; CHECK-NEXT: vldi $vr1, -981
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 13.5000000000, double 13.5000000000 }
@@ -447,6 +535,8 @@ define dso_local { float, double } @test45() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1236
; CHECK-NEXT: vldi $vr1, -980
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 14.0000000000, double 14.0000000000 }
@@ -457,6 +547,8 @@ define dso_local { float, double } @test46() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1235
; CHECK-NEXT: vldi $vr1, -979
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 14.5000000000, double 14.5000000000 }
@@ -467,6 +559,8 @@ define dso_local { float, double } @test47() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1234
; CHECK-NEXT: vldi $vr1, -978
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 15.0000000000, double 15.0000000000 }
@@ -477,6 +571,8 @@ define dso_local { float, double } @test48() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1233
; CHECK-NEXT: vldi $vr1, -977
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 15.5000000000, double 15.5000000000 }
@@ -487,6 +583,8 @@ define dso_local { float, double } @test49() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1232
; CHECK-NEXT: vldi $vr1, -976
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 16.0000000000, double 16.0000000000 }
@@ -497,6 +595,8 @@ define dso_local { float, double } @test50() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1231
; CHECK-NEXT: vldi $vr1, -975
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 17.0000000000, double 17.0000000000 }
@@ -507,6 +607,8 @@ define dso_local { float, double } @test51() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1230
; CHECK-NEXT: vldi $vr1, -974
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 18.0000000000, double 18.0000000000 }
@@ -517,6 +619,8 @@ define dso_local { float, double } @test52() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1229
; CHECK-NEXT: vldi $vr1, -973
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 19.0000000000, double 19.0000000000 }
@@ -527,6 +631,8 @@ define dso_local { float, double } @test53() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1228
; CHECK-NEXT: vldi $vr1, -972
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 20.0000000000, double 20.0000000000 }
@@ -537,6 +643,8 @@ define dso_local { float, double } @test54() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1227
; CHECK-NEXT: vldi $vr1, -971
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 21.0000000000, double 21.0000000000 }
@@ -547,6 +655,8 @@ define dso_local { float, double } @test55() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1226
; CHECK-NEXT: vldi $vr1, -970
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 22.0000000000, double 22.0000000000 }
@@ -557,6 +667,8 @@ define dso_local { float, double } @test56() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1225
; CHECK-NEXT: vldi $vr1, -969
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 23.0000000000, double 23.0000000000 }
@@ -567,6 +679,8 @@ define dso_local { float, double } @test57() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1224
; CHECK-NEXT: vldi $vr1, -968
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 24.0000000000, double 24.0000000000 }
@@ -577,6 +691,8 @@ define dso_local { float, double } @test58() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1223
; CHECK-NEXT: vldi $vr1, -967
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 25.0000000000, double 25.0000000000 }
@@ -587,6 +703,8 @@ define dso_local { float, double } @test59() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1222
; CHECK-NEXT: vldi $vr1, -966
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 26.0000000000, double 26.0000000000 }
@@ -597,6 +715,8 @@ define dso_local { float, double } @test60() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1221
; CHECK-NEXT: vldi $vr1, -965
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 27.0000000000, double 27.0000000000 }
@@ -607,6 +727,8 @@ define dso_local { float, double } @test61() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1220
; CHECK-NEXT: vldi $vr1, -964
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 28.0000000000, double 28.0000000000 }
@@ -617,6 +739,8 @@ define dso_local { float, double } @test62() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1219
; CHECK-NEXT: vldi $vr1, -963
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 29.0000000000, double 29.0000000000 }
@@ -627,6 +751,8 @@ define dso_local { float, double } @test63() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1218
; CHECK-NEXT: vldi $vr1, -962
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 30.0000000000, double 30.0000000000 }
@@ -637,6 +763,8 @@ define dso_local { float, double } @test64() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1217
; CHECK-NEXT: vldi $vr1, -961
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 31.0000000000, double 31.0000000000 }
@@ -647,6 +775,8 @@ define dso_local { float, double } @test65() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1216
; CHECK-NEXT: vldi $vr1, -960
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1250000000, double 0.1250000000 }
@@ -657,6 +787,8 @@ define dso_local { float, double } @test66() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1215
; CHECK-NEXT: vldi $vr1, -959
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1328125000, double 0.1328125000 }
@@ -667,6 +799,8 @@ define dso_local { float, double } @test67() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1214
; CHECK-NEXT: vldi $vr1, -958
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1406250000, double 0.1406250000 }
@@ -677,6 +811,8 @@ define dso_local { float, double } @test68() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1213
; CHECK-NEXT: vldi $vr1, -957
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1484375000, double 0.1484375000 }
@@ -687,6 +823,8 @@ define dso_local { float, double } @test69() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1212
; CHECK-NEXT: vldi $vr1, -956
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1562500000, double 0.1562500000 }
@@ -697,6 +835,8 @@ define dso_local { float, double } @test70() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1211
; CHECK-NEXT: vldi $vr1, -955
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1640625000, double 0.1640625000 }
@@ -707,6 +847,8 @@ define dso_local { float, double } @test71() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1210
; CHECK-NEXT: vldi $vr1, -954
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1718750000, double 0.1718750000 }
@@ -717,6 +859,8 @@ define dso_local { float, double } @test72() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1209
; CHECK-NEXT: vldi $vr1, -953
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1796875000, double 0.1796875000 }
@@ -727,6 +871,8 @@ define dso_local { float, double } @test73() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1208
; CHECK-NEXT: vldi $vr1, -952
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1875000000, double 0.1875000000 }
@@ -737,6 +883,8 @@ define dso_local { float, double } @test74() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1207
; CHECK-NEXT: vldi $vr1, -951
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.1953125000, double 0.1953125000 }
@@ -747,6 +895,8 @@ define dso_local { float, double } @test75() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1206
; CHECK-NEXT: vldi $vr1, -950
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2031250000, double 0.2031250000 }
@@ -757,6 +907,8 @@ define dso_local { float, double } @test76() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1205
; CHECK-NEXT: vldi $vr1, -949
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2109375000, double 0.2109375000 }
@@ -767,6 +919,8 @@ define dso_local { float, double } @test77() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1204
; CHECK-NEXT: vldi $vr1, -948
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2187500000, double 0.2187500000 }
@@ -777,6 +931,8 @@ define dso_local { float, double } @test78() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1203
; CHECK-NEXT: vldi $vr1, -947
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2265625000, double 0.2265625000 }
@@ -787,6 +943,8 @@ define dso_local { float, double } @test79() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1202
; CHECK-NEXT: vldi $vr1, -946
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2343750000, double 0.2343750000 }
@@ -797,6 +955,8 @@ define dso_local { float, double } @test80() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1201
; CHECK-NEXT: vldi $vr1, -945
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2421875000, double 0.2421875000 }
@@ -807,6 +967,8 @@ define dso_local { float, double } @test81() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1200
; CHECK-NEXT: vldi $vr1, -944
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2500000000, double 0.2500000000 }
@@ -817,6 +979,8 @@ define dso_local { float, double } @test82() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1199
; CHECK-NEXT: vldi $vr1, -943
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2656250000, double 0.2656250000 }
@@ -827,6 +991,8 @@ define dso_local { float, double } @test83() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1198
; CHECK-NEXT: vldi $vr1, -942
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2812500000, double 0.2812500000 }
@@ -837,6 +1003,8 @@ define dso_local { float, double } @test84() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1197
; CHECK-NEXT: vldi $vr1, -941
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.2968750000, double 0.2968750000 }
@@ -847,6 +1015,8 @@ define dso_local { float, double } @test85() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1196
; CHECK-NEXT: vldi $vr1, -940
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.3125000000, double 0.3125000000 }
@@ -857,6 +1027,8 @@ define dso_local { float, double } @test86() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1195
; CHECK-NEXT: vldi $vr1, -939
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.3281250000, double 0.3281250000 }
@@ -867,6 +1039,8 @@ define dso_local { float, double } @test87() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1194
; CHECK-NEXT: vldi $vr1, -938
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.3437500000, double 0.3437500000 }
@@ -877,6 +1051,8 @@ define dso_local { float, double } @test88() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1193
; CHECK-NEXT: vldi $vr1, -937
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.3593750000, double 0.3593750000 }
@@ -887,6 +1063,8 @@ define dso_local { float, double } @test89() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1192
; CHECK-NEXT: vldi $vr1, -936
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.3750000000, double 0.3750000000 }
@@ -897,6 +1075,8 @@ define dso_local { float, double } @test90() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1191
; CHECK-NEXT: vldi $vr1, -935
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.3906250000, double 0.3906250000 }
@@ -907,6 +1087,8 @@ define dso_local { float, double } @test91() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1190
; CHECK-NEXT: vldi $vr1, -934
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.4062500000, double 0.4062500000 }
@@ -917,6 +1099,8 @@ define dso_local { float, double } @test92() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1189
; CHECK-NEXT: vldi $vr1, -933
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.4218750000, double 0.4218750000 }
@@ -927,6 +1111,8 @@ define dso_local { float, double } @test93() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1188
; CHECK-NEXT: vldi $vr1, -932
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.4375000000, double 0.4375000000 }
@@ -937,6 +1123,8 @@ define dso_local { float, double } @test94() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1187
; CHECK-NEXT: vldi $vr1, -931
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.4531250000, double 0.4531250000 }
@@ -947,6 +1135,8 @@ define dso_local { float, double } @test95() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1186
; CHECK-NEXT: vldi $vr1, -930
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.4687500000, double 0.4687500000 }
@@ -957,6 +1147,8 @@ define dso_local { float, double } @test96() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1185
; CHECK-NEXT: vldi $vr1, -929
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.4843750000, double 0.4843750000 }
@@ -967,6 +1159,8 @@ define dso_local { float, double } @test97() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1184
; CHECK-NEXT: vldi $vr1, -928
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.5000000000, double 0.5000000000 }
@@ -977,6 +1171,8 @@ define dso_local { float, double } @test98() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1183
; CHECK-NEXT: vldi $vr1, -927
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.5312500000, double 0.5312500000 }
@@ -987,6 +1183,8 @@ define dso_local { float, double } @test99() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1182
; CHECK-NEXT: vldi $vr1, -926
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.5625000000, double 0.5625000000 }
@@ -997,6 +1195,8 @@ define dso_local { float, double } @test100() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1181
; CHECK-NEXT: vldi $vr1, -925
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.5937500000, double 0.5937500000 }
@@ -1007,6 +1207,8 @@ define dso_local { float, double } @test101() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1180
; CHECK-NEXT: vldi $vr1, -924
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.6250000000, double 0.6250000000 }
@@ -1017,6 +1219,8 @@ define dso_local { float, double } @test102() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1179
; CHECK-NEXT: vldi $vr1, -923
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.6562500000, double 0.6562500000 }
@@ -1027,6 +1231,8 @@ define dso_local { float, double } @test103() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1178
; CHECK-NEXT: vldi $vr1, -922
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.6875000000, double 0.6875000000 }
@@ -1037,6 +1243,8 @@ define dso_local { float, double } @test104() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1177
; CHECK-NEXT: vldi $vr1, -921
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.7187500000, double 0.7187500000 }
@@ -1047,6 +1255,8 @@ define dso_local { float, double } @test105() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1176
; CHECK-NEXT: vldi $vr1, -920
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.7500000000, double 0.7500000000 }
@@ -1057,6 +1267,8 @@ define dso_local { float, double } @test106() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1175
; CHECK-NEXT: vldi $vr1, -919
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.7812500000, double 0.7812500000 }
@@ -1067,6 +1279,8 @@ define dso_local { float, double } @test107() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1174
; CHECK-NEXT: vldi $vr1, -918
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.8125000000, double 0.8125000000 }
@@ -1077,6 +1291,8 @@ define dso_local { float, double } @test108() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1173
; CHECK-NEXT: vldi $vr1, -917
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.8437500000, double 0.8437500000 }
@@ -1087,6 +1303,8 @@ define dso_local { float, double } @test109() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1172
; CHECK-NEXT: vldi $vr1, -916
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.8750000000, double 0.8750000000 }
@@ -1097,6 +1315,8 @@ define dso_local { float, double } @test110() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1171
; CHECK-NEXT: vldi $vr1, -915
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.9062500000, double 0.9062500000 }
@@ -1107,6 +1327,8 @@ define dso_local { float, double } @test111() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1170
; CHECK-NEXT: vldi $vr1, -914
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.9375000000, double 0.9375000000 }
@@ -1117,6 +1339,8 @@ define dso_local { float, double } @test112() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1169
; CHECK-NEXT: vldi $vr1, -913
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 0.9687500000, double 0.9687500000 }
@@ -1127,6 +1351,8 @@ define dso_local { float, double } @test113() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1168
; CHECK-NEXT: vldi $vr1, -912
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.0000000000, double 1.0000000000 }
@@ -1137,6 +1363,8 @@ define dso_local { float, double } @test114() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1167
; CHECK-NEXT: vldi $vr1, -911
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.0625000000, double 1.0625000000 }
@@ -1147,6 +1375,8 @@ define dso_local { float, double } @test115() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1166
; CHECK-NEXT: vldi $vr1, -910
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.1250000000, double 1.1250000000 }
@@ -1157,6 +1387,8 @@ define dso_local { float, double } @test116() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1165
; CHECK-NEXT: vldi $vr1, -909
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.1875000000, double 1.1875000000 }
@@ -1167,6 +1399,8 @@ define dso_local { float, double } @test117() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1164
; CHECK-NEXT: vldi $vr1, -908
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.2500000000, double 1.2500000000 }
@@ -1177,6 +1411,8 @@ define dso_local { float, double } @test118() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1163
; CHECK-NEXT: vldi $vr1, -907
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.3125000000, double 1.3125000000 }
@@ -1187,6 +1423,8 @@ define dso_local { float, double } @test119() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1162
; CHECK-NEXT: vldi $vr1, -906
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.3750000000, double 1.3750000000 }
@@ -1197,6 +1435,8 @@ define dso_local { float, double } @test120() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1161
; CHECK-NEXT: vldi $vr1, -905
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.4375000000, double 1.4375000000 }
@@ -1207,6 +1447,8 @@ define dso_local { float, double } @test121() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1160
; CHECK-NEXT: vldi $vr1, -904
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.5000000000, double 1.5000000000 }
@@ -1217,6 +1459,8 @@ define dso_local { float, double } @test122() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1159
; CHECK-NEXT: vldi $vr1, -903
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.5625000000, double 1.5625000000 }
@@ -1227,6 +1471,8 @@ define dso_local { float, double } @test123() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1158
; CHECK-NEXT: vldi $vr1, -902
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.6250000000, double 1.6250000000 }
@@ -1237,6 +1483,8 @@ define dso_local { float, double } @test124() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1157
; CHECK-NEXT: vldi $vr1, -901
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.6875000000, double 1.6875000000 }
@@ -1247,6 +1495,8 @@ define dso_local { float, double } @test125() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1156
; CHECK-NEXT: vldi $vr1, -900
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.7500000000, double 1.7500000000 }
@@ -1257,6 +1507,8 @@ define dso_local { float, double } @test126() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1155
; CHECK-NEXT: vldi $vr1, -899
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.8125000000, double 1.8125000000 }
@@ -1267,6 +1519,8 @@ define dso_local { float, double } @test127() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1154
; CHECK-NEXT: vldi $vr1, -898
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.8750000000, double 1.8750000000 }
@@ -1277,6 +1531,8 @@ define dso_local { float, double } @test128() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1153
; CHECK-NEXT: vldi $vr1, -897
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float 1.9375000000, double 1.9375000000 }
@@ -1287,6 +1543,8 @@ define dso_local { float, double } @test129() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1152
; CHECK-NEXT: vldi $vr1, -896
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.0000000000, double -2.0000000000 }
@@ -1297,6 +1555,8 @@ define dso_local { float, double } @test130() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1151
; CHECK-NEXT: vldi $vr1, -895
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.1250000000, double -2.1250000000 }
@@ -1307,6 +1567,8 @@ define dso_local { float, double } @test131() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1150
; CHECK-NEXT: vldi $vr1, -894
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.2500000000, double -2.2500000000 }
@@ -1317,6 +1579,8 @@ define dso_local { float, double } @test132() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1149
; CHECK-NEXT: vldi $vr1, -893
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.3750000000, double -2.3750000000 }
@@ -1327,6 +1591,8 @@ define dso_local { float, double } @test133() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1148
; CHECK-NEXT: vldi $vr1, -892
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.5000000000, double -2.5000000000 }
@@ -1337,6 +1603,8 @@ define dso_local { float, double } @test134() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1147
; CHECK-NEXT: vldi $vr1, -891
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.6250000000, double -2.6250000000 }
@@ -1347,6 +1615,8 @@ define dso_local { float, double } @test135() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1146
; CHECK-NEXT: vldi $vr1, -890
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.7500000000, double -2.7500000000 }
@@ -1357,6 +1627,8 @@ define dso_local { float, double } @test136() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1145
; CHECK-NEXT: vldi $vr1, -889
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -2.8750000000, double -2.8750000000 }
@@ -1367,6 +1639,8 @@ define dso_local { float, double } @test137() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1144
; CHECK-NEXT: vldi $vr1, -888
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.0000000000, double -3.0000000000 }
@@ -1377,6 +1651,8 @@ define dso_local { float, double } @test138() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1143
; CHECK-NEXT: vldi $vr1, -887
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.1250000000, double -3.1250000000 }
@@ -1387,6 +1663,8 @@ define dso_local { float, double } @test139() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1142
; CHECK-NEXT: vldi $vr1, -886
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.2500000000, double -3.2500000000 }
@@ -1397,6 +1675,8 @@ define dso_local { float, double } @test140() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1141
; CHECK-NEXT: vldi $vr1, -885
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.3750000000, double -3.3750000000 }
@@ -1407,6 +1687,8 @@ define dso_local { float, double } @test141() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1140
; CHECK-NEXT: vldi $vr1, -884
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.5000000000, double -3.5000000000 }
@@ -1417,6 +1699,8 @@ define dso_local { float, double } @test142() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1139
; CHECK-NEXT: vldi $vr1, -883
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.6250000000, double -3.6250000000 }
@@ -1427,6 +1711,8 @@ define dso_local { float, double } @test143() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1138
; CHECK-NEXT: vldi $vr1, -882
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.7500000000, double -3.7500000000 }
@@ -1437,6 +1723,8 @@ define dso_local { float, double } @test144() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1137
; CHECK-NEXT: vldi $vr1, -881
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -3.8750000000, double -3.8750000000 }
@@ -1447,6 +1735,8 @@ define dso_local { float, double } @test145() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1136
; CHECK-NEXT: vldi $vr1, -880
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -4.0000000000, double -4.0000000000 }
@@ -1457,6 +1747,8 @@ define dso_local { float, double } @test146() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1135
; CHECK-NEXT: vldi $vr1, -879
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -4.2500000000, double -4.2500000000 }
@@ -1467,6 +1759,8 @@ define dso_local { float, double } @test147() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1134
; CHECK-NEXT: vldi $vr1, -878
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -4.5000000000, double -4.5000000000 }
@@ -1477,6 +1771,8 @@ define dso_local { float, double } @test148() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1133
; CHECK-NEXT: vldi $vr1, -877
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -4.7500000000, double -4.7500000000 }
@@ -1487,6 +1783,8 @@ define dso_local { float, double } @test149() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1132
; CHECK-NEXT: vldi $vr1, -876
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -5.0000000000, double -5.0000000000 }
@@ -1497,6 +1795,8 @@ define dso_local { float, double } @test150() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1131
; CHECK-NEXT: vldi $vr1, -875
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -5.2500000000, double -5.2500000000 }
@@ -1507,6 +1807,8 @@ define dso_local { float, double } @test151() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1130
; CHECK-NEXT: vldi $vr1, -874
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -5.5000000000, double -5.5000000000 }
@@ -1517,6 +1819,8 @@ define dso_local { float, double } @test152() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1129
; CHECK-NEXT: vldi $vr1, -873
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -5.7500000000, double -5.7500000000 }
@@ -1527,6 +1831,8 @@ define dso_local { float, double } @test153() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1128
; CHECK-NEXT: vldi $vr1, -872
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -6.0000000000, double -6.0000000000 }
@@ -1537,6 +1843,8 @@ define dso_local { float, double } @test154() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1127
; CHECK-NEXT: vldi $vr1, -871
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -6.2500000000, double -6.2500000000 }
@@ -1547,6 +1855,8 @@ define dso_local { float, double } @test155() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1126
; CHECK-NEXT: vldi $vr1, -870
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -6.5000000000, double -6.5000000000 }
@@ -1557,6 +1867,8 @@ define dso_local { float, double } @test156() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1125
; CHECK-NEXT: vldi $vr1, -869
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -6.7500000000, double -6.7500000000 }
@@ -1567,6 +1879,8 @@ define dso_local { float, double } @test157() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1124
; CHECK-NEXT: vldi $vr1, -868
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -7.0000000000, double -7.0000000000 }
@@ -1577,6 +1891,8 @@ define dso_local { float, double } @test158() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1123
; CHECK-NEXT: vldi $vr1, -867
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -7.2500000000, double -7.2500000000 }
@@ -1587,6 +1903,8 @@ define dso_local { float, double } @test159() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1122
; CHECK-NEXT: vldi $vr1, -866
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -7.5000000000, double -7.5000000000 }
@@ -1597,6 +1915,8 @@ define dso_local { float, double } @test160() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1121
; CHECK-NEXT: vldi $vr1, -865
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -7.7500000000, double -7.7500000000 }
@@ -1607,6 +1927,8 @@ define dso_local { float, double } @test161() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1120
; CHECK-NEXT: vldi $vr1, -864
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -8.0000000000, double -8.0000000000 }
@@ -1617,6 +1939,8 @@ define dso_local { float, double } @test162() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1119
; CHECK-NEXT: vldi $vr1, -863
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -8.5000000000, double -8.5000000000 }
@@ -1627,6 +1951,8 @@ define dso_local { float, double } @test163() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1118
; CHECK-NEXT: vldi $vr1, -862
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -9.0000000000, double -9.0000000000 }
@@ -1637,6 +1963,8 @@ define dso_local { float, double } @test164() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1117
; CHECK-NEXT: vldi $vr1, -861
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -9.5000000000, double -9.5000000000 }
@@ -1647,6 +1975,8 @@ define dso_local { float, double } @test165() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1116
; CHECK-NEXT: vldi $vr1, -860
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -10.0000000000, double -10.0000000000 }
@@ -1657,6 +1987,8 @@ define dso_local { float, double } @test166() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1115
; CHECK-NEXT: vldi $vr1, -859
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -10.5000000000, double -10.5000000000 }
@@ -1667,6 +1999,8 @@ define dso_local { float, double } @test167() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1114
; CHECK-NEXT: vldi $vr1, -858
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -11.0000000000, double -11.0000000000 }
@@ -1677,6 +2011,8 @@ define dso_local { float, double } @test168() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1113
; CHECK-NEXT: vldi $vr1, -857
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -11.5000000000, double -11.5000000000 }
@@ -1687,6 +2023,8 @@ define dso_local { float, double } @test169() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1112
; CHECK-NEXT: vldi $vr1, -856
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -12.0000000000, double -12.0000000000 }
@@ -1697,6 +2035,8 @@ define dso_local { float, double } @test170() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1111
; CHECK-NEXT: vldi $vr1, -855
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -12.5000000000, double -12.5000000000 }
@@ -1707,6 +2047,8 @@ define dso_local { float, double } @test171() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1110
; CHECK-NEXT: vldi $vr1, -854
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -13.0000000000, double -13.0000000000 }
@@ -1717,6 +2059,8 @@ define dso_local { float, double } @test172() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1109
; CHECK-NEXT: vldi $vr1, -853
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -13.5000000000, double -13.5000000000 }
@@ -1727,6 +2071,8 @@ define dso_local { float, double } @test173() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1108
; CHECK-NEXT: vldi $vr1, -852
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -14.0000000000, double -14.0000000000 }
@@ -1737,6 +2083,8 @@ define dso_local { float, double } @test174() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1107
; CHECK-NEXT: vldi $vr1, -851
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -14.5000000000, double -14.5000000000 }
@@ -1747,6 +2095,8 @@ define dso_local { float, double } @test175() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1106
; CHECK-NEXT: vldi $vr1, -850
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -15.0000000000, double -15.0000000000 }
@@ -1757,6 +2107,8 @@ define dso_local { float, double } @test176() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1105
; CHECK-NEXT: vldi $vr1, -849
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -15.5000000000, double -15.5000000000 }
@@ -1767,6 +2119,8 @@ define dso_local { float, double } @test177() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1104
; CHECK-NEXT: vldi $vr1, -848
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -16.0000000000, double -16.0000000000 }
@@ -1777,6 +2131,8 @@ define dso_local { float, double } @test178() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1103
; CHECK-NEXT: vldi $vr1, -847
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -17.0000000000, double -17.0000000000 }
@@ -1787,6 +2143,8 @@ define dso_local { float, double } @test179() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1102
; CHECK-NEXT: vldi $vr1, -846
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -18.0000000000, double -18.0000000000 }
@@ -1797,6 +2155,8 @@ define dso_local { float, double } @test180() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1101
; CHECK-NEXT: vldi $vr1, -845
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -19.0000000000, double -19.0000000000 }
@@ -1807,6 +2167,8 @@ define dso_local { float, double } @test181() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1100
; CHECK-NEXT: vldi $vr1, -844
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -20.0000000000, double -20.0000000000 }
@@ -1817,6 +2179,8 @@ define dso_local { float, double } @test182() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1099
; CHECK-NEXT: vldi $vr1, -843
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -21.0000000000, double -21.0000000000 }
@@ -1827,6 +2191,8 @@ define dso_local { float, double } @test183() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1098
; CHECK-NEXT: vldi $vr1, -842
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -22.0000000000, double -22.0000000000 }
@@ -1837,6 +2203,8 @@ define dso_local { float, double } @test184() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1097
; CHECK-NEXT: vldi $vr1, -841
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -23.0000000000, double -23.0000000000 }
@@ -1847,6 +2215,8 @@ define dso_local { float, double } @test185() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1096
; CHECK-NEXT: vldi $vr1, -840
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -24.0000000000, double -24.0000000000 }
@@ -1857,6 +2227,8 @@ define dso_local { float, double } @test186() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1095
; CHECK-NEXT: vldi $vr1, -839
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -25.0000000000, double -25.0000000000 }
@@ -1867,6 +2239,8 @@ define dso_local { float, double } @test187() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1094
; CHECK-NEXT: vldi $vr1, -838
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -26.0000000000, double -26.0000000000 }
@@ -1877,6 +2251,8 @@ define dso_local { float, double } @test188() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1093
; CHECK-NEXT: vldi $vr1, -837
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -27.0000000000, double -27.0000000000 }
@@ -1887,6 +2263,8 @@ define dso_local { float, double } @test189() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1092
; CHECK-NEXT: vldi $vr1, -836
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -28.0000000000, double -28.0000000000 }
@@ -1897,6 +2275,8 @@ define dso_local { float, double } @test190() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1091
; CHECK-NEXT: vldi $vr1, -835
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -29.0000000000, double -29.0000000000 }
@@ -1907,6 +2287,8 @@ define dso_local { float, double } @test191() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1090
; CHECK-NEXT: vldi $vr1, -834
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -30.0000000000, double -30.0000000000 }
@@ -1917,6 +2299,8 @@ define dso_local { float, double } @test192() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1089
; CHECK-NEXT: vldi $vr1, -833
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -31.0000000000, double -31.0000000000 }
@@ -1927,6 +2311,8 @@ define dso_local { float, double } @test193() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1088
; CHECK-NEXT: vldi $vr1, -832
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1250000000, double -0.1250000000 }
@@ -1937,6 +2323,8 @@ define dso_local { float, double } @test194() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1087
; CHECK-NEXT: vldi $vr1, -831
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1328125000, double -0.1328125000 }
@@ -1947,6 +2335,8 @@ define dso_local { float, double } @test195() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1086
; CHECK-NEXT: vldi $vr1, -830
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1406250000, double -0.1406250000 }
@@ -1957,6 +2347,8 @@ define dso_local { float, double } @test196() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1085
; CHECK-NEXT: vldi $vr1, -829
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1484375000, double -0.1484375000 }
@@ -1967,6 +2359,8 @@ define dso_local { float, double } @test197() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1084
; CHECK-NEXT: vldi $vr1, -828
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1562500000, double -0.1562500000 }
@@ -1977,6 +2371,8 @@ define dso_local { float, double } @test198() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1083
; CHECK-NEXT: vldi $vr1, -827
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1640625000, double -0.1640625000 }
@@ -1987,6 +2383,8 @@ define dso_local { float, double } @test199() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1082
; CHECK-NEXT: vldi $vr1, -826
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1718750000, double -0.1718750000 }
@@ -1997,6 +2395,8 @@ define dso_local { float, double } @test200() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1081
; CHECK-NEXT: vldi $vr1, -825
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1796875000, double -0.1796875000 }
@@ -2007,6 +2407,8 @@ define dso_local { float, double } @test201() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1080
; CHECK-NEXT: vldi $vr1, -824
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1875000000, double -0.1875000000 }
@@ -2017,6 +2419,8 @@ define dso_local { float, double } @test202() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1079
; CHECK-NEXT: vldi $vr1, -823
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.1953125000, double -0.1953125000 }
@@ -2027,6 +2431,8 @@ define dso_local { float, double } @test203() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1078
; CHECK-NEXT: vldi $vr1, -822
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2031250000, double -0.2031250000 }
@@ -2037,6 +2443,8 @@ define dso_local { float, double } @test204() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1077
; CHECK-NEXT: vldi $vr1, -821
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2109375000, double -0.2109375000 }
@@ -2047,6 +2455,8 @@ define dso_local { float, double } @test205() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1076
; CHECK-NEXT: vldi $vr1, -820
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2187500000, double -0.2187500000 }
@@ -2057,6 +2467,8 @@ define dso_local { float, double } @test206() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1075
; CHECK-NEXT: vldi $vr1, -819
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2265625000, double -0.2265625000 }
@@ -2067,6 +2479,8 @@ define dso_local { float, double } @test207() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1074
; CHECK-NEXT: vldi $vr1, -818
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2343750000, double -0.2343750000 }
@@ -2077,6 +2491,8 @@ define dso_local { float, double } @test208() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1073
; CHECK-NEXT: vldi $vr1, -817
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2421875000, double -0.2421875000 }
@@ -2087,6 +2503,8 @@ define dso_local { float, double } @test209() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1072
; CHECK-NEXT: vldi $vr1, -816
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2500000000, double -0.2500000000 }
@@ -2097,6 +2515,8 @@ define dso_local { float, double } @test210() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1071
; CHECK-NEXT: vldi $vr1, -815
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2656250000, double -0.2656250000 }
@@ -2107,6 +2527,8 @@ define dso_local { float, double } @test211() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1070
; CHECK-NEXT: vldi $vr1, -814
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2812500000, double -0.2812500000 }
@@ -2117,6 +2539,8 @@ define dso_local { float, double } @test212() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1069
; CHECK-NEXT: vldi $vr1, -813
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.2968750000, double -0.2968750000 }
@@ -2127,6 +2551,8 @@ define dso_local { float, double } @test213() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1068
; CHECK-NEXT: vldi $vr1, -812
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.3125000000, double -0.3125000000 }
@@ -2137,6 +2563,8 @@ define dso_local { float, double } @test214() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1067
; CHECK-NEXT: vldi $vr1, -811
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.3281250000, double -0.3281250000 }
@@ -2147,6 +2575,8 @@ define dso_local { float, double } @test215() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1066
; CHECK-NEXT: vldi $vr1, -810
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.3437500000, double -0.3437500000 }
@@ -2157,6 +2587,8 @@ define dso_local { float, double } @test216() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1065
; CHECK-NEXT: vldi $vr1, -809
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.3593750000, double -0.3593750000 }
@@ -2167,6 +2599,8 @@ define dso_local { float, double } @test217() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1064
; CHECK-NEXT: vldi $vr1, -808
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.3750000000, double -0.3750000000 }
@@ -2177,6 +2611,8 @@ define dso_local { float, double } @test218() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1063
; CHECK-NEXT: vldi $vr1, -807
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.3906250000, double -0.3906250000 }
@@ -2187,6 +2623,8 @@ define dso_local { float, double } @test219() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1062
; CHECK-NEXT: vldi $vr1, -806
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.4062500000, double -0.4062500000 }
@@ -2197,6 +2635,8 @@ define dso_local { float, double } @test220() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1061
; CHECK-NEXT: vldi $vr1, -805
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.4218750000, double -0.4218750000 }
@@ -2207,6 +2647,8 @@ define dso_local { float, double } @test221() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1060
; CHECK-NEXT: vldi $vr1, -804
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.4375000000, double -0.4375000000 }
@@ -2217,6 +2659,8 @@ define dso_local { float, double } @test222() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1059
; CHECK-NEXT: vldi $vr1, -803
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.4531250000, double -0.4531250000 }
@@ -2227,6 +2671,8 @@ define dso_local { float, double } @test223() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1058
; CHECK-NEXT: vldi $vr1, -802
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.4687500000, double -0.4687500000 }
@@ -2237,6 +2683,8 @@ define dso_local { float, double } @test224() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1057
; CHECK-NEXT: vldi $vr1, -801
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.4843750000, double -0.4843750000 }
@@ -2247,6 +2695,8 @@ define dso_local { float, double } @test225() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1056
; CHECK-NEXT: vldi $vr1, -800
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.5000000000, double -0.5000000000 }
@@ -2257,6 +2707,8 @@ define dso_local { float, double } @test226() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1055
; CHECK-NEXT: vldi $vr1, -799
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.5312500000, double -0.5312500000 }
@@ -2267,6 +2719,8 @@ define dso_local { float, double } @test227() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1054
; CHECK-NEXT: vldi $vr1, -798
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.5625000000, double -0.5625000000 }
@@ -2277,6 +2731,8 @@ define dso_local { float, double } @test228() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1053
; CHECK-NEXT: vldi $vr1, -797
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.5937500000, double -0.5937500000 }
@@ -2287,6 +2743,8 @@ define dso_local { float, double } @test229() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1052
; CHECK-NEXT: vldi $vr1, -796
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.6250000000, double -0.6250000000 }
@@ -2297,6 +2755,8 @@ define dso_local { float, double } @test230() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1051
; CHECK-NEXT: vldi $vr1, -795
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.6562500000, double -0.6562500000 }
@@ -2307,6 +2767,8 @@ define dso_local { float, double } @test231() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1050
; CHECK-NEXT: vldi $vr1, -794
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.6875000000, double -0.6875000000 }
@@ -2317,6 +2779,8 @@ define dso_local { float, double } @test232() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1049
; CHECK-NEXT: vldi $vr1, -793
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.7187500000, double -0.7187500000 }
@@ -2327,6 +2791,8 @@ define dso_local { float, double } @test233() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1048
; CHECK-NEXT: vldi $vr1, -792
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.7500000000, double -0.7500000000 }
@@ -2337,6 +2803,8 @@ define dso_local { float, double } @test234() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1047
; CHECK-NEXT: vldi $vr1, -791
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.7812500000, double -0.7812500000 }
@@ -2347,6 +2815,8 @@ define dso_local { float, double } @test235() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1046
; CHECK-NEXT: vldi $vr1, -790
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.8125000000, double -0.8125000000 }
@@ -2357,6 +2827,8 @@ define dso_local { float, double } @test236() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1045
; CHECK-NEXT: vldi $vr1, -789
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.8437500000, double -0.8437500000 }
@@ -2367,6 +2839,8 @@ define dso_local { float, double } @test237() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1044
; CHECK-NEXT: vldi $vr1, -788
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.8750000000, double -0.8750000000 }
@@ -2377,6 +2851,8 @@ define dso_local { float, double } @test238() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1043
; CHECK-NEXT: vldi $vr1, -787
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.9062500000, double -0.9062500000 }
@@ -2387,6 +2863,8 @@ define dso_local { float, double } @test239() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1042
; CHECK-NEXT: vldi $vr1, -786
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.9375000000, double -0.9375000000 }
@@ -2397,6 +2875,8 @@ define dso_local { float, double } @test240() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1041
; CHECK-NEXT: vldi $vr1, -785
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -0.9687500000, double -0.9687500000 }
@@ -2407,6 +2887,8 @@ define dso_local { float, double } @test241() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1040
; CHECK-NEXT: vldi $vr1, -784
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.0000000000, double -1.0000000000 }
@@ -2417,6 +2899,8 @@ define dso_local { float, double } @test242() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1039
; CHECK-NEXT: vldi $vr1, -783
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.0625000000, double -1.0625000000 }
@@ -2427,6 +2911,8 @@ define dso_local { float, double } @test243() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1038
; CHECK-NEXT: vldi $vr1, -782
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.1250000000, double -1.1250000000 }
@@ -2437,6 +2923,8 @@ define dso_local { float, double } @test244() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1037
; CHECK-NEXT: vldi $vr1, -781
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.1875000000, double -1.1875000000 }
@@ -2447,6 +2935,8 @@ define dso_local { float, double } @test245() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1036
; CHECK-NEXT: vldi $vr1, -780
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.2500000000, double -1.2500000000 }
@@ -2457,6 +2947,8 @@ define dso_local { float, double } @test246() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1035
; CHECK-NEXT: vldi $vr1, -779
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.3125000000, double -1.3125000000 }
@@ -2467,6 +2959,8 @@ define dso_local { float, double } @test247() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1034
; CHECK-NEXT: vldi $vr1, -778
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.3750000000, double -1.3750000000 }
@@ -2477,6 +2971,8 @@ define dso_local { float, double } @test248() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1033
; CHECK-NEXT: vldi $vr1, -777
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.4375000000, double -1.4375000000 }
@@ -2487,6 +2983,8 @@ define dso_local { float, double } @test249() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1032
; CHECK-NEXT: vldi $vr1, -776
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.5000000000, double -1.5000000000 }
@@ -2497,6 +2995,8 @@ define dso_local { float, double } @test250() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1031
; CHECK-NEXT: vldi $vr1, -775
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.5625000000, double -1.5625000000 }
@@ -2507,6 +3007,8 @@ define dso_local { float, double } @test251() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1030
; CHECK-NEXT: vldi $vr1, -774
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.6250000000, double -1.6250000000 }
@@ -2517,6 +3019,8 @@ define dso_local { float, double } @test252() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1029
; CHECK-NEXT: vldi $vr1, -773
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.6875000000, double -1.6875000000 }
@@ -2527,6 +3031,8 @@ define dso_local { float, double } @test253() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1028
; CHECK-NEXT: vldi $vr1, -772
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.7500000000, double -1.7500000000 }
@@ -2537,6 +3043,8 @@ define dso_local { float, double } @test254() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1027
; CHECK-NEXT: vldi $vr1, -771
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.8125000000, double -1.8125000000 }
@@ -2547,6 +3055,8 @@ define dso_local { float, double } @test255() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1026
; CHECK-NEXT: vldi $vr1, -770
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.8750000000, double -1.8750000000 }
@@ -2557,6 +3067,8 @@ define dso_local { float, double } @test256() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vldi $vr0, -1025
; CHECK-NEXT: vldi $vr1, -769
+; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1
; CHECK-NEXT: ret
entry:
ret { float, double } { float -1.9375000000, double -1.9375000000 }
diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll
index bb3c7c27a122d..28f3691141ad8 100644
--- a/llvm/test/CodeGen/Mips/cmov.ll
+++ b/llvm/test/CodeGen/Mips/cmov.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
; RUN: llc -mtriple=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
@@ -39,6 +40,56 @@
; 64-CMP-DAG: ld $2, 0($[[T2]])
define ptr @cmov1(i32 signext %s) nounwind readonly {
+; 32-CMOV-LABEL: cmov1:
+; 32-CMOV: # %bb.0: # %entry
+; 32-CMOV-NEXT: lui $2, %hi(_gp_disp)
+; 32-CMOV-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-CMOV-NEXT: addu $1, $2, $25
+; 32-CMOV-NEXT: lw $2, %got(i3)($1)
+; 32-CMOV-NEXT: addiu $1, $1, %got(i1)
+; 32-CMOV-NEXT: movn $2, $1, $4
+; 32-CMOV-NEXT: lw $2, 0($2)
+; 32-CMOV-NEXT: jr $ra
+; 32-CMOV-NEXT: nop
+;
+; 32-CMP-LABEL: cmov1:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: lui $2, %hi(_gp_disp)
+; 32-CMP-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-CMP-NEXT: addu $1, $2, $25
+; 32-CMP-NEXT: lw $2, %got(i3)($1)
+; 32-CMP-NEXT: seleqz $2, $2, $4
+; 32-CMP-NEXT: addiu $1, $1, %got(i1)
+; 32-CMP-NEXT: selnez $1, $1, $4
+; 32-CMP-NEXT: or $1, $1, $2
+; 32-CMP-NEXT: lw $2, 0($1)
+; 32-CMP-NEXT: jrc $ra
+;
+; 64-CMOV-LABEL: cmov1:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: lui $1, %hi(%neg(%gp_rel(cmov1)))
+; 64-CMOV-NEXT: daddu $1, $1, $25
+; 64-CMOV-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(cmov1)))
+; 64-CMOV-NEXT: ld $3, %got_disp(i3)($1)
+; 64-CMOV-NEXT: ldl $2, 7($3)
+; 64-CMOV-NEXT: ldr $2, 0($3)
+; 64-CMOV-NEXT: ld $1, %got_disp(i1)($1)
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $1, $4
+;
+; 64-CMP-LABEL: cmov1:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: lui $1, %hi(%neg(%gp_rel(cmov1)))
+; 64-CMP-NEXT: daddu $1, $1, $25
+; 64-CMP-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(cmov1)))
+; 64-CMP-NEXT: sll $2, $4, 0
+; 64-CMP-NEXT: ld $3, %got_disp(i3)($1)
+; 64-CMP-NEXT: seleqz $3, $3, $2
+; 64-CMP-NEXT: daddiu $1, $1, %got_disp(i1)
+; 64-CMP-NEXT: selnez $1, $1, $2
+; 64-CMP-NEXT: or $1, $1, $3
+; 64-CMP-NEXT: ld $2, 0($1)
+; 64-CMP-NEXT: jrc $ra
entry:
%tobool = icmp ne i32 %s, 0
%tmp1 = load ptr, ptr @i3, align 4
@@ -79,6 +130,60 @@ entry:
; 64-CMP-DAG: lw $2, 0($[[T2]])
define i32 @cmov2(i32 signext %s) nounwind readonly {
+; 32-CMOV-LABEL: cmov2:
+; 32-CMOV: # %bb.0: # %entry
+; 32-CMOV-NEXT: lui $2, %hi(_gp_disp)
+; 32-CMOV-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-CMOV-NEXT: addu $1, $2, $25
+; 32-CMOV-NEXT: addiu $2, $1, %got(d)
+; 32-CMOV-NEXT: addiu $1, $1, %got(c)
+; 32-CMOV-NEXT: movn $2, $1, $4
+; 32-CMOV-NEXT: lw $1, 0($2)
+; 32-CMOV-NEXT: lw $2, 0($1)
+; 32-CMOV-NEXT: jr $ra
+; 32-CMOV-NEXT: nop
+;
+; 32-CMP-LABEL: cmov2:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: lui $2, %hi(_gp_disp)
+; 32-CMP-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-CMP-NEXT: addu $1, $2, $25
+; 32-CMP-NEXT: addiu $2, $1, %got(d)
+; 32-CMP-NEXT: seleqz $2, $2, $4
+; 32-CMP-NEXT: addiu $1, $1, %got(c)
+; 32-CMP-NEXT: selnez $1, $1, $4
+; 32-CMP-NEXT: or $1, $1, $2
+; 32-CMP-NEXT: lw $1, 0($1)
+; 32-CMP-NEXT: lw $2, 0($1)
+; 32-CMP-NEXT: jrc $ra
+;
+; 64-CMOV-LABEL: cmov2:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: lui $1, %hi(%neg(%gp_rel(cmov2)))
+; 64-CMOV-NEXT: daddu $1, $1, $25
+; 64-CMOV-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(cmov2)))
+; 64-CMOV-NEXT: daddiu $2, $1, %got_disp(d)
+; 64-CMOV-NEXT: daddiu $1, $1, %got_disp(c)
+; 64-CMOV-NEXT: movn $2, $1, $4
+; 64-CMOV-NEXT: ld $1, 0($2)
+; 64-CMOV-NEXT: lw $2, 0($1)
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: nop
+;
+; 64-CMP-LABEL: cmov2:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: lui $1, %hi(%neg(%gp_rel(cmov2)))
+; 64-CMP-NEXT: daddu $1, $1, $25
+; 64-CMP-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(cmov2)))
+; 64-CMP-NEXT: sll $2, $4, 0
+; 64-CMP-NEXT: daddiu $3, $1, %got_disp(d)
+; 64-CMP-NEXT: seleqz $3, $3, $2
+; 64-CMP-NEXT: daddiu $1, $1, %got_disp(c)
+; 64-CMP-NEXT: selnez $1, $1, $2
+; 64-CMP-NEXT: or $1, $1, $3
+; 64-CMP-NEXT: ld $1, 0($1)
+; 64-CMP-NEXT: lw $2, 0($1)
+; 64-CMP-NEXT: jrc $ra
entry:
%tobool = icmp ne i32 %s, 0
%tmp1 = load i32, ptr @c, align 4
@@ -110,6 +215,35 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @cmov3(i32 signext %a, i32 signext %b, i32 signext %c) nounwind readnone {
+; 32-CMOV-LABEL: cmov3:
+; 32-CMOV: # %bb.0: # %entry
+; 32-CMOV-NEXT: xori $1, $4, 234
+; 32-CMOV-NEXT: movz $6, $5, $1
+; 32-CMOV-NEXT: jr $ra
+; 32-CMOV-NEXT: move $2, $6
+;
+; 32-CMP-LABEL: cmov3:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: xori $1, $4, 234
+; 32-CMP-NEXT: selnez $2, $6, $1
+; 32-CMP-NEXT: seleqz $1, $5, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: cmov3:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: xori $1, $4, 234
+; 64-CMOV-NEXT: movz $6, $5, $1
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: move $2, $6
+;
+; 64-CMP-LABEL: cmov3:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: xori $1, $4, 234
+; 64-CMP-NEXT: selnez $2, $6, $1
+; 64-CMP-NEXT: seleqz $1, $5, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp eq i32 %a, 234
%cond = select i1 %cmp, i32 %b, i32 %c
@@ -143,6 +277,37 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @cmov3_ne(i32 signext %a, i32 signext %b, i32 signext %c) nounwind readnone {
+; 32-CMOV-LABEL: cmov3_ne:
+; 32-CMOV: # %bb.0: # %entry
+; 32-CMOV-NEXT: addiu $1, $zero, 234
+; 32-CMOV-NEXT: xor $1, $4, $1
+; 32-CMOV-NEXT: movn $6, $5, $1
+; 32-CMOV-NEXT: jr $ra
+; 32-CMOV-NEXT: move $2, $6
+;
+; 32-CMP-LABEL: cmov3_ne:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: xori $1, $4, 234
+; 32-CMP-NEXT: seleqz $2, $6, $1
+; 32-CMP-NEXT: selnez $1, $5, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: cmov3_ne:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: addiu $1, $zero, 234
+; 64-CMOV-NEXT: xor $1, $4, $1
+; 64-CMOV-NEXT: movn $6, $5, $1
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: move $2, $6
+;
+; 64-CMP-LABEL: cmov3_ne:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: xori $1, $4, 234
+; 64-CMP-NEXT: seleqz $2, $6, $1
+; 64-CMP-NEXT: selnez $1, $5, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp ne i32 %a, 234
%cond = select i1 %cmp, i32 %b, i32 %c
@@ -180,6 +345,43 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @cmov4(i32 signext %a, i64 %b, i64 %c) nounwind readnone {
+; 32-CMOV-LABEL: cmov4:
+; 32-CMOV: # %bb.0: # %entry
+; 32-CMOV-NEXT: xori $1, $4, 234
+; 32-CMOV-NEXT: lw $2, 16($sp)
+; 32-CMOV-NEXT: movz $2, $6, $1
+; 32-CMOV-NEXT: lw $3, 20($sp)
+; 32-CMOV-NEXT: jr $ra
+; 32-CMOV-NEXT: movz $3, $7, $1
+;
+; 32-CMP-LABEL: cmov4:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: xori $1, $4, 234
+; 32-CMP-NEXT: lw $2, 16($sp)
+; 32-CMP-NEXT: selnez $2, $2, $1
+; 32-CMP-NEXT: seleqz $3, $6, $1
+; 32-CMP-NEXT: or $2, $3, $2
+; 32-CMP-NEXT: lw $3, 20($sp)
+; 32-CMP-NEXT: selnez $3, $3, $1
+; 32-CMP-NEXT: seleqz $1, $7, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $3, $1, $3
+;
+; 64-CMOV-LABEL: cmov4:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: xori $1, $4, 234
+; 64-CMOV-NEXT: movz $6, $5, $1
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: move $2, $6
+;
+; 64-CMP-LABEL: cmov4:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: xori $1, $4, 234
+; 64-CMP-NEXT: sll $1, $1, 0
+; 64-CMP-NEXT: selnez $2, $6, $1
+; 64-CMP-NEXT: seleqz $1, $5, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp eq i32 %a, 234
%cond = select i1 %cmp, i64 %b, i64 %c
@@ -221,6 +423,45 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @cmov4_ne(i32 signext %a, i64 %b, i64 %c) nounwind readnone {
+; 32-CMOV-LABEL: cmov4_ne:
+; 32-CMOV: # %bb.0: # %entry
+; 32-CMOV-NEXT: addiu $1, $zero, 234
+; 32-CMOV-NEXT: xor $1, $4, $1
+; 32-CMOV-NEXT: lw $2, 16($sp)
+; 32-CMOV-NEXT: movn $2, $6, $1
+; 32-CMOV-NEXT: lw $3, 20($sp)
+; 32-CMOV-NEXT: jr $ra
+; 32-CMOV-NEXT: movn $3, $7, $1
+;
+; 32-CMP-LABEL: cmov4_ne:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: xori $1, $4, 234
+; 32-CMP-NEXT: lw $2, 16($sp)
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: selnez $3, $6, $1
+; 32-CMP-NEXT: or $2, $3, $2
+; 32-CMP-NEXT: lw $3, 20($sp)
+; 32-CMP-NEXT: seleqz $3, $3, $1
+; 32-CMP-NEXT: selnez $1, $7, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $3, $1, $3
+;
+; 64-CMOV-LABEL: cmov4_ne:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: addiu $1, $zero, 234
+; 64-CMOV-NEXT: xor $1, $4, $1
+; 64-CMOV-NEXT: movn $6, $5, $1
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: move $2, $6
+;
+; 64-CMP-LABEL: cmov4_ne:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: xori $1, $4, 234
+; 64-CMP-NEXT: sll $1, $1, 0
+; 64-CMP-NEXT: seleqz $2, $6, $1
+; 64-CMP-NEXT: selnez $1, $5, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp ne i32 %a, 234
%cond = select i1 %cmp, i64 %b, i64 %c
@@ -264,6 +505,33 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @slti0(i32 signext %a) {
+; 32-CMP-LABEL: slti0:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: slti $1, $4, 32767
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: selnez $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: seleqz $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: slti0:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: slti $1, $4, 32767
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movz $2, $3, $1
+;
+; 64-CMP-LABEL: slti0:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: slti $1, $4, 32767
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: selnez $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 3
+; 64-CMP-NEXT: seleqz $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i32 %a, 32766
%cond = select i1 %cmp, i32 3, i32 5
@@ -303,6 +571,36 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @slti1(i32 signext %a) {
+; 32-CMP-LABEL: slti1:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: addiu $1, $zero, 32767
+; 32-CMP-NEXT: slt $1, $1, $4
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 7
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: slti1:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: addiu $1, $zero, 32767
+; 64-CMOV-NEXT: slt $1, $1, $4
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 7
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $3, $1
+;
+; 64-CMP-LABEL: slti1:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: addiu $1, $zero, 32767
+; 64-CMP-NEXT: slt $1, $1, $4
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: seleqz $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 7
+; 64-CMP-NEXT: selnez $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i32 %a, 32767
%cond = select i1 %cmp, i32 7, i32 5
@@ -338,6 +636,33 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @slti2(i32 signext %a) {
+; 32-CMP-LABEL: slti2:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: slti $1, $4, -32768
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: selnez $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: seleqz $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: slti2:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: slti $1, $4, -32768
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movz $2, $3, $1
+;
+; 64-CMP-LABEL: slti2:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: slti $1, $4, -32768
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: selnez $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 3
+; 64-CMP-NEXT: seleqz $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i32 %a, -32769
%cond = select i1 %cmp, i32 3, i32 5
@@ -381,6 +706,39 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @slti3(i32 signext %a) {
+; 32-CMP-LABEL: slti3:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: lui $1, 65535
+; 32-CMP-NEXT: ori $1, $1, 32766
+; 32-CMP-NEXT: slt $1, $1, $4
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: slti3:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: lui $1, 65535
+; 64-CMOV-NEXT: ori $1, $1, 32766
+; 64-CMOV-NEXT: slt $1, $1, $4
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $3, $1
+;
+; 64-CMP-LABEL: slti3:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: lui $1, 65535
+; 64-CMP-NEXT: ori $1, $1, 32766
+; 64-CMP-NEXT: slt $1, $1, $4
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: seleqz $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 3
+; 64-CMP-NEXT: selnez $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i32 %a, -32770
%cond = select i1 %cmp, i32 3, i32 5
@@ -428,6 +786,39 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @slti64_0(i64 %a) {
+; 32-CMP-LABEL: slti64_0:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: addiu $2, $zero, 0
+; 32-CMP-NEXT: slt $1, $zero, $4
+; 32-CMP-NEXT: selnez $1, $1, $4
+; 32-CMP-NEXT: addiu $3, $zero, 32766
+; 32-CMP-NEXT: sltu $3, $3, $5
+; 32-CMP-NEXT: seleqz $3, $3, $4
+; 32-CMP-NEXT: or $1, $3, $1
+; 32-CMP-NEXT: addiu $3, $zero, 4
+; 32-CMP-NEXT: seleqz $3, $3, $1
+; 32-CMP-NEXT: addiu $4, $zero, 5
+; 32-CMP-NEXT: selnez $1, $4, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $3, $1, $3
+;
+; 64-CMOV-LABEL: slti64_0:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: slti $1, $4, 32767
+; 64-CMOV-NEXT: daddiu $2, $zero, 4
+; 64-CMOV-NEXT: daddiu $3, $zero, 5
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movz $2, $3, $1
+;
+; 64-CMP-LABEL: slti64_0:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: slti $1, $4, 32767
+; 64-CMP-NEXT: daddiu $2, $zero, 4
+; 64-CMP-NEXT: selnez $2, $2, $1
+; 64-CMP-NEXT: daddiu $3, $zero, 5
+; 64-CMP-NEXT: seleqz $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i64 %a, 32766
%conv = select i1 %cmp, i64 5, i64 4
@@ -474,6 +865,42 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @slti64_1(i64 %a) {
+; 32-CMP-LABEL: slti64_1:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: addiu $2, $zero, 0
+; 32-CMP-NEXT: slt $1, $zero, $4
+; 32-CMP-NEXT: selnez $1, $1, $4
+; 32-CMP-NEXT: addiu $3, $zero, 32767
+; 32-CMP-NEXT: sltu $3, $3, $5
+; 32-CMP-NEXT: seleqz $3, $3, $4
+; 32-CMP-NEXT: or $1, $3, $1
+; 32-CMP-NEXT: addiu $3, $zero, 4
+; 32-CMP-NEXT: seleqz $3, $3, $1
+; 32-CMP-NEXT: addiu $4, $zero, 5
+; 32-CMP-NEXT: selnez $1, $4, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $3, $1, $3
+;
+; 64-CMOV-LABEL: slti64_1:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: daddiu $1, $zero, 32767
+; 64-CMOV-NEXT: slt $1, $1, $4
+; 64-CMOV-NEXT: daddiu $2, $zero, 4
+; 64-CMOV-NEXT: daddiu $3, $zero, 5
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $3, $1
+;
+; 64-CMP-LABEL: slti64_1:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: daddiu $1, $zero, 32767
+; 64-CMP-NEXT: slt $1, $1, $4
+; 64-CMP-NEXT: sll $1, $1, 0
+; 64-CMP-NEXT: daddiu $2, $zero, 4
+; 64-CMP-NEXT: seleqz $2, $2, $1
+; 64-CMP-NEXT: daddiu $3, $zero, 5
+; 64-CMP-NEXT: selnez $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i64 %a, 32767
%conv = select i1 %cmp, i64 5, i64 4
@@ -502,6 +929,43 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @slti64_2(i64 %a) {
+; 32-CMP-LABEL: slti64_2:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: addiu $1, $zero, -1
+; 32-CMP-NEXT: slt $2, $1, $4
+; 32-CMP-NEXT: xor $1, $4, $1
+; 32-CMP-NEXT: sltiu $1, $1, 1
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: lui $3, 65535
+; 32-CMP-NEXT: ori $3, $3, 32767
+; 32-CMP-NEXT: sltu $3, $3, $5
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: or $1, $1, $2
+; 32-CMP-NEXT: addiu $2, $zero, 4
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: or $3, $1, $2
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: addiu $2, $zero, 0
+;
+; 64-CMOV-LABEL: slti64_2:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: slti $1, $4, -32768
+; 64-CMOV-NEXT: daddiu $2, $zero, 4
+; 64-CMOV-NEXT: daddiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movz $2, $3, $1
+;
+; 64-CMP-LABEL: slti64_2:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: slti $1, $4, -32768
+; 64-CMP-NEXT: daddiu $2, $zero, 4
+; 64-CMP-NEXT: selnez $2, $2, $1
+; 64-CMP-NEXT: daddiu $3, $zero, 3
+; 64-CMP-NEXT: seleqz $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i64 %a, -32769
%conv = select i1 %cmp, i64 3, i64 4
@@ -536,6 +1000,48 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @slti64_3(i64 %a) {
+; 32-CMP-LABEL: slti64_3:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: addiu $1, $zero, -1
+; 32-CMP-NEXT: slt $2, $1, $4
+; 32-CMP-NEXT: xor $1, $4, $1
+; 32-CMP-NEXT: sltiu $1, $1, 1
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: lui $3, 65535
+; 32-CMP-NEXT: ori $3, $3, 32766
+; 32-CMP-NEXT: sltu $3, $3, $5
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: or $1, $1, $2
+; 32-CMP-NEXT: addiu $2, $zero, 4
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 5
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: or $3, $1, $2
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: addiu $2, $zero, 0
+;
+; 64-CMOV-LABEL: slti64_3:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: lui $1, 65535
+; 64-CMOV-NEXT: ori $1, $1, 32766
+; 64-CMOV-NEXT: slt $1, $1, $4
+; 64-CMOV-NEXT: daddiu $2, $zero, 4
+; 64-CMOV-NEXT: daddiu $3, $zero, 5
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $3, $1
+;
+; 64-CMP-LABEL: slti64_3:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: lui $1, 65535
+; 64-CMP-NEXT: ori $1, $1, 32766
+; 64-CMP-NEXT: slt $1, $1, $4
+; 64-CMP-NEXT: sll $1, $1, 0
+; 64-CMP-NEXT: daddiu $2, $zero, 4
+; 64-CMP-NEXT: seleqz $2, $2, $1
+; 64-CMP-NEXT: daddiu $3, $zero, 5
+; 64-CMP-NEXT: selnez $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp sgt i64 %a, -32770
%conv = select i1 %cmp, i64 5, i64 4
@@ -573,6 +1079,33 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @sltiu0(i32 signext %a) {
+; 32-CMP-LABEL: sltiu0:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: sltiu $1, $4, 32767
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: selnez $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: seleqz $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: sltiu0:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: sltiu $1, $4, 32767
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movz $2, $3, $1
+;
+; 64-CMP-LABEL: sltiu0:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: sltiu $1, $4, 32767
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: selnez $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 3
+; 64-CMP-NEXT: seleqz $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp ugt i32 %a, 32766
%cond = select i1 %cmp, i32 3, i32 5
@@ -612,6 +1145,36 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @sltiu1(i32 signext %a) {
+; 32-CMP-LABEL: sltiu1:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: addiu $1, $zero, 32767
+; 32-CMP-NEXT: sltu $1, $1, $4
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 7
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: sltiu1:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: addiu $1, $zero, 32767
+; 64-CMOV-NEXT: sltu $1, $1, $4
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 7
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $3, $1
+;
+; 64-CMP-LABEL: sltiu1:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: addiu $1, $zero, 32767
+; 64-CMP-NEXT: sltu $1, $1, $4
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: seleqz $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 7
+; 64-CMP-NEXT: selnez $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp ugt i32 %a, 32767
%cond = select i1 %cmp, i32 7, i32 5
@@ -647,6 +1210,33 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @sltiu2(i32 signext %a) {
+; 32-CMP-LABEL: sltiu2:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: sltiu $1, $4, -32768
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: selnez $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: seleqz $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: sltiu2:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: sltiu $1, $4, -32768
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movz $2, $3, $1
+;
+; 64-CMP-LABEL: sltiu2:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: sltiu $1, $4, -32768
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: selnez $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 3
+; 64-CMP-NEXT: seleqz $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp ugt i32 %a, -32769
%cond = select i1 %cmp, i32 3, i32 5
@@ -690,6 +1280,39 @@ entry:
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i32 @sltiu3(i32 signext %a) {
+; 32-CMP-LABEL: sltiu3:
+; 32-CMP: # %bb.0: # %entry
+; 32-CMP-NEXT: lui $1, 65535
+; 32-CMP-NEXT: ori $1, $1, 32766
+; 32-CMP-NEXT: sltu $1, $1, $4
+; 32-CMP-NEXT: addiu $2, $zero, 5
+; 32-CMP-NEXT: seleqz $2, $2, $1
+; 32-CMP-NEXT: addiu $3, $zero, 3
+; 32-CMP-NEXT: selnez $1, $3, $1
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: sltiu3:
+; 64-CMOV: # %bb.0: # %entry
+; 64-CMOV-NEXT: lui $1, 65535
+; 64-CMOV-NEXT: ori $1, $1, 32766
+; 64-CMOV-NEXT: sltu $1, $1, $4
+; 64-CMOV-NEXT: addiu $2, $zero, 5
+; 64-CMOV-NEXT: addiu $3, $zero, 3
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: movn $2, $3, $1
+;
+; 64-CMP-LABEL: sltiu3:
+; 64-CMP: # %bb.0: # %entry
+; 64-CMP-NEXT: lui $1, 65535
+; 64-CMP-NEXT: ori $1, $1, 32766
+; 64-CMP-NEXT: sltu $1, $1, $4
+; 64-CMP-NEXT: addiu $2, $zero, 5
+; 64-CMP-NEXT: seleqz $2, $2, $1
+; 64-CMP-NEXT: addiu $3, $zero, 3
+; 64-CMP-NEXT: selnez $1, $3, $1
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
entry:
%cmp = icmp ugt i32 %a, -32770
%cond = select i1 %cmp, i32 3, i32 5
@@ -703,6 +1326,11 @@ entry:
; for constant operands whose difference is |1|
define i32 @slti4(i32 signext %a) nounwind readnone {
+; ALL-LABEL: slti4:
+; ALL: # %bb.0:
+; ALL-NEXT: slti $1, $4, 7
+; ALL-NEXT: jr $ra
+; ALL-NEXT: addiu $2, $1, 3
%1 = icmp slt i32 %a, 7
%2 = select i1 %1, i32 4, i32 3
ret i32 %2
@@ -729,6 +1357,26 @@ define i32 @slti4(i32 signext %a) nounwind readnone {
; 64-CMP-NOT: selnez
define i32 @slti5(i32 signext %a) nounwind readnone {
+; 32-CMP-LABEL: slti5:
+; 32-CMP: # %bb.0:
+; 32-CMP-NEXT: slti $1, $4, 7
+; 32-CMP-NEXT: addiu $2, $zero, -4
+; 32-CMP-NEXT: jr $ra
+; 32-CMP-NEXT: or $2, $1, $2
+;
+; 64-CMOV-LABEL: slti5:
+; 64-CMOV: # %bb.0:
+; 64-CMOV-NEXT: slti $1, $4, 7
+; 64-CMOV-NEXT: addiu $2, $zero, -4
+; 64-CMOV-NEXT: jr $ra
+; 64-CMOV-NEXT: or $2, $1, $2
+;
+; 64-CMP-LABEL: slti5:
+; 64-CMP: # %bb.0:
+; 64-CMP-NEXT: slti $1, $4, 7
+; 64-CMP-NEXT: addiu $2, $zero, -4
+; 64-CMP-NEXT: jr $ra
+; 64-CMP-NEXT: or $2, $1, $2
%1 = icmp slt i32 %a, 7
%2 = select i1 %1, i32 -3, i32 -4
ret i32 %2
@@ -755,6 +1403,12 @@ define i32 @slti5(i32 signext %a) nounwind readnone {
; 64-CMP-NOT: selnez
define i32 @slti6(i32 signext %a) nounwind readnone {
+; ALL-LABEL: slti6:
+; ALL: # %bb.0:
+; ALL-NEXT: addiu $1, $zero, 6
+; ALL-NEXT: slt $1, $1, $4
+; ALL-NEXT: jr $ra
+; ALL-NEXT: addiu $2, $1, 3
%1 = icmp slt i32 %a, 7
%2 = select i1 %1, i32 3, i32 4
ret i32 %2
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
index 87f7edb2b7132..9df803c52d19f 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
@@ -591,26 +591,26 @@ define signext i128 @and_i128_4(i128 signext %b) {
; MIPS-LABEL: and_i128_4:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $5, $7, 4
-; MIPS-NEXT: addiu $2, $zero, 0
-; MIPS-NEXT: addiu $3, $zero, 0
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $4, $zero, 0
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: move $3, $4
;
; MIPS32R2-LABEL: and_i128_4:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: andi $5, $7, 4
-; MIPS32R2-NEXT: addiu $2, $zero, 0
-; MIPS32R2-NEXT: addiu $3, $zero, 0
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: addiu $4, $zero, 0
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: move $3, $4
;
; MIPS32R6-LABEL: and_i128_4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: andi $5, $7, 4
-; MIPS32R6-NEXT: addiu $2, $zero, 0
-; MIPS32R6-NEXT: addiu $3, $zero, 0
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: addiu $4, $zero, 0
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: move $3, $4
;
; MIPS64-LABEL: and_i128_4:
; MIPS64: # %bb.0: # %entry
@@ -633,17 +633,17 @@ define signext i128 @and_i128_4(i128 signext %b) {
; MM32R3-LABEL: and_i128_4:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: andi16 $5, $7, 4
-; MM32R3-NEXT: li16 $2, 0
-; MM32R3-NEXT: li16 $3, 0
; MM32R3-NEXT: li16 $4, 0
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: move $3, $4
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i128_4:
; MM32R6: # %bb.0: # %entry
; MM32R6-NEXT: andi16 $5, $7, 4
-; MM32R6-NEXT: li16 $2, 0
-; MM32R6-NEXT: li16 $3, 0
; MM32R6-NEXT: li16 $4, 0
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: move $3, $4
; MM32R6-NEXT: jrc $ra
entry:
%r = and i128 4, %b
@@ -884,26 +884,26 @@ define signext i128 @and_i128_31(i128 signext %b) {
; MIPS-LABEL: and_i128_31:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $5, $7, 31
-; MIPS-NEXT: addiu $2, $zero, 0
-; MIPS-NEXT: addiu $3, $zero, 0
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $4, $zero, 0
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: move $3, $4
;
; MIPS32R2-LABEL: and_i128_31:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: andi $5, $7, 31
-; MIPS32R2-NEXT: addiu $2, $zero, 0
-; MIPS32R2-NEXT: addiu $3, $zero, 0
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: addiu $4, $zero, 0
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: move $3, $4
;
; MIPS32R6-LABEL: and_i128_31:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: andi $5, $7, 31
-; MIPS32R6-NEXT: addiu $2, $zero, 0
-; MIPS32R6-NEXT: addiu $3, $zero, 0
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: addiu $4, $zero, 0
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: move $3, $4
;
; MIPS64-LABEL: and_i128_31:
; MIPS64: # %bb.0: # %entry
@@ -926,17 +926,17 @@ define signext i128 @and_i128_31(i128 signext %b) {
; MM32R3-LABEL: and_i128_31:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: andi16 $5, $7, 31
-; MM32R3-NEXT: li16 $2, 0
-; MM32R3-NEXT: li16 $3, 0
; MM32R3-NEXT: li16 $4, 0
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: move $3, $4
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i128_31:
; MM32R6: # %bb.0: # %entry
; MM32R6-NEXT: andi16 $5, $7, 31
-; MM32R6-NEXT: li16 $2, 0
-; MM32R6-NEXT: li16 $3, 0
; MM32R6-NEXT: li16 $4, 0
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: move $3, $4
; MM32R6-NEXT: jrc $ra
entry:
%r = and i128 31, %b
@@ -1177,26 +1177,26 @@ define signext i128 @and_i128_255(i128 signext %b) {
; MIPS-LABEL: and_i128_255:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $5, $7, 255
-; MIPS-NEXT: addiu $2, $zero, 0
-; MIPS-NEXT: addiu $3, $zero, 0
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $4, $zero, 0
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: move $3, $4
;
; MIPS32R2-LABEL: and_i128_255:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: andi $5, $7, 255
-; MIPS32R2-NEXT: addiu $2, $zero, 0
-; MIPS32R2-NEXT: addiu $3, $zero, 0
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: addiu $4, $zero, 0
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: move $3, $4
;
; MIPS32R6-LABEL: and_i128_255:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: andi $5, $7, 255
-; MIPS32R6-NEXT: addiu $2, $zero, 0
-; MIPS32R6-NEXT: addiu $3, $zero, 0
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: addiu $4, $zero, 0
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: move $3, $4
;
; MIPS64-LABEL: and_i128_255:
; MIPS64: # %bb.0: # %entry
@@ -1219,17 +1219,17 @@ define signext i128 @and_i128_255(i128 signext %b) {
; MM32R3-LABEL: and_i128_255:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: andi16 $5, $7, 255
-; MM32R3-NEXT: li16 $2, 0
-; MM32R3-NEXT: li16 $3, 0
; MM32R3-NEXT: li16 $4, 0
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: move $3, $4
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i128_255:
; MM32R6: # %bb.0: # %entry
; MM32R6-NEXT: andi16 $5, $7, 255
-; MM32R6-NEXT: li16 $2, 0
-; MM32R6-NEXT: li16 $3, 0
; MM32R6-NEXT: li16 $4, 0
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: move $3, $4
; MM32R6-NEXT: jrc $ra
entry:
%r = and i128 255, %b
@@ -1479,26 +1479,26 @@ define signext i128 @and_i128_32768(i128 signext %b) {
; MIPS-LABEL: and_i128_32768:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $5, $7, 32768
-; MIPS-NEXT: addiu $2, $zero, 0
-; MIPS-NEXT: addiu $3, $zero, 0
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $4, $zero, 0
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: move $3, $4
;
; MIPS32R2-LABEL: and_i128_32768:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: andi $5, $7, 32768
-; MIPS32R2-NEXT: addiu $2, $zero, 0
-; MIPS32R2-NEXT: addiu $3, $zero, 0
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: addiu $4, $zero, 0
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: move $3, $4
;
; MIPS32R6-LABEL: and_i128_32768:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: andi $5, $7, 32768
-; MIPS32R6-NEXT: addiu $2, $zero, 0
-; MIPS32R6-NEXT: addiu $3, $zero, 0
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: addiu $4, $zero, 0
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: move $3, $4
;
; MIPS64-LABEL: and_i128_32768:
; MIPS64: # %bb.0: # %entry
@@ -1521,17 +1521,17 @@ define signext i128 @and_i128_32768(i128 signext %b) {
; MM32R3-LABEL: and_i128_32768:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: andi16 $5, $7, 32768
-; MM32R3-NEXT: li16 $2, 0
-; MM32R3-NEXT: li16 $3, 0
; MM32R3-NEXT: li16 $4, 0
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: move $3, $4
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i128_32768:
; MM32R6: # %bb.0: # %entry
; MM32R6-NEXT: andi16 $5, $7, 32768
-; MM32R6-NEXT: li16 $2, 0
-; MM32R6-NEXT: li16 $3, 0
; MM32R6-NEXT: li16 $4, 0
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: move $3, $4
; MM32R6-NEXT: jrc $ra
entry:
%r = and i128 32768, %b
@@ -1772,26 +1772,26 @@ define signext i128 @and_i128_65(i128 signext %b) {
; MIPS-LABEL: and_i128_65:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $5, $7, 65
-; MIPS-NEXT: addiu $2, $zero, 0
-; MIPS-NEXT: addiu $3, $zero, 0
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $4, $zero, 0
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: move $3, $4
;
; MIPS32R2-LABEL: and_i128_65:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: andi $5, $7, 65
-; MIPS32R2-NEXT: addiu $2, $zero, 0
-; MIPS32R2-NEXT: addiu $3, $zero, 0
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: addiu $4, $zero, 0
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: move $3, $4
;
; MIPS32R6-LABEL: and_i128_65:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: andi $5, $7, 65
-; MIPS32R6-NEXT: addiu $2, $zero, 0
-; MIPS32R6-NEXT: addiu $3, $zero, 0
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: addiu $4, $zero, 0
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: move $3, $4
;
; MIPS64-LABEL: and_i128_65:
; MIPS64: # %bb.0: # %entry
@@ -1813,18 +1813,18 @@ define signext i128 @and_i128_65(i128 signext %b) {
;
; MM32R3-LABEL: and_i128_65:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: li16 $2, 0
-; MM32R3-NEXT: li16 $3, 0
-; MM32R3-NEXT: li16 $4, 0
-; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: andi $5, $7, 65
+; MM32R3-NEXT: li16 $4, 0
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: move $3, $4
+; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i128_65:
; MM32R6: # %bb.0: # %entry
; MM32R6-NEXT: andi $5, $7, 65
-; MM32R6-NEXT: li16 $2, 0
-; MM32R6-NEXT: li16 $3, 0
; MM32R6-NEXT: li16 $4, 0
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: move $3, $4
; MM32R6-NEXT: jrc $ra
entry:
%r = and i128 65, %b
@@ -2065,26 +2065,26 @@ define signext i128 @and_i128_256(i128 signext %b) {
; MIPS-LABEL: and_i128_256:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $5, $7, 256
-; MIPS-NEXT: addiu $2, $zero, 0
-; MIPS-NEXT: addiu $3, $zero, 0
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $4, $zero, 0
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: move $3, $4
;
; MIPS32R2-LABEL: and_i128_256:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: andi $5, $7, 256
-; MIPS32R2-NEXT: addiu $2, $zero, 0
-; MIPS32R2-NEXT: addiu $3, $zero, 0
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: addiu $4, $zero, 0
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: move $3, $4
;
; MIPS32R6-LABEL: and_i128_256:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: andi $5, $7, 256
-; MIPS32R6-NEXT: addiu $2, $zero, 0
-; MIPS32R6-NEXT: addiu $3, $zero, 0
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: addiu $4, $zero, 0
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: move $3, $4
;
; MIPS64-LABEL: and_i128_256:
; MIPS64: # %bb.0: # %entry
@@ -2106,18 +2106,18 @@ define signext i128 @and_i128_256(i128 signext %b) {
;
; MM32R3-LABEL: and_i128_256:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: li16 $2, 0
-; MM32R3-NEXT: li16 $3, 0
-; MM32R3-NEXT: li16 $4, 0
-; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: andi $5, $7, 256
+; MM32R3-NEXT: li16 $4, 0
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: move $3, $4
+; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i128_256:
; MM32R6: # %bb.0: # %entry
; MM32R6-NEXT: andi $5, $7, 256
-; MM32R6-NEXT: li16 $2, 0
-; MM32R6-NEXT: li16 $3, 0
; MM32R6-NEXT: li16 $4, 0
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: move $3, $4
; MM32R6-NEXT: jrc $ra
entry:
%r = and i128 256, %b
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index 04bed7d42bf96..10e4d464a5ae0 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -2938,8 +2938,8 @@ define fp128 @call_structure_without_fp128() nounwind {
; C_CC_FMT-NEXT: .Ltmp51:
; C_CC_FMT-NEXT: jalr $25
; C_CC_FMT-NEXT: nop
-; C_CC_FMT-NEXT: daddiu $2, $zero, 0
; C_CC_FMT-NEXT: daddiu $4, $zero, 0
+; C_CC_FMT-NEXT: move $2, $4
; C_CC_FMT-NEXT: ld $gp, 32($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: daddiu $sp, $sp, 48
@@ -2959,8 +2959,8 @@ define fp128 @call_structure_without_fp128() nounwind {
; CMP_CC_FMT-NEXT: .reloc .Ltmp51, R_MIPS_JALR, bar_structure_without_fp128
; CMP_CC_FMT-NEXT: .Ltmp51:
; CMP_CC_FMT-NEXT: jalrc $25
-; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0
; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT: move $2, $4
; CMP_CC_FMT-NEXT: ld $gp, 32($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 48
@@ -2973,15 +2973,15 @@ entry:
define { fp128 } @bar_structure_fp128() nounwind {
; C_CC_FMT-LABEL: bar_structure_fp128:
; C_CC_FMT: # %bb.0: # %entry
-; C_CC_FMT-NEXT: daddiu $2, $zero, 0
; C_CC_FMT-NEXT: daddiu $4, $zero, 0
+; C_CC_FMT-NEXT: move $2, $4
; C_CC_FMT-NEXT: jr $ra
; C_CC_FMT-NEXT: nop
;
; CMP_CC_FMT-LABEL: bar_structure_fp128:
; CMP_CC_FMT: # %bb.0: # %entry
-; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0
; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT: move $2, $4
; CMP_CC_FMT-NEXT: jrc $ra
entry:
ret { fp128 } zeroinitializer
@@ -3001,8 +3001,8 @@ define fp128 @tail_call_structure_fp128() nounwind {
; C_CC_FMT-NEXT: .Ltmp52:
; C_CC_FMT-NEXT: jalr $25
; C_CC_FMT-NEXT: nop
-; C_CC_FMT-NEXT: daddiu $2, $zero, 0
; C_CC_FMT-NEXT: daddiu $4, $zero, 0
+; C_CC_FMT-NEXT: move $2, $4
; C_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: daddiu $sp, $sp, 16
@@ -3021,8 +3021,8 @@ define fp128 @tail_call_structure_fp128() nounwind {
; CMP_CC_FMT-NEXT: .reloc .Ltmp52, R_MIPS_JALR, bar_structure_fp128
; CMP_CC_FMT-NEXT: .Ltmp52:
; CMP_CC_FMT-NEXT: jalrc $25
-; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0
; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT: move $2, $4
; CMP_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 16
@@ -3035,15 +3035,15 @@ entry:
define fp128 @bar_fp128() nounwind {
; C_CC_FMT-LABEL: bar_fp128:
; C_CC_FMT: # %bb.0: # %entry
-; C_CC_FMT-NEXT: daddiu $2, $zero, 0
; C_CC_FMT-NEXT: daddiu $4, $zero, 0
+; C_CC_FMT-NEXT: move $2, $4
; C_CC_FMT-NEXT: jr $ra
; C_CC_FMT-NEXT: nop
;
; CMP_CC_FMT-LABEL: bar_fp128:
; CMP_CC_FMT: # %bb.0: # %entry
-; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0
; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT: move $2, $4
; CMP_CC_FMT-NEXT: jrc $ra
entry:
ret fp128 zeroinitializer
@@ -3063,8 +3063,8 @@ define fp128 @call_fp128() nounwind {
; C_CC_FMT-NEXT: .Ltmp53:
; C_CC_FMT-NEXT: jalr $25
; C_CC_FMT-NEXT: nop
-; C_CC_FMT-NEXT: daddiu $2, $zero, 0
; C_CC_FMT-NEXT: daddiu $4, $zero, 0
+; C_CC_FMT-NEXT: move $2, $4
; C_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: daddiu $sp, $sp, 16
@@ -3083,8 +3083,8 @@ define fp128 @call_fp128() nounwind {
; CMP_CC_FMT-NEXT: .reloc .Ltmp53, R_MIPS_JALR, bar_fp128
; CMP_CC_FMT-NEXT: .Ltmp53:
; CMP_CC_FMT-NEXT: jalrc $25
-; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0
; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT: move $2, $4
; CMP_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 16
@@ -3108,8 +3108,8 @@ define fp128 @call_structure_fp128() nounwind {
; C_CC_FMT-NEXT: .Ltmp54:
; C_CC_FMT-NEXT: jalr $25
; C_CC_FMT-NEXT: nop
-; C_CC_FMT-NEXT: daddiu $2, $zero, 0
; C_CC_FMT-NEXT: daddiu $4, $zero, 0
+; C_CC_FMT-NEXT: move $2, $4
; C_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; C_CC_FMT-NEXT: daddiu $sp, $sp, 16
@@ -3128,8 +3128,8 @@ define fp128 @call_structure_fp128() nounwind {
; CMP_CC_FMT-NEXT: .reloc .Ltmp54, R_MIPS_JALR, bar_structure_fp128
; CMP_CC_FMT-NEXT: .Ltmp54:
; CMP_CC_FMT-NEXT: jalrc $25
-; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0
; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT: move $2, $4
; CMP_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 16
diff --git a/llvm/test/CodeGen/Mips/readcyclecounter.ll b/llvm/test/CodeGen/Mips/readcyclecounter.ll
index 467dd92884b3d..ff69365d11597 100644
--- a/llvm/test/CodeGen/Mips/readcyclecounter.ll
+++ b/llvm/test/CodeGen/Mips/readcyclecounter.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
;RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 < %s | FileCheck %s --check-prefix=MIPSEL
;RUN: llc -mtriple=mips64el-linux-gnuabi64 -mcpu=mips64r2 < %s | FileCheck %s --check-prefix=MIPS64EL
;RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips2 < %s | FileCheck %s --check-prefix=MIPSEL
@@ -19,12 +20,6 @@ define i64 @test_readcyclecounter() nounwind {
; MIPSEL-NEXT: jr $ra
; MIPSEL-NEXT: addiu $3, $zero, 0
;
-; MIPSEL_NOT_SUPPORTED-LABEL: test_readcyclecounter:
-; MIPSEL_NOT_SUPPORTED: # %bb.0: # %entry
-; MIPSEL_NOT_SUPPORTED-NEXT: addiu $2, $zero, 0
-; MIPSEL_NOT_SUPPORTED-NEXT: jr $ra
-; MIPSEL_NOT_SUPPORTED-NEXT: addiu $3, $zero, 0
-;
; MIPS64EL-LABEL: test_readcyclecounter:
; MIPS64EL: # %bb.0: # %entry
; MIPS64EL-NEXT: .set push
@@ -34,6 +29,12 @@ define i64 @test_readcyclecounter() nounwind {
; MIPS64EL-NEXT: jr $ra
; MIPS64EL-NEXT: nop
;
+; MIPSEL_NOT_SUPPORTED-LABEL: test_readcyclecounter:
+; MIPSEL_NOT_SUPPORTED: # %bb.0: # %entry
+; MIPSEL_NOT_SUPPORTED-NEXT: addiu $2, $zero, 0
+; MIPSEL_NOT_SUPPORTED-NEXT: jr $ra
+; MIPSEL_NOT_SUPPORTED-NEXT: move $3, $2
+;
; MIPS64EL_NOT_SUPPORTED-LABEL: test_readcyclecounter:
; MIPS64EL_NOT_SUPPORTED: # %bb.0: # %entry
; MIPS64EL_NOT_SUPPORTED-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
index c9eb6521c11ba..80ec534c29199 100644
--- a/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target triple = "powerpc-unknown-linux-gnu"
@@ -12,6 +13,17 @@ target triple = "powerpc-unknown-linux-gnu"
; CHECK: li 10, 0
; CHECK: blr
define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
+; CHECK-LABEL: func:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 0
+; CHECK-NEXT: li 5, 0
+; CHECK-NEXT: li 6, 0
+; CHECK-NEXT: li 7, 0
+; CHECK-NEXT: li 8, 0
+; CHECK-NEXT: li 9, 0
+; CHECK-NEXT: li 10, 0
+; CHECK-NEXT: blr
entry:
br i1 false, label %bb36, label %bb484
diff --git a/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
index 380097f2e6d2e..f7eda89285952 100644
--- a/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-unknown-linux-gnu"
@@ -9,6 +10,14 @@ target triple = "powerpc-unknown-linux-gnu"
; CHECK: sth 5
; CHECK: blr
define signext i16 @t(ptr %dct) nounwind {
+; CHECK-LABEL: t:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mr 4, 3
+; CHECK-NEXT: lbz 3, 1(0)
+; CHECK-NEXT: extsb 5, 3
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: sth 5, 0(4)
+; CHECK-NEXT: blr
entry:
load i16, ptr null, align 2 ; <i16>:0 [#uses=2]
lshr i16 %0, 11 ; <i16>:1 [#uses=0]
diff --git a/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
index 966fb52089716..f99eda5b017f9 100644
--- a/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-unknown-linux-gnu"
@@ -7,6 +8,11 @@ target triple = "powerpc-unknown-linux-gnu"
; CHECK: li 4, 0
; CHECK: blr
define hidden i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
+; CHECK-LABEL: __fixunstfdi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 0
+; CHECK-NEXT: blr
entry:
br i1 false, label %bb3, label %bb4
diff --git a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
index a14ef4f93c701..180ff9ed1fd93 100644
--- a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefixes=SEC,SEC32
@@ -126,18 +127,18 @@ entry:
; RELO-NEXT: OFFSET TYPE VALUE
; RELO-NEXT: 00000006 R_POS .dwabrev
; RELO-NEXT: 00000027 R_POS .dwline
-; RELO-NEXT: 00000009 R_POS
-; RELO-NEXT: 0000003a R_POS
+; RELO-NEXT: 00000009 R_POS
+; RELO-NEXT: 0000003a R_POS
; RELO: RELOCATION RECORDS FOR [.dwline]:
; RELO-NEXT: OFFSET TYPE VALUE
-; RELO-NEXT: 00000000 R_POS
+; RELO-NEXT: 00000000 R_POS
; RELO64: RELOCATION RECORDS FOR [.dwinfo]:
; RELO64-NEXT: OFFSET TYPE VALUE
; RELO64-NEXT: 000000000000000e R_POS .dwabrev
; RELO64-NEXT: 000000000000000b R_POS .dwline
-; RELO64-NEXT: 0000000000000041 R_POS
-; RELO64-NEXT: 000000000000004e R_POS
+; RELO64-NEXT: 0000000000000041 R_POS
+; RELO64-NEXT: 000000000000004e R_POS
; RELO64: RELOCATION RECORDS FOR [.dwline]:
; RELO64-NEXT: OFFSET TYPE VALUE
-; RELO64-NEXT: 000000000000000c R_POS
+; RELO64-NEXT: 000000000000000c R_POS
diff --git a/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll b/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll
index 21d880ec47534..368e3896c2595 100644
--- a/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll
+++ b/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Test that the default CPU for the triple powerpc64-unknown-linux-gnu is ppc64.
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -frame-pointer=all -mcpu=ppc | FileCheck %s -check-prefixes=LNX-PPC,LNX-COM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -frame-pointer=all | FileCheck %s -check-prefixes=LNX-PPC64,LNX-COM
@@ -13,6 +14,77 @@
; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s -check-prefixes=AIX64-PWR7,AIX64-COM-NEXT
define i32 @main() {
+; LNX-PPC-LABEL: main:
+; LNX-PPC: # %bb.0: # %entry
+; LNX-PPC-NEXT: lis 0, -1
+; LNX-PPC-NEXT: ori 0, 0, 32704
+; LNX-PPC-NEXT: std 31, -8(1)
+; LNX-PPC-NEXT: stdux 1, 1, 0
+; LNX-PPC-NEXT: .cfi_def_cfa_offset 32832
+; LNX-PPC-NEXT: .cfi_offset r31, -8
+; LNX-PPC-NEXT: mr 31, 1
+; LNX-PPC-NEXT: .cfi_def_cfa_register r31
+; LNX-PPC-NEXT: li 3, 0
+; LNX-PPC-NEXT: stw 3, 60(31)
+; LNX-PPC-NEXT: ld 1, 0(1)
+; LNX-PPC-NEXT: ld 31, -8(1)
+; LNX-PPC-NEXT: blr
+;
+; LNX-PPC64-LABEL: main:
+; LNX-PPC64: # %bb.0: # %entry
+; LNX-PPC64-NEXT: lis 0, -1
+; LNX-PPC64-NEXT: std 31, -8(1)
+; LNX-PPC64-NEXT: ori 0, 0, 32704
+; LNX-PPC64-NEXT: stdux 1, 1, 0
+; LNX-PPC64-NEXT: .cfi_def_cfa_offset 32832
+; LNX-PPC64-NEXT: .cfi_offset r31, -8
+; LNX-PPC64-NEXT: mr 31, 1
+; LNX-PPC64-NEXT: .cfi_def_cfa_register r31
+; LNX-PPC64-NEXT: li 3, 0
+; LNX-PPC64-NEXT: stw 3, 60(31)
+; LNX-PPC64-NEXT: ld 1, 0(1)
+; LNX-PPC64-NEXT: ld 31, -8(1)
+; LNX-PPC64-NEXT: blr
+;
+; AIX-PPC-LABEL: main:
+; AIX-PPC: # %bb.0: # %entry
+; AIX-PPC-NEXT: lis 0, -1
+; AIX-PPC-NEXT: ori 0, 0, 32736
+; AIX-PPC-NEXT: stwux 1, 1, 0
+; AIX-PPC-NEXT: li 3, 0
+; AIX-PPC-NEXT: stw 3, 36(1)
+; AIX-PPC-NEXT: lwz 1, 0(1)
+; AIX-PPC-NEXT: blr
+;
+; AIX-PWR7-LABEL: main:
+; AIX-PWR7: # %bb.0: # %entry
+; AIX-PWR7-NEXT: lis 0, -1
+; AIX-PWR7-NEXT: ori 0, 0, 32736
+; AIX-PWR7-NEXT: stwux 1, 1, 0
+; AIX-PWR7-NEXT: li 3, 0
+; AIX-PWR7-NEXT: stw 3, 36(1)
+; AIX-PWR7-NEXT: lwz 1, 0(1)
+; AIX-PWR7-NEXT: blr
+;
+; AIX64-PPC-LABEL: main:
+; AIX64-PPC: # %bb.0: # %entry
+; AIX64-PPC-NEXT: lis 0, -1
+; AIX64-PPC-NEXT: ori 0, 0, 32720
+; AIX64-PPC-NEXT: stdux 1, 1, 0
+; AIX64-PPC-NEXT: li 3, 0
+; AIX64-PPC-NEXT: stw 3, 52(1)
+; AIX64-PPC-NEXT: ld 1, 0(1)
+; AIX64-PPC-NEXT: blr
+;
+; AIX64-PWR7-LABEL: main:
+; AIX64-PWR7: # %bb.0: # %entry
+; AIX64-PWR7-NEXT: lis 0, -1
+; AIX64-PWR7-NEXT: ori 0, 0, 32720
+; AIX64-PWR7-NEXT: stdux 1, 1, 0
+; AIX64-PWR7-NEXT: li 3, 0
+; AIX64-PWR7-NEXT: stw 3, 52(1)
+; AIX64-PWR7-NEXT: ld 1, 0(1)
+; AIX64-PWR7-NEXT: blr
entry:
%retval = alloca i32, i32 8191, align 4
store i32 0, ptr %retval, align 4
@@ -65,3 +137,7 @@ entry:
; AIX64-PWR7-NEXT: stw 3, 52(1)
; AIX64-COM-NEXT: ld 1, 0(1)
; AIX64-COM-NEXT: blr
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AIX-COM: {{.*}}
+; AIX64-COM-NEXT: {{.*}}
+; LNX-COM: {{.*}}
diff --git a/llvm/test/CodeGen/PowerPC/register-pressure.ll b/llvm/test/CodeGen/PowerPC/register-pressure.ll
index 40ee849c6c2b3..7d8eac30aee8b 100644
--- a/llvm/test/CodeGen/PowerPC/register-pressure.ll
+++ b/llvm/test/CodeGen/PowerPC/register-pressure.ll
@@ -12,41 +12,44 @@ define dso_local i32 @main() #0 {
; CHECK-LABEL: main:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
-; CHECK-NEXT: stwu 1, -48(1)
-; CHECK-NEXT: stw 31, 44(1)
-; CHECK-NEXT: stw 0, 52(1)
-; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: stwu 1, -64(1)
+; CHECK-NEXT: stw 31, 60(1)
+; CHECK-NEXT: stw 0, 68(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset r31, -4
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: mr 31, 1
; CHECK-NEXT: .cfi_def_cfa_register r31
+; CHECK-NEXT: .cfi_offset r30, -8
+; CHECK-NEXT: stw 30, 56(31) # 4-byte Folded Spill
; CHECK-NEXT: li 3, 10
-; CHECK-NEXT: stw 3, 40(31)
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: stw 3, 28(31)
-; CHECK-NEXT: lis 4, 16404
-; CHECK-NEXT: stw 4, 24(31)
-; CHECK-NEXT: stw 3, 36(31)
-; CHECK-NEXT: lis 3, 16420
+; CHECK-NEXT: stw 3, 52(31)
+; CHECK-NEXT: li 30, 0
+; CHECK-NEXT: stw 30, 36(31)
+; CHECK-NEXT: lis 3, 16404
; CHECK-NEXT: stw 3, 32(31)
-; CHECK-NEXT: lwz 3, 40(31)
+; CHECK-NEXT: stw 30, 44(31)
+; CHECK-NEXT: lis 3, 16420
+; CHECK-NEXT: stw 3, 40(31)
+; CHECK-NEXT: lwz 3, 52(31)
; CHECK-NEXT: slwi 3, 3, 4
; CHECK-NEXT: bl malloc
+; CHECK-NEXT: stw 3, 28(31)
+; CHECK-NEXT: addi 7, 31, 32
+; CHECK-NEXT: stw 7, 24(31)
+; CHECK-NEXT: lwz 3, 28(31)
; CHECK-NEXT: stw 3, 20(31)
-; CHECK-NEXT: addi 7, 31, 24
-; CHECK-NEXT: stw 7, 16(31)
-; CHECK-NEXT: lwz 3, 20(31)
-; CHECK-NEXT: stw 3, 12(31)
-; CHECK-NEXT: lwz 5, 16(31)
-; CHECK-NEXT: lwz 6, 12(31)
+; CHECK-NEXT: lwz 5, 24(31)
+; CHECK-NEXT: lwz 6, 20(31)
; CHECK-NEXT: li 3, 5
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: li 8, 1
; CHECK-NEXT: bl pass11
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: lwz 0, 52(1)
-; CHECK-NEXT: lwz 31, 44(1)
-; CHECK-NEXT: addi 1, 1, 48
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: lwz 30, 56(31) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 0, 68(1)
+; CHECK-NEXT: lwz 31, 60(1)
+; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%1 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index a95f68b5e118d..1a83305c096da 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple s390x-ibm-zos | FileCheck %s
; Source to regenerate:
; struct Foo {
@@ -103,9 +104,6 @@ declare void @use_foo(ptr)
define void @ptr32_to_ptr(ptr %f, ptr addrspace(1) %i) {
entry:
-; CHECK-LABEL: ptr32_to_ptr:
-; CHECK: llgtr 0,2
-; CHECK-NEXT: stg 0,8(1)
%0 = addrspacecast ptr addrspace(1) %i to ptr
%p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
store ptr %0, ptr %p64, align 8
@@ -115,9 +113,6 @@ entry:
define void @ptr_to_ptr32(ptr %f, ptr %i) {
entry:
-; CHECK-LABEL: ptr_to_ptr32:
-; CHECK: nilh 2,32767
-; CHECK-NEXT: st 2,0(1)
%0 = addrspacecast ptr %i to ptr addrspace(1)
%p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
store ptr addrspace(1) %0, ptr %p32, align 8
@@ -127,8 +122,6 @@ entry:
define void @ptr32_to_ptr32(ptr %f, ptr addrspace(1) %i) {
entry:
-; CHECK-LABEL: ptr32_to_ptr32:
-; CHECK: st 2,0(1)
%p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
store ptr addrspace(1) %i, ptr %p32, align 8
tail call void @use_foo(ptr %f)
@@ -136,8 +129,6 @@ entry:
}
define void @ptr_to_ptr(ptr %f, ptr %i) {
-; CHECK-LABEL: ptr_to_ptr:
-; CHECK: stg 2,8(1)
%p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
store ptr %i, ptr %p64, align 8
tail call void @use_foo(ptr %f)
@@ -146,10 +137,6 @@ define void @ptr_to_ptr(ptr %f, ptr %i) {
define void @test_indexing(ptr %f) {
entry:
-; CHECK-LABEL: test_indexing:
-; CHECK: l 0,1032
-; CHECK: llgtr 0,0
-; CHECK: stg 0,16(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1032 to ptr), align 8
%1 = addrspacecast ptr addrspace(1) %0 to ptr
%cp64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 2
@@ -160,12 +147,6 @@ entry:
define void @test_indexing_2(ptr %f) {
entry:
-; CHECK-LABEL: test_indexing_2:
-; CHECK: lhi 0,16
-; CHECK-NEXT: a 0,1032
-; CHECK-NEXT: llgtr 2,0
-; CHECK: lg 0,24(2)
-; CHECK: stg 0,16(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1032 to ptr), align 8
%arrayidx = getelementptr inbounds ptr, ptr addrspace(1) %0, i32 2
%1 = load ptr, ptr addrspace(1) %arrayidx, align 8
@@ -181,14 +162,6 @@ entry:
define ptr @test_misc() {
entry:
-; CHECK-LABEL: test_misc:
-; CHECK: lhi 0,88
-; CHECK-NEXT: a 0,1208
-; CHECK-NEXT: llgtr 1,0
-; CHECK-NEXT: lg 1,0(1)
-; CHECK-NEXT: lg 1,8(1)
-; CHECK-NEXT: lg 1,904(1)
-; CHECK-NEXT: lg 3,1192(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1208 to ptr), align 8
%arrayidx = getelementptr inbounds ptr, ptr addrspace(1) %0, i32 11
%1 = load ptr, ptr addrspace(1) %arrayidx, align 8
@@ -204,13 +177,6 @@ entry:
define ptr addrspace(1) @test_misc_2() {
entry:
-; CHECK-LABEL: test_misc_2:
-; CHECK: lhi 0,544
-; CHECK: a 0,16
-; CHECK: llgtr 1,0
-; CHECK: lhi 0,24
-; CHECK: a 0,0(1)
-; CHECK: llgtr 1,0
%0 = load ptr addrspace(1), ptr inttoptr (i64 16 to ptr), align 16
%arrayidx = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) %0, i32 136
%1 = load ptr addrspace(1), ptr addrspace(1) %arrayidx, align 4
@@ -221,11 +187,6 @@ entry:
define zeroext i16 @test_misc_3() {
entry:
-; CHECK-LABEL: test_misc_3:
-; CHECK: a 0,548
-; CHECK-NEXT: llgtr 1,0
-; CHECK-NEXT: llgh 3,0(1)
-; CHECK-NEXT: b 2(7)
%0 = load ptr addrspace(1), ptr inttoptr (i64 548 to ptr), align 4
%arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %0, i32 18
%arrayidx = addrspacecast ptr addrspace(1) %arrayidx2 to ptr
@@ -235,15 +196,6 @@ entry:
define signext i32 @test_misc_4() {
entry:
-; CHECK-LABEL: test_misc_4:
-; CHECK: lhi 0,88
-; CHECK-NEXT: a 0,1208
-; CHECK-NEXT: llgtr 1,0
-; CHECK-NEXT: lg 1,0(1)
-; CHECK-NEXT: lg 1,8(1)
-; CHECK-NEXT: lg 1,984(1)
-; CHECK-NEXT: iilf 0,67240703
-; CHECK-NEXT: c 0,80(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1208 to ptr), align 8
%arrayidx = getelementptr inbounds ptr, ptr addrspace(1) %0, i32 11
%1 = load ptr, ptr addrspace(1) %arrayidx, align 8
@@ -261,12 +213,6 @@ entry:
define void @test_misc_5(ptr %f) {
entry:
-; CHECK-LABEL: test_misc_5:
-; CHECK: l 0,548
-; CHECK-NEXT: lg 6,8(5)
-; CHECK-NEXT: lg 5,0(5)
-; CHECK-NEXT: llgtr 0,0
-; CHECK-NEXT: stg 0,16(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 548 to ptr), align 4
%1 = addrspacecast ptr addrspace(1) %0 to ptr
%cp64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 2
@@ -277,14 +223,6 @@ entry:
define signext i32 @get_processor_count() {
entry:
-; CHECK-LABEL: get_processor_count:
-; CHECK: lhi 0,660
-; CHECK-NEXT: a 0,16
-; CHECK-NEXT: llgtr 1,0
-; CHECK-NEXT: lhi 0,53
-; CHECK-NEXT: a 0,0(1)
-; CHECK-NEXT: llgtr 1,0
-; CHECK-NEXT: lgb 3,0(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 16 to ptr), align 16
%arrayidx = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) %0, i32 165
%1 = load ptr addrspace(1), ptr addrspace(1) %arrayidx, align 4
@@ -296,22 +234,6 @@ entry:
define void @spill_ptr32_args_to_registers(i8 addrspace(1)* %p) {
entry:
-; CHECK-LABEL: spill_ptr32_args_to_registers:
-; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: aghi 4,-192
-; CHECK-NEXT: lgr 2,1
-; CHECK-NEXT: lg 6,24(5)
-; CHECK-NEXT: lg 5,16(5)
-; CHECK-NEXT: stg 1,2216(4)
-; CHECK-NEXT: stg 1,2208(4)
-; CHECK-NEXT: lghi 1,5
-; CHECK-NEXT: stg 2,2200(4)
-; CHECK-NEXT: lgr 3,2
-; CHECK-NEXT: basr 7,6
-; CHECK-NEXT: bcr 0,0
-; CHECK-NEXT: lg 7,2072(4)
-; CHECK-NEXT: aghi 4,192
-; CHECK-NEXT: b 2(7)
tail call void (i32, ...) @g(i32 noundef signext 5, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p)
ret void
}
@@ -327,14 +249,6 @@ declare void @g(i32 signext, ...)
; cast to __ptr32, setting the upper 32 bit to zero.
;
define signext i32 @setlength() {
-; CHECK-LABEL: setlength:
-; CHECK: basr 7,6
-; CHECK: lgr [[MALLOC:[0-9]+]],3
-; CHECK: basr 7,6
-; CHECK: lgr [[LENGTH:[0-9]+]],3
-; CHECK: la [[ADDR:[0-9]+]],4([[MALLOC]])
-; CHECK: llgtr [[ADDR]],[[ADDR]]
-; CHECK: stg [[LENGTH]],0([[ADDR]])
entry:
%call = tail call ptr @__malloc31(i64 noundef 8)
%call1 = tail call signext i32 @foo()
@@ -351,14 +265,6 @@ entry:
; the function now returns a __ptr32.
;
define signext i32 @setlength2() {
-; CHECK-LABEL: setlength2:
-; CHECK: basr 7,6
-; CHECK: lgr [[MALLOC:[0-9]+]],3
-; CHECK: basr 7,6
-; CHECK: lgr [[LENGTH:[0-9]+]],3
-; CHECK: ahi [[MALLOC]],4
-; CHECK: llgtr [[ADDR]],[[MALLOC]]
-; CHECK: stg [[LENGTH]],0([[ADDR]])
entry:
%call = tail call ptr addrspace(1) @domalloc(i64 noundef 8)
%call1 = tail call signext i32 @foo()
@@ -373,3 +279,5 @@ declare ptr @__malloc31(i64)
declare signext i32 @foo(...)
declare ptr addrspace(1) @domalloc(i64)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll b/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
index bef7603c53b55..e6f28c2057f77 100644
--- a/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
+++ b/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
@@ -29,7 +29,6 @@ define i1 @loadAndRLEsource_no_exit_2E_1_label_2E_0(i32 %tmp.21.reload, i32 %tmp
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_2: ## %codeRepl5.exitStub
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
newFuncRoot:
diff --git a/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll b/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll
index 8cc4dfcbd528b..206574eeae2ae 100644
--- a/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll
+++ b/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll
@@ -90,7 +90,6 @@ define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(ptr %l_addr.01.0.i2.i.i929, ptr %tm
; CHECK-NEXT: LBB0_3: ## %NewDefault
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
index 1a9f6dba64267..cfb3e508576dd 100644
--- a/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -21,7 +21,6 @@ define signext i16 @f(ptr %bp, ptr %ss) {
; CHECK-NEXT: jb .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
index 53ea8c0576c50..6ebb97d63e7c6 100644
--- a/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
+++ b/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
@@ -16,7 +16,6 @@ define signext i16 @t(ptr %qmatrix, ptr %dct, ptr %acBaseTable, ptr %acExtTabl
; CHECK-NEXT: jb .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
entry:
br label %cond_next127
diff --git a/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
index 8704a676954bb..503afa8803a43 100644
--- a/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
+++ b/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
@@ -7,7 +7,6 @@ define signext i16 @t() {
; CHECK-NEXT: movswl 0, %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
entry:
%tmp180 = load i16, ptr null, align 2 ; <i16> [#uses=3]
diff --git a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
index 31395ca16e6ac..b32afdc2214e0 100644
--- a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -83,7 +83,6 @@ define i16 @SQLDriversW(ptr %henv, i16 zeroext %fDir, ptr %szDrvDesc, i16 signe
; CHECK-NEXT: addl $48, %esp
; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: LBB0_2: ## %bb
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll
index fdd743843b8e5..079294ef09bdb 100644
--- a/llvm/test/CodeGen/X86/add.ll
+++ b/llvm/test/CodeGen/X86/add.ll
@@ -136,7 +136,6 @@ define i1 @test4(i32 %v1, i32 %v2, ptr %X) nounwind {
; X86-NEXT: movl $0, (%eax)
; X86-NEXT: .LBB5_2: # %overflow
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LINUX-LABEL: test4:
@@ -147,7 +146,6 @@ define i1 @test4(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-LINUX-NEXT: movl $0, (%rdx)
; X64-LINUX-NEXT: .LBB5_2: # %overflow
; X64-LINUX-NEXT: xorl %eax, %eax
-; X64-LINUX-NEXT: # kill: def $al killed $al killed $eax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test4:
@@ -158,7 +156,6 @@ define i1 @test4(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-WIN32-NEXT: movl $0, (%r8)
; X64-WIN32-NEXT: .LBB5_2: # %overflow
; X64-WIN32-NEXT: xorl %eax, %eax
-; X64-WIN32-NEXT: # kill: def $al killed $al killed $eax
; X64-WIN32-NEXT: retq
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -185,7 +182,6 @@ define i1 @test5(i32 %v1, i32 %v2, ptr %X) nounwind {
; X86-NEXT: movl $0, (%eax)
; X86-NEXT: .LBB6_2: # %carry
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LINUX-LABEL: test5:
@@ -196,7 +192,6 @@ define i1 @test5(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-LINUX-NEXT: movl $0, (%rdx)
; X64-LINUX-NEXT: .LBB6_2: # %carry
; X64-LINUX-NEXT: xorl %eax, %eax
-; X64-LINUX-NEXT: # kill: def $al killed $al killed $eax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test5:
@@ -207,7 +202,6 @@ define i1 @test5(i32 %v1, i32 %v2, ptr %X) nounwind {
; X64-WIN32-NEXT: movl $0, (%r8)
; X64-WIN32-NEXT: .LBB6_2: # %carry
; X64-WIN32-NEXT: xorl %eax, %eax
-; X64-WIN32-NEXT: # kill: def $al killed $al killed $eax
; X64-WIN32-NEXT: retq
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll
index 1f3ab806329e8..97894db1188e2 100644
--- a/llvm/test/CodeGen/X86/addcarry.ll
+++ b/llvm/test/CodeGen/X86/addcarry.ll
@@ -607,9 +607,8 @@ define { i64, i64, i1 } @addcarry_2x64_and_reversed(i64 %x0, i64 %x1, i64 %y0, i
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
-; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movq %rsi, %rdx
-; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index b18a2d7418158..4c58c8a980314 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -97,7 +97,6 @@ define i8 @ccmp8rr_sf(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8rr_sf:
@@ -110,7 +109,6 @@ define i8 @ccmp8rr_sf(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
@@ -137,7 +135,6 @@ define i8 @ccmp8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8rr_none:
@@ -150,7 +147,6 @@ define i8 @ccmp8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
@@ -384,7 +380,6 @@ define i8 @ccmp8ri_zf_double(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8ri_zf_double:
@@ -398,7 +393,6 @@ define i8 @ccmp8ri_zf_double(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; NDD-NEXT: .LBB9_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
@@ -429,7 +423,6 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8ri_zf_double_p:
@@ -446,7 +439,6 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; NDD-NEXT: .LBB10_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
@@ -477,7 +469,6 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; CHECK-NEXT: .LBB11_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NDD-LABEL: ccmp8ri_zf_double_np:
@@ -494,7 +485,6 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
; NDD-NEXT: .LBB11_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
diff --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll
index e431736e83b73..5f3ec8a19d0a4 100644
--- a/llvm/test/CodeGen/X86/apx/ctest.ll
+++ b/llvm/test/CodeGen/X86/apx/ctest.ll
@@ -49,7 +49,6 @@ define i8 @ctest8rr_zf_double(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi)
; CHECK-NEXT: .LBB1_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_zf_double:
@@ -62,7 +61,6 @@ define i8 @ctest8rr_zf_double(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi)
; NDD-NEXT: .LBB1_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
@@ -92,7 +90,6 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi)
; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_zf_double_p:
@@ -108,7 +105,6 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi)
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
@@ -138,7 +134,6 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rsi)
; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_zf_double_np:
@@ -154,7 +149,6 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rsi)
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
@@ -216,7 +210,6 @@ define i8 @ctest8rr_sf_2(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx)
; CHECK-NEXT: .LBB5_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_sf_2:
@@ -228,7 +221,6 @@ define i8 @ctest8rr_sf_2(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx)
; NDD-NEXT: .LBB5_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp sgt i8 %a, 0
@@ -254,7 +246,6 @@ define i8 @ctest8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; CHECK-NEXT: movb %dil, (%rdx)
; CHECK-NEXT: .LBB6_2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
;
; NDD-LABEL: ctest8rr_none:
@@ -266,7 +257,6 @@ define i8 @ctest8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: movb %dil, (%rdx)
; NDD-NEXT: .LBB6_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
-; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
entry:
%tobool = icmp ne i8 %a, 0
diff --git a/llvm/test/CodeGen/X86/apx/imulzu.ll b/llvm/test/CodeGen/X86/apx/imulzu.ll
index e8e6efa0357b5..9a4a63750a1db 100644
--- a/llvm/test/CodeGen/X86/apx/imulzu.ll
+++ b/llvm/test/CodeGen/X86/apx/imulzu.ll
@@ -208,7 +208,6 @@ define i16 @mul0_16(i16 %A) {
; CHECK-LABEL: mul0_16:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%mul = mul i16 %A, 0
ret i16 %mul
diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll
index 133dbca10a396..e8e0ee0b7ef49 100644
--- a/llvm/test/CodeGen/X86/atomic-unordered.ll
+++ b/llvm/test/CodeGen/X86/atomic-unordered.ll
@@ -2318,19 +2318,32 @@ define i16 @load_combine(ptr %p) {
}
define i1 @fold_cmp_over_fence(ptr %p, i32 %v1) {
-; CHECK-LABEL: fold_cmp_over_fence:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl (%rdi), %eax
-; CHECK-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: cmpl %eax, %esi
-; CHECK-NEXT: jne .LBB116_2
-; CHECK-NEXT: # %bb.1: # %taken
-; CHECK-NEXT: movb $1, %al
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB116_2: # %untaken
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
+; CHECK-O0-LABEL: fold_cmp_over_fence:
+; CHECK-O0: # %bb.0:
+; CHECK-O0-NEXT: movl (%rdi), %eax
+; CHECK-O0-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
+; CHECK-O0-NEXT: cmpl %eax, %esi
+; CHECK-O0-NEXT: jne .LBB116_2
+; CHECK-O0-NEXT: # %bb.1: # %taken
+; CHECK-O0-NEXT: movb $1, %al
+; CHECK-O0-NEXT: retq
+; CHECK-O0-NEXT: .LBB116_2: # %untaken
+; CHECK-O0-NEXT: xorl %eax, %eax
+; CHECK-O0-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-O0-NEXT: retq
+;
+; CHECK-O3-LABEL: fold_cmp_over_fence:
+; CHECK-O3: # %bb.0:
+; CHECK-O3-NEXT: movl (%rdi), %eax
+; CHECK-O3-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
+; CHECK-O3-NEXT: cmpl %eax, %esi
+; CHECK-O3-NEXT: jne .LBB116_2
+; CHECK-O3-NEXT: # %bb.1: # %taken
+; CHECK-O3-NEXT: movb $1, %al
+; CHECK-O3-NEXT: retq
+; CHECK-O3-NEXT: .LBB116_2: # %untaken
+; CHECK-O3-NEXT: xorl %eax, %eax
+; CHECK-O3-NEXT: retq
%v2 = load atomic i32, ptr %p unordered, align 4
fence seq_cst
%cmp = icmp eq i32 %v1, %v2
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 392263dc8c49d..ed3f0e0f0aa71 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -66,7 +66,6 @@ define i8 @test2b(i8 %X, ptr %y) nounwind {
; CHECK-NEXT: retq # encoding: [0xc3]
; CHECK-NEXT: .LBB2_2: # %ReturnBlock
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i8, ptr %y
diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
index f07a2a9819d0d..66ba54f3e318e 100644
--- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
+++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
@@ -21,19 +21,19 @@ define i1 @_ZN4llvm8LLParser17parseDIEnumeratorERPNS_6MDNodeEb(i32 %arg) {
; CHECK-NEXT: .LBB0_4: # %if.then.i.i
; CHECK-NEXT: movb $1, %dl
; CHECK-NEXT: testb %dl, %dl
-; CHECK-NEXT: je .LBB0_7
-; CHECK-NEXT: .LBB0_6: # %do.end
+; CHECK-NEXT: je .LBB0_6
+; CHECK-NEXT: .LBB0_7: # %do.end
; CHECK-NEXT: movq %rcx, 0
; CHECK-NEXT: movb %al, 0
-; CHECK-NEXT: .LBB0_7: # %if.then8
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: testb %dl, %dl
-; CHECK-NEXT: jne .LBB0_6
-; CHECK-NEXT: jmp .LBB0_7
+; CHECK-NEXT: jne .LBB0_7
+; CHECK-NEXT: .LBB0_6: # %if.then8
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
entry:
switch i32 %arg, label %if.then.i.i [
i32 1, label %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
diff --git a/llvm/test/CodeGen/X86/combine-mulo.ll b/llvm/test/CodeGen/X86/combine-mulo.ll
index 0c722e09888ac..896269a288f56 100644
--- a/llvm/test/CodeGen/X86/combine-mulo.ll
+++ b/llvm/test/CodeGen/X86/combine-mulo.ll
@@ -97,7 +97,6 @@ define { i32, i1 } @combine_smul_nsw(i32 %a, i32 %b) {
; CHECK-NEXT: andl $524287, %eax # imm = 0x7FFFF
; CHECK-NEXT: imull %edi, %eax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%aa = and i32 %a, 4095 ; 0xfff
%bb = and i32 %b, 524287; 0x7ffff
diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll
index 20a6522654e97..4b01c16a6324e 100644
--- a/llvm/test/CodeGen/X86/combine-srem.ll
+++ b/llvm/test/CodeGen/X86/combine-srem.ll
@@ -429,7 +429,6 @@ define i1 @bool_srem(i1 %x, i1 %y) {
; CHECK-LABEL: bool_srem:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%r = srem i1 %x, %y
ret i1 %r
diff --git a/llvm/test/CodeGen/X86/combine-subo.ll b/llvm/test/CodeGen/X86/combine-subo.ll
index 57aa323ee1a76..68ba746584d76 100644
--- a/llvm/test/CodeGen/X86/combine-subo.ll
+++ b/llvm/test/CodeGen/X86/combine-subo.ll
@@ -162,7 +162,6 @@ define { i32, i1 } @combine_usub_nuw(i32 %a, i32 %b) {
; CHECK-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
; CHECK-NEXT: subl %esi, %eax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%aa = or i32 %a, 2147483648
%bb = and i32 %b, 2147483647
diff --git a/llvm/test/CodeGen/X86/combine-urem.ll b/llvm/test/CodeGen/X86/combine-urem.ll
index ca49ed6c71532..715d5c7b28f11 100644
--- a/llvm/test/CodeGen/X86/combine-urem.ll
+++ b/llvm/test/CodeGen/X86/combine-urem.ll
@@ -488,7 +488,6 @@ define i1 @bool_urem(i1 %x, i1 %y) {
; CHECK-LABEL: bool_urem:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%r = urem i1 %x, %y
ret i1 %r
diff --git a/llvm/test/CodeGen/X86/divmod128.ll b/llvm/test/CodeGen/X86/divmod128.ll
index 3d24ffc1bca3c..3796dd796eaf9 100644
--- a/llvm/test/CodeGen/X86/divmod128.ll
+++ b/llvm/test/CodeGen/X86/divmod128.ll
@@ -141,8 +141,8 @@ define i128 @urem_i128_3(i128 %x) nounwind {
; X86-64-NEXT: shrq %rdx
; X86-64-NEXT: leaq (%rdx,%rdx,2), %rax
; X86-64-NEXT: subq %rax, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_3:
@@ -155,8 +155,8 @@ define i128 @urem_i128_3(i128 %x) nounwind {
; WIN64-NEXT: shrq %rdx
; WIN64-NEXT: leaq (%rdx,%rdx,2), %rax
; WIN64-NEXT: subq %rax, %rcx
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %rcx, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 3
@@ -174,8 +174,8 @@ define i128 @urem_i128_5(i128 %x) nounwind {
; X86-64-NEXT: shrq $2, %rdx
; X86-64-NEXT: leaq (%rdx,%rdx,4), %rax
; X86-64-NEXT: subq %rax, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_5:
@@ -188,8 +188,8 @@ define i128 @urem_i128_5(i128 %x) nounwind {
; WIN64-NEXT: shrq $2, %rdx
; WIN64-NEXT: leaq (%rdx,%rdx,4), %rax
; WIN64-NEXT: subq %rax, %rcx
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %rcx, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 5
@@ -208,8 +208,8 @@ define i128 @urem_i128_15(i128 %x) nounwind {
; X86-64-NEXT: leaq (%rdx,%rdx,4), %rax
; X86-64-NEXT: leaq (%rax,%rax,2), %rax
; X86-64-NEXT: subq %rax, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_15:
@@ -223,8 +223,8 @@ define i128 @urem_i128_15(i128 %x) nounwind {
; WIN64-NEXT: leaq (%rdx,%rdx,4), %rax
; WIN64-NEXT: leaq (%rax,%rax,2), %rax
; WIN64-NEXT: subq %rax, %rcx
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %rcx, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 15
@@ -244,8 +244,8 @@ define i128 @urem_i128_17(i128 %x) nounwind {
; X86-64-NEXT: shrq $4, %rdx
; X86-64-NEXT: addq %rax, %rdx
; X86-64-NEXT: subq %rdx, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_17:
@@ -260,8 +260,8 @@ define i128 @urem_i128_17(i128 %x) nounwind {
; WIN64-NEXT: shrq $4, %rdx
; WIN64-NEXT: addq %rax, %rdx
; WIN64-NEXT: subq %rdx, %rcx
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %rcx, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 17
@@ -282,8 +282,8 @@ define i128 @urem_i128_255(i128 %x) nounwind {
; X86-64-NEXT: subq %rax, %rdx
; X86-64-NEXT: addq %rsi, %rdi
; X86-64-NEXT: adcq %rdx, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_255:
@@ -300,8 +300,8 @@ define i128 @urem_i128_255(i128 %x) nounwind {
; WIN64-NEXT: subq %rax, %rdx
; WIN64-NEXT: addq %rcx, %r8
; WIN64-NEXT: adcq %rdx, %r8
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %r8, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 255
@@ -321,8 +321,8 @@ define i128 @urem_i128_257(i128 %x) nounwind {
; X86-64-NEXT: shrq $8, %rdx
; X86-64-NEXT: addq %rax, %rdx
; X86-64-NEXT: subq %rdx, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_257:
@@ -337,8 +337,8 @@ define i128 @urem_i128_257(i128 %x) nounwind {
; WIN64-NEXT: shrq $8, %rdx
; WIN64-NEXT: addq %rax, %rdx
; WIN64-NEXT: subq %rdx, %rcx
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %rcx, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 257
@@ -359,8 +359,8 @@ define i128 @urem_i128_65535(i128 %x) nounwind {
; X86-64-NEXT: subq %rax, %rdx
; X86-64-NEXT: addq %rsi, %rdi
; X86-64-NEXT: adcq %rdx, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_65535:
@@ -377,8 +377,8 @@ define i128 @urem_i128_65535(i128 %x) nounwind {
; WIN64-NEXT: subq %rax, %rdx
; WIN64-NEXT: addq %rcx, %r8
; WIN64-NEXT: adcq %rdx, %r8
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %r8, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 65535
@@ -398,8 +398,8 @@ define i128 @urem_i128_65537(i128 %x) nounwind {
; X86-64-NEXT: shrq $16, %rdx
; X86-64-NEXT: addq %rax, %rdx
; X86-64-NEXT: subq %rdx, %rdi
-; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: movq %rdi, %rax
+; X86-64-NEXT: xorl %edx, %edx
; X86-64-NEXT: retq
;
; WIN64-LABEL: urem_i128_65537:
@@ -414,8 +414,8 @@ define i128 @urem_i128_65537(i128 %x) nounwind {
; WIN64-NEXT: shrq $16, %rdx
; WIN64-NEXT: addq %rax, %rdx
; WIN64-NEXT: subq %rdx, %rcx
-; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: movq %rcx, %rax
+; WIN64-NEXT: xorl %edx, %edx
; WIN64-NEXT: retq
entry:
%rem = urem i128 %x, 65537
diff --git a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
index 19bf6c3b61e9c..b9ef3154cd1c3 100644
--- a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
@@ -584,7 +584,6 @@ define zeroext i1 @fcmp_ogt2(float %x) {
; SDAG-LABEL: fcmp_ogt2:
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: fcmp_ogt2:
@@ -679,7 +678,6 @@ define zeroext i1 @fcmp_olt2(float %x) {
; SDAG-LABEL: fcmp_olt2:
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: fcmp_olt2:
@@ -774,7 +772,6 @@ define zeroext i1 @fcmp_one2(float %x) {
; SDAG-LABEL: fcmp_one2:
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: fcmp_one2:
diff --git a/llvm/test/CodeGen/X86/fast-isel-load-i1.ll b/llvm/test/CodeGen/X86/fast-isel-load-i1.ll
index e48558f3f4c2d..34ce8810251e0 100644
--- a/llvm/test/CodeGen/X86/fast-isel-load-i1.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-load-i1.ll
@@ -8,7 +8,6 @@ define i1 @test_i1(ptr %b) {
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %in
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_2: # %out
; CHECK-NEXT: movb $1, %al
diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index c509e05165b25..9121cf2d654a3 100644
--- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -849,7 +849,6 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: ret{{[l|q]}}
%t0 = lshr i8 24, %y
%t1 = and i8 %t0, %x
diff --git a/llvm/test/CodeGen/X86/i128-immediate.ll b/llvm/test/CodeGen/X86/i128-immediate.ll
index 738448299e761..96c05a3a32128 100644
--- a/llvm/test/CodeGen/X86/i128-immediate.ll
+++ b/llvm/test/CodeGen/X86/i128-immediate.ll
@@ -5,7 +5,7 @@ define i128 @__addvti3() {
; CHECK-LABEL: __addvti3:
; CHECK: # %bb.0:
; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: movq %rax, %rdx
+; CHECK-NEXT: movq $-1, %rdx
; CHECK-NEXT: retq
ret i128 -1
}
diff --git a/llvm/test/CodeGen/X86/int-to-fp-demanded.ll b/llvm/test/CodeGen/X86/int-to-fp-demanded.ll
index baf6e2982fdac..cdde03fb0534b 100644
--- a/llvm/test/CodeGen/X86/int-to-fp-demanded.ll
+++ b/llvm/test/CodeGen/X86/int-to-fp-demanded.ll
@@ -261,9 +261,8 @@ define <2 x i16> @uitofp_signbit_only_fail_bad_width2(i32 %i_in) nounwind {
; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: movl $32768, %eax # imm = 0x8000
; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: xorl %edx, %edx
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: # kill: def $dx killed $dx killed $edx
+; X86-NEXT: xorl %edx, %edx
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index f20dd90d9b7ff..97136dafa6c2c 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -1636,13 +1636,11 @@ define i1 @isnone_f(float %x) {
; X86-LABEL: isnone_f:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LABEL: isnone_f:
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
diff --git a/llvm/test/CodeGen/X86/isel-fpclass.ll b/llvm/test/CodeGen/X86/isel-fpclass.ll
index e16a6d650060d..df04b673d8223 100644
--- a/llvm/test/CodeGen/X86/isel-fpclass.ll
+++ b/llvm/test/CodeGen/X86/isel-fpclass.ll
@@ -10,13 +10,11 @@ define i1 @isnone_f(float %x) nounwind {
; X86-LABEL: isnone_f:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LABEL: isnone_f:
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-FASTISEL-LABEL: isnone_f:
@@ -24,7 +22,6 @@ define i1 @isnone_f(float %x) nounwind {
; X86-FASTISEL-NEXT: flds {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstp %st(0)
; X86-FASTISEL-NEXT: xorl %eax, %eax
-; X86-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X86-FASTISEL-NEXT: retl
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
@@ -408,13 +405,11 @@ define i1 @isnone_d(double %x) nounwind {
; X86-LABEL: isnone_d:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-LABEL: isnone_d:
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-FASTISEL-LABEL: isnone_d:
@@ -422,7 +417,6 @@ define i1 @isnone_d(double %x) nounwind {
; X86-FASTISEL-NEXT: fldl {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstp %st(0)
; X86-FASTISEL-NEXT: xorl %eax, %eax
-; X86-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X86-FASTISEL-NEXT: retl
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 0)
@@ -455,13 +449,11 @@ define i1 @isnone_f80(x86_fp80 %x) nounwind {
; X86-LABEL: isnone_f80:
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
;
; X64-SDAGISEL-LABEL: isnone_f80:
; X64-SDAGISEL: # %bb.0: # %entry
; X64-SDAGISEL-NEXT: xorl %eax, %eax
-; X64-SDAGISEL-NEXT: # kill: def $al killed $al killed $eax
; X64-SDAGISEL-NEXT: retq
;
; X86-FASTISEL-LABEL: isnone_f80:
@@ -469,7 +461,6 @@ define i1 @isnone_f80(x86_fp80 %x) nounwind {
; X86-FASTISEL-NEXT: fldt {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstp %st(0)
; X86-FASTISEL-NEXT: xorl %eax, %eax
-; X86-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X86-FASTISEL-NEXT: retl
;
; X64-FASTISEL-LABEL: isnone_f80:
@@ -477,13 +468,11 @@ define i1 @isnone_f80(x86_fp80 %x) nounwind {
; X64-FASTISEL-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-FASTISEL-NEXT: fstp %st(0)
; X64-FASTISEL-NEXT: xorl %eax, %eax
-; X64-FASTISEL-NEXT: # kill: def $al killed $al killed $eax
; X64-FASTISEL-NEXT: retq
;
; X64-GISEL-LABEL: isnone_f80:
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: xorl %eax, %eax
-; X64-GISEL-NEXT: # kill: def $al killed $al killed $eax
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 0)
diff --git a/llvm/test/CodeGen/X86/knownbits-div.ll b/llvm/test/CodeGen/X86/knownbits-div.ll
index 698f56e93884a..02e20a9010cc6 100644
--- a/llvm/test/CodeGen/X86/knownbits-div.ll
+++ b/llvm/test/CodeGen/X86/knownbits-div.ll
@@ -5,7 +5,6 @@ define i8 @sdiv_neg_neg_high_bits(i8 %x, i8 %y) {
; CHECK-LABEL: sdiv_neg_neg_high_bits:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%num = or i8 %x, 128
%denum = or i8 %y, 131
@@ -46,7 +45,6 @@ define i8 @udiv_exact_even_odd(i8 %x, i8 %y) {
; CHECK-LABEL: udiv_exact_even_odd:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%num = and i8 %x, -2
%denum = or i8 %y, 1
diff --git a/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll b/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
index 35e6a04cff653..7bef94cca0d35 100644
--- a/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
+++ b/llvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
@@ -641,7 +641,6 @@ define i1 @add_ugtcmp_bad_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: add_ugtcmp_bad_i16_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: ret{{[l|q]}}
%tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ugt i16 %tmp0, -1 ; when we +1 it, it will wrap to 0
diff --git a/llvm/test/CodeGen/X86/memcmp-constant.ll b/llvm/test/CodeGen/X86/memcmp-constant.ll
index d828ba1ee3518..2059b8f804082 100644
--- a/llvm/test/CodeGen/X86/memcmp-constant.ll
+++ b/llvm/test/CodeGen/X86/memcmp-constant.ll
@@ -19,7 +19,6 @@ define i1 @length4_same_lt() nounwind {
; CHECK-LABEL: length4_same_lt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str1, i64 4) nounwind
%c = icmp slt i32 %m, 0
@@ -30,7 +29,6 @@ define i1 @length4_same_gt() nounwind {
; CHECK-LABEL: length4_same_gt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str1, i64 4) nounwind
%c = icmp sgt i32 %m, 0
@@ -81,7 +79,6 @@ define i1 @length4_gt() nounwind {
; CHECK-LABEL: length4_gt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str2, i64 4) nounwind
%c = icmp sgt i32 %m, 0
@@ -102,7 +99,6 @@ define i1 @length4_ge() nounwind {
; CHECK-LABEL: length4_ge:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%m = tail call i32 @memcmp(ptr @.str1, ptr @.str2, i64 4) nounwind
%c = icmp sge i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
index 55600502b992e..7d1422d3c961e 100644
--- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
+++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
@@ -35,7 +35,6 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X86-LABEL: length0_lt:
; X86: # %bb.0:
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
index 68ad6dc25eab1..3a3824a4ffe83 100644
--- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
+++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
@@ -41,7 +41,6 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X64-LABEL: length0_lt:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp-x32.ll b/llvm/test/CodeGen/X86/memcmp-x32.ll
index 633f614f9a1a7..28e732be9191d 100644
--- a/llvm/test/CodeGen/X86/memcmp-x32.ll
+++ b/llvm/test/CodeGen/X86/memcmp-x32.ll
@@ -34,7 +34,6 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X86-LABEL: length0_lt:
; X86: # %bb.0:
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/memcmp.ll b/llvm/test/CodeGen/X86/memcmp.ll
index 2571a7b7f1501..9e713bfa6c392 100644
--- a/llvm/test/CodeGen/X86/memcmp.ll
+++ b/llvm/test/CodeGen/X86/memcmp.ll
@@ -40,7 +40,6 @@ define i1 @length0_lt(ptr %X, ptr %Y) nounwind {
; X64-LABEL: length0_lt:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 0) nounwind
%c = icmp slt i32 %m, 0
diff --git a/llvm/test/CodeGen/X86/negate.ll b/llvm/test/CodeGen/X86/negate.ll
index b5cda9dfaee2f..38751d954b05e 100644
--- a/llvm/test/CodeGen/X86/negate.ll
+++ b/llvm/test/CodeGen/X86/negate.ll
@@ -23,7 +23,6 @@ define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
; CHECK-LABEL: negate_zero_or_minsigned_nsw:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%signbit = and i8 %x, 128
%neg = sub nsw i8 0, %signbit
diff --git a/llvm/test/CodeGen/X86/overflow.ll b/llvm/test/CodeGen/X86/overflow.ll
index f3768718c2b2d..5900e7674cd0e 100644
--- a/llvm/test/CodeGen/X86/overflow.ll
+++ b/llvm/test/CodeGen/X86/overflow.ll
@@ -57,8 +57,8 @@ define i128 @mulhioverflow(i64 %a, i64 %b, i64 %c) nounwind {
; X64-NEXT: mulq %rsi
; X64-NEXT: andl $1, %ecx
; X64-NEXT: addq %rdx, %rcx
-; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movq %rcx, %rax
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: retq
%1 = zext i64 %a to i128
%2 = zext i64 %b to i128
diff --git a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
index 8751211ee14aa..f3741dc202dc5 100644
--- a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
+++ b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
@@ -22,7 +22,6 @@ define i1 @plus_one() nounwind {
; CHECK32-NEXT: je .LBB0_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
-; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB0_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -38,7 +37,6 @@ define i1 @plus_one() nounwind {
; CHECK64-NEXT: je .LBB0_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
-; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB0_2: # %exit
; CHECK64-NEXT: movb $1, %al
@@ -72,7 +70,6 @@ define i1 @plus_forty_two() nounwind {
; CHECK32-NEXT: je .LBB1_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
-; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB1_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -88,7 +85,6 @@ define i1 @plus_forty_two() nounwind {
; CHECK64-NEXT: je .LBB1_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
-; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB1_2: # %exit
; CHECK64-NEXT: movb $1, %al
@@ -122,7 +118,6 @@ define i1 @minus_one() nounwind {
; CHECK32-NEXT: je .LBB2_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
-; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB2_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -138,7 +133,6 @@ define i1 @minus_one() nounwind {
; CHECK64-NEXT: je .LBB2_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
-; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB2_2: # %exit
; CHECK64-NEXT: movb $1, %al
@@ -172,7 +166,6 @@ define i1 @minus_forty_two() nounwind {
; CHECK32-NEXT: je .LBB3_2
; CHECK32-NEXT: # %bb.3: # %exit2
; CHECK32-NEXT: xorl %eax, %eax
-; CHECK32-NEXT: # kill: def $al killed $al killed $eax
; CHECK32-NEXT: retl
; CHECK32-NEXT: .LBB3_2: # %exit
; CHECK32-NEXT: movb $1, %al
@@ -188,7 +181,6 @@ define i1 @minus_forty_two() nounwind {
; CHECK64-NEXT: je .LBB3_2
; CHECK64-NEXT: # %bb.3: # %exit2
; CHECK64-NEXT: xorl %eax, %eax
-; CHECK64-NEXT: # kill: def $al killed $al killed $eax
; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB3_2: # %exit
; CHECK64-NEXT: movb $1, %al
diff --git a/llvm/test/CodeGen/X86/pr108728.ll b/llvm/test/CodeGen/X86/pr108728.ll
index 23c7eff837853..75a661891e726 100644
--- a/llvm/test/CodeGen/X86/pr108728.ll
+++ b/llvm/test/CodeGen/X86/pr108728.ll
@@ -5,7 +5,6 @@ define i8 @PR108728(i1 %a0) {
; CHECK-LABEL: PR108728:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%sel = select i1 %a0, i8 0, i8 1
%not = xor i8 %sel, -1
diff --git a/llvm/test/CodeGen/X86/pr132844.ll b/llvm/test/CodeGen/X86/pr132844.ll
index 43d12bb721080..dc9f006d93d12 100644
--- a/llvm/test/CodeGen/X86/pr132844.ll
+++ b/llvm/test/CodeGen/X86/pr132844.ll
@@ -4,13 +4,13 @@
define { ptr, i8 } @PR132844(<4 x ptr> %0, <4 x ptr> %1) {
; CHECK-LABEL: PR132844:
; CHECK: # %bb.0:
-; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vinsertf128 $1, 16, %ymm0, %ymm0
-; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vinsertf128 $1, 16, %ymm2, %ymm2
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3],ymm0[4,5],ymm2[6,7]
; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%3 = alloca [35 x ptr], i32 0, align 16
diff --git a/llvm/test/CodeGen/X86/pr61348.ll b/llvm/test/CodeGen/X86/pr61348.ll
index f17cbf3b62583..8ed0b690aeaa5 100644
--- a/llvm/test/CodeGen/X86/pr61348.ll
+++ b/llvm/test/CodeGen/X86/pr61348.ll
@@ -5,17 +5,18 @@
define i32 @PR61348() optsize {
; CHECK-LABEL: PR61348:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl $3, %ecx
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: rep;movsq (%rsi), %es:(%rdi)
-; CHECK-NEXT: movb 30, %al
-; CHECK-NEXT: movb %al, 30
-; CHECK-NEXT: movzwl 28, %eax
-; CHECK-NEXT: movw %ax, 28
-; CHECK-NEXT: movl 24, %eax
-; CHECK-NEXT: movl %eax, 24
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movb 30, %cl
+; CHECK-NEXT: movb %cl, 30
+; CHECK-NEXT: movzwl 28, %ecx
+; CHECK-NEXT: movw %cx, 28
+; CHECK-NEXT: movl 24, %ecx
+; CHECK-NEXT: movl %ecx, 24
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 null, ptr align 1 null, i64 31, i1 true)
ret i32 0
diff --git a/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll b/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
index d79b07854cae0..854a36489dfab 100644
--- a/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
+++ b/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
@@ -13,7 +13,6 @@ define i1 @dont_hit_assert(i24 signext %d) {
; CHECK-LABEL: dont_hit_assert:
; CHECK: # %bb.0: # %for.cond
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
for.cond:
%t0 = insertelement <8 x i24> zeroinitializer, i24 1, i32 0
diff --git a/llvm/test/CodeGen/X86/smul-with-overflow.ll b/llvm/test/CodeGen/X86/smul-with-overflow.ll
index 4884a0775443c..df167338268c4 100644
--- a/llvm/test/CodeGen/X86/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/smul-with-overflow.ll
@@ -16,7 +16,6 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind {
; X86-NEXT: movl $no, (%esp)
; X86-NEXT: calll printf at PLT
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: addl $12, %esp
; X86-NEXT: retl
; X86-NEXT: .LBB0_1: # %normal
@@ -29,17 +28,16 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind {
;
; X64-LABEL: test1:
; X64: # %bb.0: # %entry
-; X64-NEXT: pushq %rbx
+; X64-NEXT: pushq %rax
; X64-NEXT: movl %edi, %eax
; X64-NEXT: imull %esi, %eax
; X64-NEXT: jno .LBB0_1
; X64-NEXT: # %bb.2: # %overflow
-; X64-NEXT: xorl %ebx, %ebx
; X64-NEXT: movl $no, %edi
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
-; X64-NEXT: movl %ebx, %eax
-; X64-NEXT: popq %rbx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: popq %rcx
; X64-NEXT: retq
; X64-NEXT: .LBB0_1: # %normal
; X64-NEXT: movl $ok, %edi
@@ -47,7 +45,7 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
; X64-NEXT: movb $1, %al
-; X64-NEXT: popq %rbx
+; X64-NEXT: popq %rcx
; X64-NEXT: retq
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -75,7 +73,6 @@ define i1 @test2(i32 %v1, i32 %v2) nounwind {
; X86-NEXT: movl $no, (%esp)
; X86-NEXT: calll printf at PLT
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: addl $12, %esp
; X86-NEXT: retl
; X86-NEXT: .LBB1_2: # %normal
@@ -88,17 +85,16 @@ define i1 @test2(i32 %v1, i32 %v2) nounwind {
;
; X64-LABEL: test2:
; X64: # %bb.0: # %entry
-; X64-NEXT: pushq %rbx
+; X64-NEXT: pushq %rax
; X64-NEXT: movl %edi, %eax
; X64-NEXT: imull %esi, %eax
; X64-NEXT: jno .LBB1_2
; X64-NEXT: # %bb.1: # %overflow
-; X64-NEXT: xorl %ebx, %ebx
; X64-NEXT: movl $no, %edi
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
-; X64-NEXT: movl %ebx, %eax
-; X64-NEXT: popq %rbx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: popq %rcx
; X64-NEXT: retq
; X64-NEXT: .LBB1_2: # %normal
; X64-NEXT: movl $ok, %edi
@@ -106,7 +102,7 @@ define i1 @test2(i32 %v1, i32 %v2) nounwind {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: callq printf at PLT
; X64-NEXT: movb $1, %al
-; X64-NEXT: popq %rbx
+; X64-NEXT: popq %rcx
; X64-NEXT: retq
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
diff --git a/llvm/test/CodeGen/X86/sub-with-overflow.ll b/llvm/test/CodeGen/X86/sub-with-overflow.ll
index f9a43f7f18edf..d3bd3b1cdf0ac 100644
--- a/llvm/test/CodeGen/X86/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/sub-with-overflow.ll
@@ -15,7 +15,6 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: movl $no, (%esp)
; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
@@ -52,7 +51,6 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: movl $no, (%esp)
; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_1: # %normal
diff --git a/llvm/test/CodeGen/X86/subcarry.ll b/llvm/test/CodeGen/X86/subcarry.ll
index 2f3774f38a8c6..7d5db07c0172a 100644
--- a/llvm/test/CodeGen/X86/subcarry.ll
+++ b/llvm/test/CodeGen/X86/subcarry.ll
@@ -282,9 +282,8 @@ define { i64, i64, i1 } @subcarry_2x64_and_reversed(i64 %x0, i64 %x1, i64 %y0, i
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: sbbq %rcx, %rsi
-; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movq %rsi, %rdx
-; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
diff --git a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
index 71731f91351ca..f0dc17b556613 100644
--- a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
+++ b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
@@ -7,10 +7,10 @@ define i64 @foo() nounwind {
; CHECK-NEXT: cmpl $12, 0
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb65
-; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1: # %bb56
entry:
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index e911daab4b06d..d9ab2f7d1f5fb 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -196,7 +196,6 @@ define i1 @dont_merge_oddly(ptr %result) nounwind {
; CHECK-NEXT: jbe .LBB2_2
; CHECK-NEXT: .LBB2_4: # %bb26
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
entry:
%tmp4 = getelementptr float, ptr %result, i32 2
diff --git a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
index 0d770ba1f6529..ecbbaf3ab362d 100644
--- a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
+++ b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
@@ -137,7 +137,6 @@ define zeroext i1 @zext_i1(i1 %k) {
; CHECK-NEXT: je _foo_i1 ## TAILCALL
; CHECK-NEXT: ## %bb.1: ## %land.end
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
entry:
br i1 %k, label %land.end, label %land.rhs
diff --git a/llvm/test/CodeGen/X86/trunc-to-bool.ll b/llvm/test/CodeGen/X86/trunc-to-bool.ll
index 1800eb157603b..5a5d057597465 100644
--- a/llvm/test/CodeGen/X86/trunc-to-bool.ll
+++ b/llvm/test/CodeGen/X86/trunc-to-bool.ll
@@ -26,7 +26,6 @@ define i1 @test2(i32 %val, i32 %mask) nounwind {
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_2: # %ret_false
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retl
entry:
%shifted = ashr i32 %val, %mask
diff --git a/llvm/test/CodeGen/X86/umul-with-carry.ll b/llvm/test/CodeGen/X86/umul-with-carry.ll
index 0106e9a3e8d63..787ce2fc57d73 100644
--- a/llvm/test/CodeGen/X86/umul-with-carry.ll
+++ b/llvm/test/CodeGen/X86/umul-with-carry.ll
@@ -17,7 +17,6 @@ define i1 @func(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: calll printf at PLT
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
; CHECK-NEXT: pushl %eax
diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll
index 914b2f7e1ff69..c2a8002c949ce 100644
--- a/llvm/test/CodeGen/X86/xaluo.ll
+++ b/llvm/test/CodeGen/X86/xaluo.ll
@@ -647,7 +647,6 @@ define zeroext i1 @saddobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB31_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: saddobri32:
@@ -685,7 +684,6 @@ define zeroext i1 @saddobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB32_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: saddobri64:
@@ -723,7 +721,6 @@ define zeroext i1 @uaddobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB33_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: uaddobri32:
@@ -761,7 +758,6 @@ define zeroext i1 @uaddobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB34_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: uaddobri64:
@@ -799,7 +795,6 @@ define zeroext i1 @ssubobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB35_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: ssubobri32:
@@ -837,7 +832,6 @@ define zeroext i1 @ssubobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB36_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: ssubobri64:
@@ -875,7 +869,6 @@ define zeroext i1 @usubobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB37_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: usubobri32:
@@ -913,7 +906,6 @@ define zeroext i1 @usubobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: LBB38_1: ## %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: ## kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: usubobri64:
@@ -948,7 +940,6 @@ define {i64, i1} @saddoovf(i64 %a, i64 %b) {
; CHECK-NEXT: shrq $31, %rsi
; CHECK-NEXT: leaq (%rsi,%rdi), %rax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%1 = ashr i64 %a, 17
%2 = lshr i64 %b, 31
@@ -963,7 +954,6 @@ define {i64, i1} @ssuboovf(i64 %a, i64 %b) {
; CHECK-NEXT: shrq $22, %rsi
; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%1 = and i64 %a, 65535
%2 = lshr i64 %b, 22
@@ -978,7 +968,6 @@ define {i64, i1} @uaddoovf(i64 %a, i64 %b) {
; CHECK-NEXT: movzbl %sil, %eax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%1 = and i64 %a, 255
%2 = and i64 %b, 255
@@ -992,7 +981,6 @@ define {i64, i1} @usuboovf(i64 %a, i64 %b) {
; CHECK-NEXT: movq %rsi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: ## kill: def $dl killed $dl killed $edx
; CHECK-NEXT: retq
%t0 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %a)
%v0 = extractvalue {i64, i1} %t0, 0
diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll
index 1387361e4f0c9..a076d0d762aa3 100644
--- a/llvm/test/CodeGen/X86/xmulo.ll
+++ b/llvm/test/CodeGen/X86/xmulo.ll
@@ -8,17 +8,15 @@
define {i64, i1} @t1() nounwind {
; CHECK-LABEL: t1:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl $72, %eax
-; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: retq
;
; WIN32-LABEL: t1:
; WIN32: # %bb.0:
-; WIN32-NEXT: xorl %ecx, %ecx
; WIN32-NEXT: movl $72, %eax
-; WIN32-NEXT: movl %ecx, %edx
-; WIN32-NEXT: # kill: def $cl killed $cl killed $ecx
+; WIN32-NEXT: xorl %edx, %edx
+; WIN32-NEXT: xorl %ecx, %ecx
; WIN32-NEXT: retl
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 8)
ret {i64, i1} %1
@@ -28,14 +26,14 @@ define {i64, i1} @t2() nounwind {
; CHECK-LABEL: t2:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: retq
;
; WIN32-LABEL: t2:
; WIN32: # %bb.0:
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: movl %eax, %edx
-; WIN32-NEXT: movl %eax, %ecx
+; WIN32-NEXT: xorl %edx, %edx
+; WIN32-NEXT: xorl %ecx, %ecx
; WIN32-NEXT: retl
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 0)
ret {i64, i1} %1
@@ -739,7 +737,6 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB15_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri8:
@@ -770,7 +767,6 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB15_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri8:
@@ -783,7 +779,6 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB15_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 %v1, i8 %v2)
%val = extractvalue {i8, i1} %t, 0
@@ -807,7 +802,6 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB16_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri16:
@@ -835,7 +829,6 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB16_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri16:
@@ -848,7 +841,6 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB16_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %v1, i16 %v2)
%val = extractvalue {i16, i1} %t, 0
@@ -872,7 +864,6 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB17_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri32:
@@ -898,7 +889,6 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB17_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri32:
@@ -911,7 +901,6 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB17_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -935,7 +924,6 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB18_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: smulobri64:
@@ -961,7 +949,6 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB18_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: smulobri64:
@@ -1012,9 +999,9 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: xorl %eax, %esi
; WIN32-NEXT: orl %edx, %esi
; WIN32-NEXT: jne LBB18_1
-; WIN32-NEXT: # %bb.2: # %continue
+; WIN32-NEXT: # %bb.3: # %continue
; WIN32-NEXT: movb $1, %al
-; WIN32-NEXT: LBB18_3: # %continue
+; WIN32-NEXT: LBB18_2: # %overflow
; WIN32-NEXT: addl $4, %esp
; WIN32-NEXT: popl %esi
; WIN32-NEXT: popl %edi
@@ -1023,8 +1010,7 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB18_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
-; WIN32-NEXT: jmp LBB18_3
+; WIN32-NEXT: jmp LBB18_2
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -1049,7 +1035,6 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB19_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri8:
@@ -1080,7 +1065,6 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB19_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri8:
@@ -1093,7 +1077,6 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB19_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %v1, i8 %v2)
%val = extractvalue {i8, i1} %t, 0
@@ -1119,7 +1102,6 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB20_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri16:
@@ -1150,7 +1132,6 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB20_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri16:
@@ -1163,7 +1144,6 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB20_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %v1, i16 %v2)
%val = extractvalue {i16, i1} %t, 0
@@ -1188,7 +1168,6 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB21_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri32:
@@ -1216,7 +1195,6 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB21_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri32:
@@ -1229,7 +1207,6 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB21_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
; WIN32-NEXT: retl
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -1254,7 +1231,6 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; SDAG-NEXT: retq
; SDAG-NEXT: .LBB22_1: # %overflow
; SDAG-NEXT: xorl %eax, %eax
-; SDAG-NEXT: # kill: def $al killed $al killed $eax
; SDAG-NEXT: retq
;
; FAST-LABEL: umulobri64:
@@ -1282,7 +1258,6 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; WIN64-NEXT: retq
; WIN64-NEXT: .LBB22_1: # %overflow
; WIN64-NEXT: xorl %eax, %eax
-; WIN64-NEXT: # kill: def $al killed $al killed $eax
; WIN64-NEXT: retq
;
; WIN32-LABEL: umulobri64:
@@ -1315,9 +1290,9 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: orb %ch, %al
; WIN32-NEXT: subb $1, %al
; WIN32-NEXT: je LBB22_1
-; WIN32-NEXT: # %bb.2: # %continue
+; WIN32-NEXT: # %bb.3: # %continue
; WIN32-NEXT: movb $1, %al
-; WIN32-NEXT: LBB22_3: # %continue
+; WIN32-NEXT: LBB22_2: # %overflow
; WIN32-NEXT: popl %esi
; WIN32-NEXT: popl %edi
; WIN32-NEXT: popl %ebx
@@ -1325,8 +1300,7 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; WIN32-NEXT: retl
; WIN32-NEXT: LBB22_1: # %overflow
; WIN32-NEXT: xorl %eax, %eax
-; WIN32-NEXT: # kill: def $al killed $al killed $eax
-; WIN32-NEXT: jmp LBB22_3
+; WIN32-NEXT: jmp LBB22_2
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/DebugInfo/ARM/constant-dbgloc.ll b/llvm/test/DebugInfo/ARM/constant-dbgloc.ll
index c3b65ff6e19d5..721e20d06e810 100644
--- a/llvm/test/DebugInfo/ARM/constant-dbgloc.ll
+++ b/llvm/test/DebugInfo/ARM/constant-dbgloc.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -filetype=asm %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -34,3 +35,5 @@ entry:
!9 = !{i32 2, !"Debug Info Version", i32 3}
!10 = !{i32 1, !"wchar_size", i32 4}
!11 = !DILocation(line: 4, column: 5, scope: !4)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
index f10b9fdaa6b0e..e008125f94bba 100644
--- a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
+++ b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
@@ -42,11 +42,10 @@ registers:
body: |
bb.0.entry:
; CHECK-LABEL: name: main
- ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, debug-location !DILocation(line: 14, column: 11, scope: <0x{{[0-9a-f]+}}>)
- ; CHECK-NEXT: DBG_VALUE [[MOV32r0_]], $noreg, <0x{{[0-9a-f]+}}>, !DIExpression(), debug-location !DILocation(line: 13, column: 7, scope: <0x{{[0-9a-f]+}}>)
- ; CHECK-NEXT: DBG_VALUE [[MOV32r0_]], $noreg, <0x{{[0-9a-f]+}}>, !DIExpression(), debug-location !DILocation(line: 16, column: 3, scope: <0x{{[0-9a-f]+}}>)
- ; CHECK-NEXT: $eax = COPY [[MOV32r0_]], debug-location !DILocation(line: 16, column: 3, scope: <0x{{[0-9a-f]+}}>)
- ; CHECK-NEXT: RET 0, killed $eax, debug-location !DILocation(line: 16, column: 3, scope: <0x{{[0-9a-f]+}}>)
+ ; CHECK: $eax = MOV32r0 implicit-def dead $eflags, debug-location !DILocation(line: 16, column: 3, scope: <0x612fb4e96a00>)
+ ; CHECK-NEXT: DBG_VALUE $eax, $noreg, <0x612fb4e97f18>, !DIExpression(), debug-location !DILocation(line: 16, column: 3, scope: <0x612fb4e96a00>)
+ ; CHECK-NEXT: DBG_VALUE $eax, $noreg, <0x612fb4e98528>, !DIExpression(), debug-location !DILocation(line: 13, column: 7, scope: <0x612fb4e96a00>)
+ ; CHECK-NEXT: RET 0, killed $eax, debug-location !DILocation(line: 16, column: 3, scope: <0x612fb4e96a00>)
%0 = MOV32r0 implicit-def dead $eflags, debug-location !20
DBG_VALUE %0, _, !18, !DIExpression(), debug-location !21
DBG_VALUE %0, _, !19, !DIExpression(), debug-location !22
diff --git a/llvm/test/DebugInfo/XCOFF/empty-prolog.ll b/llvm/test/DebugInfo/XCOFF/empty-prolog.ll
index 78e90cc5ffcf7..d5111d76c4d20 100644
--- a/llvm/test/DebugInfo/XCOFF/empty-prolog.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty-prolog.ll
@@ -1,5 +1,6 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t %s
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t %s
; RUN: llvm-dwarfdump -debug-line %t | FileCheck %s
; CHECK: Address Line Column File ISA Discriminator OpIndex Flags
diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll
index af2f74fb82b8f..d8853eb326a4c 100644
--- a/llvm/test/DebugInfo/XCOFF/empty.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s --check-prefix=ASM32
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc64-ibm-aix-xcoff < %s | \
@@ -10,6 +11,25 @@ target datalayout = "E-m:a-p:32:32-i64:64-n32"
; Function Attrs: noinline nounwind optnone
define i32 @main() #0 !dbg !8 {
+; ASM32-LABEL: main:
+; ASM32: # %bb.0: # %entry
+; ASM32-NEXT: L..tmp0:
+; ASM32-NEXT: li 3, 0
+; ASM32-NEXT: stw 3, -4(1)
+; ASM32-NEXT: L..tmp1:
+; ASM32-NEXT: L..tmp2:
+; ASM32-NEXT: blr
+; ASM32-NEXT: L..tmp3:
+;
+; ASM64-LABEL: main:
+; ASM64: # %bb.0: # %entry
+; ASM64-NEXT: L..tmp0:
+; ASM64-NEXT: li 3, 0
+; ASM64-NEXT: stw 3, -4(1)
+; ASM64-NEXT: L..tmp1:
+; ASM64-NEXT: L..tmp2:
+; ASM64-NEXT: blr
+; ASM64-NEXT: L..tmp3:
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
diff --git a/llvm/test/DebugInfo/XCOFF/explicit-section.ll b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
index 0ae9289c08df3..3f591fa708076 100644
--- a/llvm/test/DebugInfo/XCOFF/explicit-section.ll
+++ b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s
@@ -7,12 +8,36 @@ target datalayout = "E-m:a-p:32:32-i64:64-n32"
; Function Attrs: noinline nounwind optnone
define i32 @bar() #0 !dbg !8 {
+; CHECK-LABEL: bar:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: L..tmp0:
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: blr
+; CHECK-NEXT: L..tmp1:
entry:
ret i32 1, !dbg !13
}
; Function Attrs: noinline nounwind optnone
define i32 @main() #0 section "explicit_main_sec" !dbg !14 {
+; CHECK-LABEL: main:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: L..tmp2:
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -64(1)
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: stw 0, 72(1)
+; CHECK-NEXT: stw 3, 60(1)
+; CHECK-NEXT: L..tmp3:
+; CHECK-NEXT: L..tmp4:
+; CHECK-NEXT: bl .bar
+; CHECK-NEXT: nop
+; CHECK-NEXT: L..tmp5:
+; CHECK-NEXT: addi 1, 1, 64
+; CHECK-NEXT: lwz 0, 8(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
+; CHECK-NEXT: L..tmp6:
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
diff --git a/llvm/test/DebugInfo/XCOFF/function-sections.ll b/llvm/test/DebugInfo/XCOFF/function-sections.ll
index 6a86ae6796fbc..bea47b77ca440 100644
--- a/llvm/test/DebugInfo/XCOFF/function-sections.ll
+++ b/llvm/test/DebugInfo/XCOFF/function-sections.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff -function-sections \
; RUN: < %s | FileCheck %s
@@ -278,7 +279,7 @@ entry:
; CHECK-NEXT: .byte 20 # Start sequence
; CHECK-NEXT: .byte 0 # Set address to L..func_end0
; CHECK-NEXT: .byte 5
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 2
; CHECK-NEXT: .vbyte 4, L..func_end0
; CHECK-NEXT: .byte 0 # End sequence
; CHECK-NEXT: .byte 1
@@ -299,3 +300,5 @@ entry:
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 1
; CHECK-NEXT: L..debug_line_end0:
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
index 429bee4195fa9..cdadba1325e34 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
@@ -119,25 +119,24 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, x at rel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, x at rel32@hi+12
-; CHECK-NEXT: v_mov_b32_e32 v2, 1
-; CHECK-NEXT: v_mov_b32_e32 v3, 2
-; CHECK-NEXT: v_mov_b32_e32 v4, 3
-; CHECK-NEXT: v_mov_b32_e32 v5, 4
+; CHECK-NEXT: v_mov_b32_e32 v3, 1
+; CHECK-NEXT: v_mov_b32_e32 v4, 2
+; CHECK-NEXT: v_mov_b32_e32 v5, 3
+; CHECK-NEXT: v_mov_b32_e32 v6, 4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12
-; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16
-; CHECK-NEXT: v_mov_b32_e32 v0, s4
-; CHECK-NEXT: v_mov_b32_e32 v1, s5
-; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16
+; CHECK-NEXT: v_mov_b32_e32 v1, s4
+; CHECK-NEXT: v_mov_b32_e32 v2, s5
+; CHECK-NEXT: flat_store_dword v[1:2], v3
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: s_mov_b32 s33, s6
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
index 842fd8836da7e..875cc85be8f04 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
@@ -96,25 +96,24 @@ define dso_local i32 @main() #0 {
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, x at rel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, x at rel32@hi+12
-; CHECK-NEXT: v_mov_b32_e32 v2, 1
-; CHECK-NEXT: v_mov_b32_e32 v3, 2
-; CHECK-NEXT: v_mov_b32_e32 v4, 3
-; CHECK-NEXT: v_mov_b32_e32 v5, 4
+; CHECK-NEXT: v_mov_b32_e32 v3, 1
+; CHECK-NEXT: v_mov_b32_e32 v4, 2
+; CHECK-NEXT: v_mov_b32_e32 v5, 3
+; CHECK-NEXT: v_mov_b32_e32 v6, 4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12
-; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16
-; CHECK-NEXT: v_mov_b32_e32 v0, s4
-; CHECK-NEXT: v_mov_b32_e32 v1, s5
-; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16
+; CHECK-NEXT: v_mov_b32_e32 v1, s4
+; CHECK-NEXT: v_mov_b32_e32 v2, s5
+; CHECK-NEXT: flat_store_dword v[1:2], v3
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: s_mov_b32 s33, s6
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
index 2dfb725f55665..91bb79f19ca5b 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
@@ -100,23 +100,20 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="none" }
; CHECK-NEXT: sub sp, sp, #20
; CHECK-NEXT: ldr r0, .LCPI1_0
; CHECK-NEXT: mov r1, #1
-; CHECK-NEXT: mov r2, #3
-; CHECK-NEXT: mov r3, #4
+; CHECK-NEXT: mov r12, #2
+; CHECK-NEXT: mov r3, #3
+; CHECK-NEXT: mov r2, #4
; CHECK-NEXT: str r1, [sp, #12]
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: str r0, [sp, #16]
-; CHECK-NEXT: mov r0, #2
-; CHECK-NEXT: str r0, [sp, #8]
-; CHECK-NEXT: str r2, [sp, #4]
-; CHECK-NEXT: str r3, [sp]
+; CHECK-NEXT: str r12, [sp, #8]
+; CHECK-NEXT: str r3, [sp, #4]
+; CHECK-NEXT: str r2, [sp]
; CHECK-NEXT: @APP
; CHECK-NEXT: @NO_APP
-; CHECK-NEXT: str r0, [sp, #8]
-; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: str r1, [sp, #12]
-; CHECK-NEXT: str r2, [sp, #4]
-; CHECK-NEXT: str r3, [sp]
+; CHECK-NEXT: stm sp, {r2, r3, r12}
; CHECK-NEXT: add sp, sp, #20
; CHECK-NEXT: mov pc, lr
; CHECK-NEXT: .p2align 2
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
index 85d3389cdaaf9..a5e76707c02eb 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
@@ -77,23 +77,20 @@ define dso_local i32 @main() #0 {
; CHECK-NEXT: sub sp, sp, #20
; CHECK-NEXT: ldr r0, .LCPI1_0
; CHECK-NEXT: mov r1, #1
-; CHECK-NEXT: mov r2, #3
-; CHECK-NEXT: mov r3, #4
+; CHECK-NEXT: mov r12, #2
+; CHECK-NEXT: mov r3, #3
+; CHECK-NEXT: mov r2, #4
; CHECK-NEXT: str r1, [sp, #12]
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: str r0, [sp, #16]
-; CHECK-NEXT: mov r0, #2
-; CHECK-NEXT: str r0, [sp, #8]
-; CHECK-NEXT: str r2, [sp, #4]
-; CHECK-NEXT: str r3, [sp]
+; CHECK-NEXT: str r12, [sp, #8]
+; CHECK-NEXT: str r3, [sp, #4]
+; CHECK-NEXT: str r2, [sp]
; CHECK-NEXT: @APP
; CHECK-NEXT: @NO_APP
-; CHECK-NEXT: str r0, [sp, #8]
-; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: str r1, [sp, #12]
-; CHECK-NEXT: str r2, [sp, #4]
-; CHECK-NEXT: str r3, [sp]
+; CHECK-NEXT: stm sp, {r2, r3, r12}
; CHECK-NEXT: add sp, sp, #20
; CHECK-NEXT: mov pc, lr
; CHECK-NEXT: .p2align 2
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected
index 36519299c1ffb..abd1c955f88ef 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected
@@ -113,7 +113,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: mov #4, -20(r4)
; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: clr r12
-; CHECK-NEXT: clr r13
+; CHECK-NEXT: mov r12, r13
; CHECK-NEXT: add #20, r1
; CHECK-NEXT: pop r4
; CHECK-NEXT: .cfi_def_cfa r1, 2
@@ -151,7 +151,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: clr -18(r4)
; CHECK-NEXT: mov #4, -20(r4)
; CHECK-NEXT: clr r12
-; CHECK-NEXT: clr r13
+; CHECK-NEXT: mov r12, r13
; CHECK-NEXT: add #20, r1
; CHECK-NEXT: pop r4
; CHECK-NEXT: .cfi_def_cfa r1, 2
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected
index ffe417b9d618b..ad7447db37500 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected
@@ -54,7 +54,7 @@ define dso_local i32 @check_boundaries() #0 {
; CHECK-NEXT: mov #4, -20(r4)
; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: clr r12
-; CHECK-NEXT: clr r13
+; CHECK-NEXT: mov r12, r13
; CHECK-NEXT: add #20, r1
; CHECK-NEXT: pop r4
; CHECK-NEXT: .cfi_def_cfa r1, 2
@@ -128,7 +128,7 @@ define dso_local i32 @main() #0 {
; CHECK-NEXT: clr -18(r4)
; CHECK-NEXT: mov #4, -20(r4)
; CHECK-NEXT: clr r12
-; CHECK-NEXT: clr r13
+; CHECK-NEXT: mov r12, r13
; CHECK-NEXT: add #20, r1
; CHECK-NEXT: pop r4
; CHECK-NEXT: .cfi_def_cfa r1, 2
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected
index 2b4c8025af30e..9e2d367b50bf4 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected
@@ -108,24 +108,23 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: mr 31, 1
; CHECK-NEXT: .cfi_def_cfa_register r31
; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 1
+; CHECK-NEXT: li 5, 2
+; CHECK-NEXT: li 6, 3
+; CHECK-NEXT: li 7, 4
+; CHECK-NEXT: lis 8, x at ha
; CHECK-NEXT: stw 3, 24(31)
-; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: li 4, 2
-; CHECK-NEXT: li 5, 3
-; CHECK-NEXT: li 6, 4
-; CHECK-NEXT: lis 7, x at ha
-; CHECK-NEXT: stw 3, 20(31)
-; CHECK-NEXT: stw 4, 16(31)
-; CHECK-NEXT: stw 5, 12(31)
-; CHECK-NEXT: stw 6, 8(31)
-; CHECK-NEXT: stw 3, x at l(7)
+; CHECK-NEXT: stw 4, 20(31)
+; CHECK-NEXT: stw 5, 16(31)
+; CHECK-NEXT: stw 6, 12(31)
+; CHECK-NEXT: stw 7, 8(31)
+; CHECK-NEXT: stw 4, x at l(8)
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: stw 3, 20(31)
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: stw 4, 16(31)
-; CHECK-NEXT: stw 5, 12(31)
-; CHECK-NEXT: stw 6, 8(31)
+; CHECK-NEXT: stw 4, 20(31)
+; CHECK-NEXT: stw 5, 16(31)
+; CHECK-NEXT: stw 6, 12(31)
+; CHECK-NEXT: stw 7, 8(31)
; CHECK-NEXT: lwz 31, 28(1)
; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: blr
@@ -168,23 +167,22 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; AIX-NEXT: lwz 4, L..C0(2) # @x
; AIX-NEXT: mr 31, 1
; AIX-NEXT: li 3, 0
+; AIX-NEXT: li 5, 1
+; AIX-NEXT: li 6, 2
+; AIX-NEXT: li 7, 3
+; AIX-NEXT: li 8, 4
; AIX-NEXT: stw 3, 40(31)
-; AIX-NEXT: li 3, 1
-; AIX-NEXT: li 5, 2
-; AIX-NEXT: li 6, 3
-; AIX-NEXT: li 7, 4
-; AIX-NEXT: stw 3, 36(31)
-; AIX-NEXT: stw 5, 32(31)
-; AIX-NEXT: stw 6, 28(31)
-; AIX-NEXT: stw 7, 24(31)
-; AIX-NEXT: stw 3, 0(4)
+; AIX-NEXT: stw 5, 36(31)
+; AIX-NEXT: stw 6, 32(31)
+; AIX-NEXT: stw 7, 28(31)
+; AIX-NEXT: stw 8, 24(31)
+; AIX-NEXT: stw 5, 0(4)
; AIX-NEXT: #APP
; AIX-NEXT: #NO_APP
-; AIX-NEXT: stw 3, 36(31)
-; AIX-NEXT: li 3, 0
-; AIX-NEXT: stw 5, 32(31)
-; AIX-NEXT: stw 6, 28(31)
-; AIX-NEXT: stw 7, 24(31)
+; AIX-NEXT: stw 5, 36(31)
+; AIX-NEXT: stw 6, 32(31)
+; AIX-NEXT: stw 7, 28(31)
+; AIX-NEXT: stw 8, 24(31)
; AIX-NEXT: addi 1, 1, 48
; AIX-NEXT: lwz 31, -4(1)
; AIX-NEXT: blr
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected
index 601abc548a45e..ee87feec40151 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected
@@ -116,24 +116,23 @@ define dso_local i32 @main() #0 {
; CHECK-NEXT: mr 31, 1
; CHECK-NEXT: .cfi_def_cfa_register r31
; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 1
+; CHECK-NEXT: li 5, 2
+; CHECK-NEXT: li 6, 3
+; CHECK-NEXT: li 7, 4
+; CHECK-NEXT: lis 8, x at ha
; CHECK-NEXT: stw 3, 24(31)
-; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: li 4, 2
-; CHECK-NEXT: li 5, 3
-; CHECK-NEXT: li 6, 4
-; CHECK-NEXT: lis 7, x at ha
-; CHECK-NEXT: stw 3, 20(31)
-; CHECK-NEXT: stw 4, 16(31)
-; CHECK-NEXT: stw 5, 12(31)
-; CHECK-NEXT: stw 6, 8(31)
-; CHECK-NEXT: stw 3, x at l(7)
+; CHECK-NEXT: stw 4, 20(31)
+; CHECK-NEXT: stw 5, 16(31)
+; CHECK-NEXT: stw 6, 12(31)
+; CHECK-NEXT: stw 7, 8(31)
+; CHECK-NEXT: stw 4, x at l(8)
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: stw 3, 20(31)
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: stw 4, 16(31)
-; CHECK-NEXT: stw 5, 12(31)
-; CHECK-NEXT: stw 6, 8(31)
+; CHECK-NEXT: stw 4, 20(31)
+; CHECK-NEXT: stw 5, 16(31)
+; CHECK-NEXT: stw 6, 12(31)
+; CHECK-NEXT: stw 7, 8(31)
; CHECK-NEXT: lwz 31, 28(1)
; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: blr
@@ -145,23 +144,22 @@ define dso_local i32 @main() #0 {
; AIX-NEXT: lwz 4, L..C0(2) # @x
; AIX-NEXT: mr 31, 1
; AIX-NEXT: li 3, 0
+; AIX-NEXT: li 5, 1
+; AIX-NEXT: li 6, 2
+; AIX-NEXT: li 7, 3
+; AIX-NEXT: li 8, 4
; AIX-NEXT: stw 3, 40(31)
-; AIX-NEXT: li 3, 1
-; AIX-NEXT: li 5, 2
-; AIX-NEXT: li 6, 3
-; AIX-NEXT: li 7, 4
-; AIX-NEXT: stw 3, 36(31)
-; AIX-NEXT: stw 5, 32(31)
-; AIX-NEXT: stw 6, 28(31)
-; AIX-NEXT: stw 7, 24(31)
-; AIX-NEXT: stw 3, 0(4)
+; AIX-NEXT: stw 5, 36(31)
+; AIX-NEXT: stw 6, 32(31)
+; AIX-NEXT: stw 7, 28(31)
+; AIX-NEXT: stw 8, 24(31)
+; AIX-NEXT: stw 5, 0(4)
; AIX-NEXT: #APP
; AIX-NEXT: #NO_APP
-; AIX-NEXT: stw 3, 36(31)
-; AIX-NEXT: li 3, 0
-; AIX-NEXT: stw 5, 32(31)
-; AIX-NEXT: stw 6, 28(31)
-; AIX-NEXT: stw 7, 24(31)
+; AIX-NEXT: stw 5, 36(31)
+; AIX-NEXT: stw 6, 32(31)
+; AIX-NEXT: stw 7, 28(31)
+; AIX-NEXT: stw 8, 24(31)
; AIX-NEXT: addi 1, 1, 48
; AIX-NEXT: lwz 31, -4(1)
; AIX-NEXT: blr
diff --git a/temp b/temp
new file mode 100644
index 0000000000000..8101ff2bb0cac
--- /dev/null
+++ b/temp
@@ -0,0 +1,178 @@
+ .file "filename.ll"
+ .text
+ .globl test # -- Begin function test
+ .p2align 3
+ .type test, at function
+test: # @test
+.Ltest$local:
+ .type .Ltest$local, at function
+.Lfunc_begin0:
+ .file 1 "/home/yhs/ttmp" "/home/yhs/ttmp/t.c"
+ .loc 1 1 0 # /home/yhs/ttmp/t.c:1:0
+ .cfi_startproc
+# %bb.0:
+ w0 = 0
+.Ltmp0:
+ .loc 1 1 14 prologue_end # /home/yhs/ttmp/t.c:1:14
+.Ltmp1:
+.Ltmp2:
+ exit
+.Ltmp3:
+.Ltmp4:
+.Lfunc_end0:
+ .size test, .Lfunc_end0-test
+ .size .Ltest$local, .Lfunc_end0-test
+ .cfi_endproc
+ # -- End function
+ .section .debug_abbrev,"", at progbits
+ .byte 1 # Abbreviation Code
+ .byte 17 # DW_TAG_compile_unit
+ .byte 1 # DW_CHILDREN_yes
+ .byte 37 # DW_AT_producer
+ .byte 14 # DW_FORM_strp
+ .byte 19 # DW_AT_language
+ .byte 5 # DW_FORM_data2
+ .byte 3 # DW_AT_name
+ .byte 14 # DW_FORM_strp
+ .byte 16 # DW_AT_stmt_list
+ .byte 23 # DW_FORM_sec_offset
+ .byte 27 # DW_AT_comp_dir
+ .byte 14 # DW_FORM_strp
+ .byte 17 # DW_AT_low_pc
+ .byte 1 # DW_FORM_addr
+ .byte 18 # DW_AT_high_pc
+ .byte 6 # DW_FORM_data4
+ .byte 0 # EOM(1)
+ .byte 0 # EOM(2)
+ .byte 2 # Abbreviation Code
+ .byte 46 # DW_TAG_subprogram
+ .byte 0 # DW_CHILDREN_no
+ .byte 17 # DW_AT_low_pc
+ .byte 1 # DW_FORM_addr
+ .byte 18 # DW_AT_high_pc
+ .byte 6 # DW_FORM_data4
+ .byte 64 # DW_AT_frame_base
+ .byte 24 # DW_FORM_exprloc
+ .byte 3 # DW_AT_name
+ .byte 14 # DW_FORM_strp
+ .byte 58 # DW_AT_decl_file
+ .byte 11 # DW_FORM_data1
+ .byte 59 # DW_AT_decl_line
+ .byte 11 # DW_FORM_data1
+ .byte 73 # DW_AT_type
+ .byte 19 # DW_FORM_ref4
+ .byte 63 # DW_AT_external
+ .byte 25 # DW_FORM_flag_present
+ .byte 0 # EOM(1)
+ .byte 0 # EOM(2)
+ .byte 3 # Abbreviation Code
+ .byte 36 # DW_TAG_base_type
+ .byte 0 # DW_CHILDREN_no
+ .byte 3 # DW_AT_name
+ .byte 14 # DW_FORM_strp
+ .byte 62 # DW_AT_encoding
+ .byte 11 # DW_FORM_data1
+ .byte 11 # DW_AT_byte_size
+ .byte 11 # DW_FORM_data1
+ .byte 0 # EOM(1)
+ .byte 0 # EOM(2)
+ .byte 0 # EOM(3)
+ .section .debug_info,"", at progbits
+.Lcu_begin0:
+ .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit
+.Ldebug_info_start0:
+ .short 4 # DWARF version number
+ .long .debug_abbrev # Offset Into Abbrev. Section
+ .byte 8 # Address Size (in bytes)
+ .byte 1 # Abbrev [1] 0xb:0x40 DW_TAG_compile_unit
+ .long .Linfo_string0 # DW_AT_producer
+ .short 12 # DW_AT_language
+ .long .Linfo_string1 # DW_AT_name
+ .long .Lline_table_start0 # DW_AT_stmt_list
+ .long .Linfo_string2 # DW_AT_comp_dir
+ .quad .Lfunc_begin0 # DW_AT_low_pc
+ .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc
+ .byte 2 # Abbrev [2] 0x2a:0x19 DW_TAG_subprogram
+ .quad .Lfunc_begin0 # DW_AT_low_pc
+ .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc
+ .byte 1 # DW_AT_frame_base
+ .byte 90
+ .long .Linfo_string3 # DW_AT_name
+ .byte 1 # DW_AT_decl_file
+ .byte 1 # DW_AT_decl_line
+ .long 67 # DW_AT_type
+ # DW_AT_external
+ .byte 3 # Abbrev [3] 0x43:0x7 DW_TAG_base_type
+ .long .Linfo_string4 # DW_AT_name
+ .byte 5 # DW_AT_encoding
+ .byte 4 # DW_AT_byte_size
+ .byte 0 # End Of Children Mark
+.Ldebug_info_end0:
+ .section .debug_str,"MS", at progbits,1
+.Linfo_string0:
+ .asciz "clang version 8.0.20181009 " # string offset=0
+.Linfo_string1:
+ .asciz "/home/yhs/ttmp/t.c" # string offset=28
+.Linfo_string2:
+ .asciz "/home/yhs/ttmp" # string offset=47
+.Linfo_string3:
+ .asciz "test" # string offset=62
+.Linfo_string4:
+ .asciz "int" # string offset=67
+ .section .BTF,"", at progbits
+ .short 60319 # 0xeb9f
+ .byte 1
+ .byte 0
+ .long 24
+ .long 0
+ .long 40
+ .long 40
+ .long 35
+ .long 0 # BTF_KIND_FUNC_PROTO(id = 1)
+ .long 218103808 # 0xd000000
+ .long 2
+ .long 1 # BTF_KIND_INT(id = 2)
+ .long 16777216 # 0x1000000
+ .long 4
+ .long 16777248 # 0x1000020
+ .long 5 # BTF_KIND_FUNC(id = 3)
+ .long 201326593 # 0xc000001
+ .long 1
+ .byte 0 # string offset=0
+ .ascii "int" # string offset=1
+ .byte 0
+ .ascii "test" # string offset=5
+ .byte 0
+ .ascii ".text" # string offset=10
+ .byte 0
+ .ascii "/home/yhs/ttmp/t.c" # string offset=16
+ .byte 0
+ .section .BTF.ext,"", at progbits
+ .short 60319 # 0xeb9f
+ .byte 1
+ .byte 0
+ .long 32
+ .long 0
+ .long 20
+ .long 20
+ .long 44
+ .long 64
+ .long 0
+ .long 8 # FuncInfo
+ .long 10 # FuncInfo section string offset=10
+ .long 1
+ .long .Lfunc_begin0
+ .long 3
+ .long 16 # LineInfo
+ .long 10 # LineInfo section string offset=10
+ .long 2
+ .long .Lfunc_begin0
+ .long 16
+ .long 0
+ .long 1024 # Line 1 Col 0
+ .long .Ltmp2
+ .long 16
+ .long 0
+ .long 1038 # Line 1 Col 14
+ .section .debug_line,"", at progbits
+.Lline_table_start0:
>From 91af3da8679b671fb555b9863276b84f39fb3e2f Mon Sep 17 00:00:00 2001
From: rez5427 <guanjian at stu.cdut.edu.cn>
Date: Wed, 15 Oct 2025 09:31:46 +0800
Subject: [PATCH 3/4] restore old non-autogenerated file
---
llvm/test/CodeGen/AArch64/arm64-vector-ext.ll | 23 ++---
llvm/test/CodeGen/AArch64/arm64-vshuffle.ll | 13 +--
llvm/test/CodeGen/ARM/readcyclecounter.ll | 8 +-
.../CodeGen/AVR/calling-conv/c/return_aggr.ll | 29 ++----
llvm/test/CodeGen/BPF/BTF/filename.ll | 17 ----
llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll | 19 ----
llvm/test/CodeGen/BPF/fi_ri.ll | 19 ++--
llvm/test/CodeGen/BPF/inlineasm-wreg.ll | 22 +----
llvm/test/CodeGen/BPF/rodata_1.ll | 22 ++---
llvm/test/CodeGen/BPF/rodata_2.ll | 28 +++---
llvm/test/CodeGen/Mips/readcyclecounter.ll | 13 ++-
.../CodeGen/PowerPC/2008-05-01-ppc_fp128.ll | 12 ---
.../PowerPC/2008-07-15-SignExtendInreg.ll | 9 --
llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll | 6 --
llvm/test/CodeGen/PowerPC/aix-dwarf.ll | 13 ++-
llvm/test/CodeGen/PowerPC/llc_default_cpu.ll | 76 --------------
llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll | 98 ++++++++++++++++++-
llvm/test/CodeGen/X86/vectorcall.ll | 83 +++++++++++++++-
llvm/test/DebugInfo/ARM/constant-dbgloc.ll | 3 -
llvm/test/DebugInfo/MIR/X86/regcoalescer.mir | 10 +-
llvm/test/DebugInfo/XCOFF/empty-prolog.ll | 3 +-
llvm/test/DebugInfo/XCOFF/empty.ll | 20 ----
llvm/test/DebugInfo/XCOFF/explicit-section.ll | 25 -----
.../test/DebugInfo/XCOFF/function-sections.ll | 5 +-
llvm/test/Other/machine-size-remarks.ll | 7 +-
25 files changed, 248 insertions(+), 335 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
index 91f0fbcd5c46b..197a385b0e7cb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
@@ -1,16 +1,15 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+;CHECK: @func30
+;CHECK: movi.4h v1, #1
+;CHECK: and.8b v0, v0, v1
+;CHECK: ushll.4s v0, v0, #0
+;CHECK: str q0, [x0]
+;CHECK: ret
+
%T0_30 = type <4 x i1>
%T1_30 = type <4 x i32>
define void @func30(%T0_30 %v0, ptr %p1) {
-; CHECK-LABEL: func30:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.4h v1, #1
-; CHECK-NEXT: and.8b v0, v0, v1
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
%r = zext %T0_30 %v0 to %T1_30
store %T1_30 %r, ptr %p1
ret void
@@ -19,11 +18,9 @@ define void @func30(%T0_30 %v0, ptr %p1) {
; Extend from v1i1 was crashing things (PR20791). Make sure we do something
; sensible instead.
define <1 x i32> @autogen_SD7918() {
-; CHECK-LABEL: autogen_SD7918:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.2d v0, #0000000000000000
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-LABEL: autogen_SD7918
+; CHECK: movi.2d v0, #0000000000000000
+; CHECK-NEXT: ret
%I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
%ZE = zext <1 x i1> %I29 to <1 x i32>
ret <1 x i32> %ZE
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
index fd0f2433f2c2b..b225d9a1acaf5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
@@ -1,11 +1,9 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
define <8 x i1> @test1() {
; CHECK-LABEL: test1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.16b v0, #0
-; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
@@ -60,14 +58,9 @@ bb:
; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0
define <16 x i1> @test4(ptr %ptr, i32 %v) {
-; CHECK-LABEL: test4:
-; CHECK: ; %bb.0: ; %bb
-; CHECK-NEXT: Lloh0:
-; CHECK-NEXT: adrp x8, lCPI3_0 at PAGE
-; CHECK-NEXT: Lloh1:
-; CHECK-NEXT: ldr q0, [x8, lCPI3_0 at PAGEOFF]
-; CHECK-NEXT: ret
-; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
+; CHECK-LABEL: _test4:
+; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0 at PAGE
+; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0 at PAGEOFF]
bb:
%Shuff = shufflevector <16 x i1> zeroinitializer,
<16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
diff --git a/llvm/test/CodeGen/ARM/readcyclecounter.ll b/llvm/test/CodeGen/ARM/readcyclecounter.ll
index 9a49aa63a0700..7ed49ff95deca 100644
--- a/llvm/test/CodeGen/ARM/readcyclecounter.ll
+++ b/llvm/test/CodeGen/ARM/readcyclecounter.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s
; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
@@ -18,8 +17,9 @@ define i64 @get_count() {
; As usual, exact registers only sort of matter but the cycle-count had better
; end up in r0 in the end.
+; CHECK: mrc p15, #0, r0, c9, c13, #0
+; CHECK: {{movs?}} r1, #0
+; CHECK-NO-PERFMON: {{movs?}} r0, #0
+; CHECK-NO-PERFMON: {{movs?}} r1, #0
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
-; CHECK-NO-PERFMON: {{.*}}
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
index 0945ae0e4e918..6f154a9afffae 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
@@ -1,20 +1,14 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: ret_struct_i8_i16_i8
define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
-; CHECK-LABEL: ret_struct_i8_i16_i8:
-; CHECK: ; %bb.0: ; %start
-; CHECK-NEXT: ldi r22, 64
-; CHECK-NEXT: ldi r18, 0
-; CHECK-NEXT: ldi r19, 4
-; CHECK-NEXT: ldi r25, 11
-; CHECK-NEXT: mov r23, r18
-; CHECK-NEXT: mov r24, r19
-; CHECK-NEXT: ret
start:
; for some reason the i16 is loaded to r24:r25
; and then moved to r23:r24
+ ; CHECK: ldi r22, 64
+ ; CHECK-NEXT: r23,
+ ; CHECK-NEXT: r24,
+ ; CHECK-NEXT: r25, 11
%0 = insertvalue {i8, i16, i8} undef, i8 64, 0
%1 = insertvalue {i8, i16, i8} %0, i16 1024, 1
%2 = insertvalue {i8, i16, i8} %1, i8 11, 2
@@ -23,16 +17,13 @@ start:
; CHECK-LABEL: ret_struct_i32_i16
define { i32, i16 } @ret_struct_i32_i16() {
-; CHECK-LABEL: ret_struct_i32_i16:
-; CHECK: ; %bb.0: ; %start
-; CHECK-NEXT: ldi r18, 4
-; CHECK-NEXT: ldi r19, 3
-; CHECK-NEXT: ldi r20, 2
-; CHECK-NEXT: ldi r21, 1
-; CHECK-NEXT: ldi r22, 0
-; CHECK-NEXT: ldi r23, 8
-; CHECK-NEXT: ret
start:
+ ; CHECK: ldi r18, 4
+ ; CHECK-NEXT: ldi r19, 3
+ ; CHECK-NEXT: ldi r20, 2
+ ; CHECK-NEXT: ldi r21, 1
+ ; CHECK-NEXT: ldi r22, 0
+ ; CHECK-NEXT: ldi r23, 8
%0 = insertvalue { i32, i16 } undef, i32 16909060, 0
%1 = insertvalue { i32, i16 } %0, i16 2048, 1
ret { i32, i16} %1
diff --git a/llvm/test/CodeGen/BPF/BTF/filename.ll b/llvm/test/CodeGen/BPF/BTF/filename.ll
index 022a6fb9ac974..ae08aea71b2cb 100644
--- a/llvm/test/CodeGen/BPF/BTF/filename.ll
+++ b/llvm/test/CodeGen/BPF/BTF/filename.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
; RUN: llc -mtriple=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
@@ -9,22 +8,6 @@
; Function Attrs: norecurse nounwind readnone uwtable
define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 {
-; CHECK-LABEL: test:
-; CHECK: .Ltest$local:
-; CHECK-NEXT: .type .Ltest$local, at function
-; CHECK-NEXT: .Lfunc_begin0:
-; CHECK-NEXT: .file 1 "/home/yhs/ttmp" "/home/yhs/ttmp/t.c"
-; CHECK-NEXT: .loc 1 1 0 # /home/yhs/ttmp/t.c:1:0
-; CHECK-NEXT: .cfi_startproc
-; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: w0 = 0
-; CHECK-NEXT: .Ltmp0:
-; CHECK-NEXT: .loc 1 1 14 prologue_end # /home/yhs/ttmp/t.c:1:14
-; CHECK-NEXT: .Ltmp1:
-; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: exit
-; CHECK-NEXT: .Ltmp3:
-; CHECK-NEXT: .Ltmp4:
ret i32 0, !dbg !11
}
diff --git a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
index 728e0354d33c8..f9439e606ae87 100644
--- a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
+++ b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
; RUN: llc -mtriple=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
@@ -9,24 +8,6 @@
; Function Attrs: nounwind readnone
define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 {
-; CHECK-LABEL: f1:
-; CHECK: .Lf1$local:
-; CHECK-NEXT: .type .Lf1$local, at function
-; CHECK-NEXT: .Lfunc_begin0:
-; CHECK-NEXT: .file 1 "/DNE" "t.c"
-; CHECK-NEXT: .loc 1 1 0 # t.c:1:0
-; CHECK-NEXT: .cfi_sections .debug_frame
-; CHECK-NEXT: .cfi_startproc
-; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: #DEBUG_VALUE: f1:a1 <- $w1
-; CHECK-NEXT: w0 = 0
-; CHECK-NEXT: .Ltmp0:
-; CHECK-NEXT: .loc 1 1 18 prologue_end # t.c:1:18
-; CHECK-NEXT: .Ltmp1:
-; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: exit
-; CHECK-NEXT: .Ltmp3:
-; CHECK-NEXT: .Ltmp4:
call void @llvm.dbg.value(metadata i32 %0, metadata !12, metadata !DIExpression()), !dbg !13
ret i32 0, !dbg !14
}
diff --git a/llvm/test/CodeGen/BPF/fi_ri.ll b/llvm/test/CodeGen/BPF/fi_ri.ll
index cc9943c4812bc..8d60d29b52726 100644
--- a/llvm/test/CodeGen/BPF/fi_ri.ll
+++ b/llvm/test/CodeGen/BPF/fi_ri.ll
@@ -1,24 +1,19 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpf -mcpu=v1 | FileCheck %s
%struct.key_t = type { i32, [16 x i8] }
; Function Attrs: nounwind uwtable
define i32 @test() #0 {
-; CHECK-LABEL: test:
-; CHECK: # %bb.0:
-; CHECK-NEXT: r6 = 0
-; CHECK-NEXT: *(u32 *)(r10 - 8) = r6
-; CHECK-NEXT: *(u64 *)(r10 - 16) = r6
-; CHECK-NEXT: *(u64 *)(r10 - 24) = r6
-; CHECK-NEXT: r1 = r10
-; CHECK-NEXT: r1 += -20
-; CHECK-NEXT: call test1
-; CHECK-NEXT: r0 = r6
-; CHECK-NEXT: exit
%key = alloca %struct.key_t, align 4
+; CHECK: r1 = 0
+; CHECK: *(u32 *)(r10 - 8) = r1
+; CHECK: *(u64 *)(r10 - 16) = r1
+; CHECK: *(u64 *)(r10 - 24) = r1
call void @llvm.memset.p0.i64(ptr align 4 %key, i8 0, i64 20, i1 false)
+; CHECK: r1 = r10
+; CHECK: r1 += -20
%1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
+; CHECK: call test1
call void @test1(ptr %1) #3
ret i32 0
}
diff --git a/llvm/test/CodeGen/BPF/inlineasm-wreg.ll b/llvm/test/CodeGen/BPF/inlineasm-wreg.ll
index 96008335afd6f..496a2d909cb7c 100644
--- a/llvm/test/CodeGen/BPF/inlineasm-wreg.ll
+++ b/llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -1,36 +1,18 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
; Test that %w works as input constraint
; CHECK-LABEL: test_inlineasm_w_input_constraint
define dso_local i32 @test_inlineasm_w_input_constraint() {
-; CHECK-LABEL: test_inlineasm_w_input_constraint:
-; CHECK: .Ltest_inlineasm_w_input_constraint$local:
-; CHECK-NEXT: .type .Ltest_inlineasm_w_input_constraint$local, at function
-; CHECK-NEXT: .cfi_startproc
-; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: w0 = 42
-; CHECK-NEXT: #APP
-; CHECK-NEXT: w0 = w0
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: exit
tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
ret i32 42
}
; Test that %w works as output constraint
; CHECK-LABEL: test_inlineasm_w_output_constraint
define dso_local i32 @test_inlineasm_w_output_constraint() {
-; CHECK-LABEL: test_inlineasm_w_output_constraint:
-; CHECK: .Ltest_inlineasm_w_output_constraint$local:
-; CHECK-NEXT: .type .Ltest_inlineasm_w_output_constraint$local, at function
-; CHECK-NEXT: .cfi_startproc
-; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: #APP
-; CHECK-NEXT: w0 = 42
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: exit
%1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
ret i32 %1
}
diff --git a/llvm/test/CodeGen/BPF/rodata_1.ll b/llvm/test/CodeGen/BPF/rodata_1.ll
index a6db9deeface6..26dd85caa1d21 100644
--- a/llvm/test/CodeGen/BPF/rodata_1.ll
+++ b/llvm/test/CodeGen/BPF/rodata_1.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpfel -mcpu=v1 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -verify-machineinstrs | FileCheck %s
@@ -32,24 +31,17 @@
; Function Attrs: nounwind
define i32 @test() local_unnamed_addr #0 {
; CHECK-LABEL: test:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: r1 = g1 ll
-; CHECK-NEXT: r0 = 0
-; CHECK-NEXT: *(u8 *)(r1 + 1) = r0
-; CHECK-NEXT: *(u8 *)(r1 + 0) = r0
-; CHECK-NEXT: r2 = 1
-; CHECK-NEXT: *(u8 *)(r1 + 2) = r2
-; CHECK-NEXT: r1 = g2 ll
-; CHECK-NEXT: *(u32 *)(r1 + 8) = r2
-; CHECK-NEXT: *(u32 *)(r1 + 4) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 0) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 12) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 16) = r0
-; CHECK-NEXT: exit
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr @g1, ptr @test.t1, i64 3, i1 false)
tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g2, ptr align 4 @test.t2, i64 20, i1 false)
+; CHECK: r1 = g1
+; CHECK: r2 = 0
+; CHECK: *(u8 *)(r1 + 1) = r2
+; CHECK: r3 = 1
+; CHECK: *(u8 *)(r1 + 2) = r3
+; CHECK: r1 = g2
+; CHECK: *(u32 *)(r1 + 8) = r3
ret i32 0
}
; CHECK: .section .rodata,"a", at progbits
diff --git a/llvm/test/CodeGen/BPF/rodata_2.ll b/llvm/test/CodeGen/BPF/rodata_2.ll
index c8fb758c0c698..bb7bf4ba8ace7 100644
--- a/llvm/test/CodeGen/BPF/rodata_2.ll
+++ b/llvm/test/CodeGen/BPF/rodata_2.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=bpfel -mcpu=v1 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -verify-machineinstrs | FileCheck %s
@@ -30,24 +29,21 @@
; Function Attrs: nounwind
define i32 @test() local_unnamed_addr #0 {
; CHECK-LABEL: test:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: r1 = g ll
-; CHECK-NEXT: r2 = 3
-; CHECK-NEXT: *(u32 *)(r1 + 24) = r2
-; CHECK-NEXT: r2 = 2
-; CHECK-NEXT: *(u32 *)(r1 + 20) = r2
-; CHECK-NEXT: r2 = 1
-; CHECK-NEXT: *(u32 *)(r1 + 16) = r2
-; CHECK-NEXT: r0 = 0
-; CHECK-NEXT: *(u32 *)(r1 + 28) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 12) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 8) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 4) = r0
-; CHECK-NEXT: *(u32 *)(r1 + 0) = r0
-; CHECK-NEXT: exit
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g, ptr align 4 @test.t2, i64 32, i1 false)
+; CHECK: r1 = g ll
+; CHECK: r2 = 3
+; CHECK: *(u32 *)(r1 + 24) = r2
+; CHECK: r2 = 2
+; CHECK: *(u32 *)(r1 + 20) = r2
+; CHECK: r2 = 1
+; CHECK: *(u32 *)(r1 + 16) = r2
+; CHECK: r2 = 0
+; CHECK: *(u32 *)(r1 + 28) = r2
+; CHECK: *(u32 *)(r1 + 8) = r2
+; CHECK: *(u32 *)(r1 + 4) = r2
+; CHECK: *(u32 *)(r1 + 0) = r2
ret i32 0
}
; CHECK: .section .rodata.cst32,"aM", at progbits,32
diff --git a/llvm/test/CodeGen/Mips/readcyclecounter.ll b/llvm/test/CodeGen/Mips/readcyclecounter.ll
index ff69365d11597..467dd92884b3d 100644
--- a/llvm/test/CodeGen/Mips/readcyclecounter.ll
+++ b/llvm/test/CodeGen/Mips/readcyclecounter.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
;RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 < %s | FileCheck %s --check-prefix=MIPSEL
;RUN: llc -mtriple=mips64el-linux-gnuabi64 -mcpu=mips64r2 < %s | FileCheck %s --check-prefix=MIPS64EL
;RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips2 < %s | FileCheck %s --check-prefix=MIPSEL
@@ -20,6 +19,12 @@ define i64 @test_readcyclecounter() nounwind {
; MIPSEL-NEXT: jr $ra
; MIPSEL-NEXT: addiu $3, $zero, 0
;
+; MIPSEL_NOT_SUPPORTED-LABEL: test_readcyclecounter:
+; MIPSEL_NOT_SUPPORTED: # %bb.0: # %entry
+; MIPSEL_NOT_SUPPORTED-NEXT: addiu $2, $zero, 0
+; MIPSEL_NOT_SUPPORTED-NEXT: jr $ra
+; MIPSEL_NOT_SUPPORTED-NEXT: addiu $3, $zero, 0
+;
; MIPS64EL-LABEL: test_readcyclecounter:
; MIPS64EL: # %bb.0: # %entry
; MIPS64EL-NEXT: .set push
@@ -29,12 +34,6 @@ define i64 @test_readcyclecounter() nounwind {
; MIPS64EL-NEXT: jr $ra
; MIPS64EL-NEXT: nop
;
-; MIPSEL_NOT_SUPPORTED-LABEL: test_readcyclecounter:
-; MIPSEL_NOT_SUPPORTED: # %bb.0: # %entry
-; MIPSEL_NOT_SUPPORTED-NEXT: addiu $2, $zero, 0
-; MIPSEL_NOT_SUPPORTED-NEXT: jr $ra
-; MIPSEL_NOT_SUPPORTED-NEXT: move $3, $2
-;
; MIPS64EL_NOT_SUPPORTED-LABEL: test_readcyclecounter:
; MIPS64EL_NOT_SUPPORTED: # %bb.0: # %entry
; MIPS64EL_NOT_SUPPORTED-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
index 80ec534c29199..c9eb6521c11ba 100644
--- a/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target triple = "powerpc-unknown-linux-gnu"
@@ -13,17 +12,6 @@ target triple = "powerpc-unknown-linux-gnu"
; CHECK: li 10, 0
; CHECK: blr
define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
-; CHECK-LABEL: func:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: li 5, 0
-; CHECK-NEXT: li 6, 0
-; CHECK-NEXT: li 7, 0
-; CHECK-NEXT: li 8, 0
-; CHECK-NEXT: li 9, 0
-; CHECK-NEXT: li 10, 0
-; CHECK-NEXT: blr
entry:
br i1 false, label %bb36, label %bb484
diff --git a/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
index f7eda89285952..380097f2e6d2e 100644
--- a/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-unknown-linux-gnu"
@@ -10,14 +9,6 @@ target triple = "powerpc-unknown-linux-gnu"
; CHECK: sth 5
; CHECK: blr
define signext i16 @t(ptr %dct) nounwind {
-; CHECK-LABEL: t:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mr 4, 3
-; CHECK-NEXT: lbz 3, 1(0)
-; CHECK-NEXT: extsb 5, 3
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: sth 5, 0(4)
-; CHECK-NEXT: blr
entry:
load i16, ptr null, align 2 ; <i16>:0 [#uses=2]
lshr i16 %0, 11 ; <i16>:1 [#uses=0]
diff --git a/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
index f99eda5b017f9..966fb52089716 100644
--- a/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-unknown-linux-gnu"
@@ -8,11 +7,6 @@ target triple = "powerpc-unknown-linux-gnu"
; CHECK: li 4, 0
; CHECK: blr
define hidden i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: __fixunstfdi:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: blr
entry:
br i1 false, label %bb3, label %bb4
diff --git a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
index 180ff9ed1fd93..a14ef4f93c701 100644
--- a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefixes=SEC,SEC32
@@ -127,18 +126,18 @@ entry:
; RELO-NEXT: OFFSET TYPE VALUE
; RELO-NEXT: 00000006 R_POS .dwabrev
; RELO-NEXT: 00000027 R_POS .dwline
-; RELO-NEXT: 00000009 R_POS
-; RELO-NEXT: 0000003a R_POS
+; RELO-NEXT: 00000009 R_POS
+; RELO-NEXT: 0000003a R_POS
; RELO: RELOCATION RECORDS FOR [.dwline]:
; RELO-NEXT: OFFSET TYPE VALUE
-; RELO-NEXT: 00000000 R_POS
+; RELO-NEXT: 00000000 R_POS
; RELO64: RELOCATION RECORDS FOR [.dwinfo]:
; RELO64-NEXT: OFFSET TYPE VALUE
; RELO64-NEXT: 000000000000000e R_POS .dwabrev
; RELO64-NEXT: 000000000000000b R_POS .dwline
-; RELO64-NEXT: 0000000000000041 R_POS
-; RELO64-NEXT: 000000000000004e R_POS
+; RELO64-NEXT: 0000000000000041 R_POS
+; RELO64-NEXT: 000000000000004e R_POS
; RELO64: RELOCATION RECORDS FOR [.dwline]:
; RELO64-NEXT: OFFSET TYPE VALUE
-; RELO64-NEXT: 000000000000000c R_POS
+; RELO64-NEXT: 000000000000000c R_POS
diff --git a/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll b/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll
index 368e3896c2595..21d880ec47534 100644
--- a/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll
+++ b/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Test that the default CPU for the triple powerpc64-unknown-linux-gnu is ppc64.
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -frame-pointer=all -mcpu=ppc | FileCheck %s -check-prefixes=LNX-PPC,LNX-COM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -frame-pointer=all | FileCheck %s -check-prefixes=LNX-PPC64,LNX-COM
@@ -14,77 +13,6 @@
; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s -check-prefixes=AIX64-PWR7,AIX64-COM-NEXT
define i32 @main() {
-; LNX-PPC-LABEL: main:
-; LNX-PPC: # %bb.0: # %entry
-; LNX-PPC-NEXT: lis 0, -1
-; LNX-PPC-NEXT: ori 0, 0, 32704
-; LNX-PPC-NEXT: std 31, -8(1)
-; LNX-PPC-NEXT: stdux 1, 1, 0
-; LNX-PPC-NEXT: .cfi_def_cfa_offset 32832
-; LNX-PPC-NEXT: .cfi_offset r31, -8
-; LNX-PPC-NEXT: mr 31, 1
-; LNX-PPC-NEXT: .cfi_def_cfa_register r31
-; LNX-PPC-NEXT: li 3, 0
-; LNX-PPC-NEXT: stw 3, 60(31)
-; LNX-PPC-NEXT: ld 1, 0(1)
-; LNX-PPC-NEXT: ld 31, -8(1)
-; LNX-PPC-NEXT: blr
-;
-; LNX-PPC64-LABEL: main:
-; LNX-PPC64: # %bb.0: # %entry
-; LNX-PPC64-NEXT: lis 0, -1
-; LNX-PPC64-NEXT: std 31, -8(1)
-; LNX-PPC64-NEXT: ori 0, 0, 32704
-; LNX-PPC64-NEXT: stdux 1, 1, 0
-; LNX-PPC64-NEXT: .cfi_def_cfa_offset 32832
-; LNX-PPC64-NEXT: .cfi_offset r31, -8
-; LNX-PPC64-NEXT: mr 31, 1
-; LNX-PPC64-NEXT: .cfi_def_cfa_register r31
-; LNX-PPC64-NEXT: li 3, 0
-; LNX-PPC64-NEXT: stw 3, 60(31)
-; LNX-PPC64-NEXT: ld 1, 0(1)
-; LNX-PPC64-NEXT: ld 31, -8(1)
-; LNX-PPC64-NEXT: blr
-;
-; AIX-PPC-LABEL: main:
-; AIX-PPC: # %bb.0: # %entry
-; AIX-PPC-NEXT: lis 0, -1
-; AIX-PPC-NEXT: ori 0, 0, 32736
-; AIX-PPC-NEXT: stwux 1, 1, 0
-; AIX-PPC-NEXT: li 3, 0
-; AIX-PPC-NEXT: stw 3, 36(1)
-; AIX-PPC-NEXT: lwz 1, 0(1)
-; AIX-PPC-NEXT: blr
-;
-; AIX-PWR7-LABEL: main:
-; AIX-PWR7: # %bb.0: # %entry
-; AIX-PWR7-NEXT: lis 0, -1
-; AIX-PWR7-NEXT: ori 0, 0, 32736
-; AIX-PWR7-NEXT: stwux 1, 1, 0
-; AIX-PWR7-NEXT: li 3, 0
-; AIX-PWR7-NEXT: stw 3, 36(1)
-; AIX-PWR7-NEXT: lwz 1, 0(1)
-; AIX-PWR7-NEXT: blr
-;
-; AIX64-PPC-LABEL: main:
-; AIX64-PPC: # %bb.0: # %entry
-; AIX64-PPC-NEXT: lis 0, -1
-; AIX64-PPC-NEXT: ori 0, 0, 32720
-; AIX64-PPC-NEXT: stdux 1, 1, 0
-; AIX64-PPC-NEXT: li 3, 0
-; AIX64-PPC-NEXT: stw 3, 52(1)
-; AIX64-PPC-NEXT: ld 1, 0(1)
-; AIX64-PPC-NEXT: blr
-;
-; AIX64-PWR7-LABEL: main:
-; AIX64-PWR7: # %bb.0: # %entry
-; AIX64-PWR7-NEXT: lis 0, -1
-; AIX64-PWR7-NEXT: ori 0, 0, 32720
-; AIX64-PWR7-NEXT: stdux 1, 1, 0
-; AIX64-PWR7-NEXT: li 3, 0
-; AIX64-PWR7-NEXT: stw 3, 52(1)
-; AIX64-PWR7-NEXT: ld 1, 0(1)
-; AIX64-PWR7-NEXT: blr
entry:
%retval = alloca i32, i32 8191, align 4
store i32 0, ptr %retval, align 4
@@ -137,7 +65,3 @@ entry:
; AIX64-PWR7-NEXT: stw 3, 52(1)
; AIX64-COM-NEXT: ld 1, 0(1)
; AIX64-COM-NEXT: blr
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; AIX-COM: {{.*}}
-; AIX64-COM-NEXT: {{.*}}
-; LNX-COM: {{.*}}
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index 1a83305c096da..a95f68b5e118d 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple s390x-ibm-zos | FileCheck %s
; Source to regenerate:
; struct Foo {
@@ -104,6 +103,9 @@ declare void @use_foo(ptr)
define void @ptr32_to_ptr(ptr %f, ptr addrspace(1) %i) {
entry:
+; CHECK-LABEL: ptr32_to_ptr:
+; CHECK: llgtr 0,2
+; CHECK-NEXT: stg 0,8(1)
%0 = addrspacecast ptr addrspace(1) %i to ptr
%p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
store ptr %0, ptr %p64, align 8
@@ -113,6 +115,9 @@ entry:
define void @ptr_to_ptr32(ptr %f, ptr %i) {
entry:
+; CHECK-LABEL: ptr_to_ptr32:
+; CHECK: nilh 2,32767
+; CHECK-NEXT: st 2,0(1)
%0 = addrspacecast ptr %i to ptr addrspace(1)
%p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
store ptr addrspace(1) %0, ptr %p32, align 8
@@ -122,6 +127,8 @@ entry:
define void @ptr32_to_ptr32(ptr %f, ptr addrspace(1) %i) {
entry:
+; CHECK-LABEL: ptr32_to_ptr32:
+; CHECK: st 2,0(1)
%p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
store ptr addrspace(1) %i, ptr %p32, align 8
tail call void @use_foo(ptr %f)
@@ -129,6 +136,8 @@ entry:
}
define void @ptr_to_ptr(ptr %f, ptr %i) {
+; CHECK-LABEL: ptr_to_ptr:
+; CHECK: stg 2,8(1)
%p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
store ptr %i, ptr %p64, align 8
tail call void @use_foo(ptr %f)
@@ -137,6 +146,10 @@ define void @ptr_to_ptr(ptr %f, ptr %i) {
define void @test_indexing(ptr %f) {
entry:
+; CHECK-LABEL: test_indexing:
+; CHECK: l 0,1032
+; CHECK: llgtr 0,0
+; CHECK: stg 0,16(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1032 to ptr), align 8
%1 = addrspacecast ptr addrspace(1) %0 to ptr
%cp64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 2
@@ -147,6 +160,12 @@ entry:
define void @test_indexing_2(ptr %f) {
entry:
+; CHECK-LABEL: test_indexing_2:
+; CHECK: lhi 0,16
+; CHECK-NEXT: a 0,1032
+; CHECK-NEXT: llgtr 2,0
+; CHECK: lg 0,24(2)
+; CHECK: stg 0,16(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1032 to ptr), align 8
%arrayidx = getelementptr inbounds ptr, ptr addrspace(1) %0, i32 2
%1 = load ptr, ptr addrspace(1) %arrayidx, align 8
@@ -162,6 +181,14 @@ entry:
define ptr @test_misc() {
entry:
+; CHECK-LABEL: test_misc:
+; CHECK: lhi 0,88
+; CHECK-NEXT: a 0,1208
+; CHECK-NEXT: llgtr 1,0
+; CHECK-NEXT: lg 1,0(1)
+; CHECK-NEXT: lg 1,8(1)
+; CHECK-NEXT: lg 1,904(1)
+; CHECK-NEXT: lg 3,1192(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1208 to ptr), align 8
%arrayidx = getelementptr inbounds ptr, ptr addrspace(1) %0, i32 11
%1 = load ptr, ptr addrspace(1) %arrayidx, align 8
@@ -177,6 +204,13 @@ entry:
define ptr addrspace(1) @test_misc_2() {
entry:
+; CHECK-LABEL: test_misc_2:
+; CHECK: lhi 0,544
+; CHECK: a 0,16
+; CHECK: llgtr 1,0
+; CHECK: lhi 0,24
+; CHECK: a 0,0(1)
+; CHECK: llgtr 1,0
%0 = load ptr addrspace(1), ptr inttoptr (i64 16 to ptr), align 16
%arrayidx = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) %0, i32 136
%1 = load ptr addrspace(1), ptr addrspace(1) %arrayidx, align 4
@@ -187,6 +221,11 @@ entry:
define zeroext i16 @test_misc_3() {
entry:
+; CHECK-LABEL: test_misc_3:
+; CHECK: a 0,548
+; CHECK-NEXT: llgtr 1,0
+; CHECK-NEXT: llgh 3,0(1)
+; CHECK-NEXT: b 2(7)
%0 = load ptr addrspace(1), ptr inttoptr (i64 548 to ptr), align 4
%arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %0, i32 18
%arrayidx = addrspacecast ptr addrspace(1) %arrayidx2 to ptr
@@ -196,6 +235,15 @@ entry:
define signext i32 @test_misc_4() {
entry:
+; CHECK-LABEL: test_misc_4:
+; CHECK: lhi 0,88
+; CHECK-NEXT: a 0,1208
+; CHECK-NEXT: llgtr 1,0
+; CHECK-NEXT: lg 1,0(1)
+; CHECK-NEXT: lg 1,8(1)
+; CHECK-NEXT: lg 1,984(1)
+; CHECK-NEXT: iilf 0,67240703
+; CHECK-NEXT: c 0,80(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 1208 to ptr), align 8
%arrayidx = getelementptr inbounds ptr, ptr addrspace(1) %0, i32 11
%1 = load ptr, ptr addrspace(1) %arrayidx, align 8
@@ -213,6 +261,12 @@ entry:
define void @test_misc_5(ptr %f) {
entry:
+; CHECK-LABEL: test_misc_5:
+; CHECK: l 0,548
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: llgtr 0,0
+; CHECK-NEXT: stg 0,16(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 548 to ptr), align 4
%1 = addrspacecast ptr addrspace(1) %0 to ptr
%cp64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 2
@@ -223,6 +277,14 @@ entry:
define signext i32 @get_processor_count() {
entry:
+; CHECK-LABEL: get_processor_count:
+; CHECK: lhi 0,660
+; CHECK-NEXT: a 0,16
+; CHECK-NEXT: llgtr 1,0
+; CHECK-NEXT: lhi 0,53
+; CHECK-NEXT: a 0,0(1)
+; CHECK-NEXT: llgtr 1,0
+; CHECK-NEXT: lgb 3,0(1)
%0 = load ptr addrspace(1), ptr inttoptr (i64 16 to ptr), align 16
%arrayidx = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) %0, i32 165
%1 = load ptr addrspace(1), ptr addrspace(1) %arrayidx, align 4
@@ -234,6 +296,22 @@ entry:
define void @spill_ptr32_args_to_registers(i8 addrspace(1)* %p) {
entry:
+; CHECK-LABEL: spill_ptr32_args_to_registers:
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: lgr 2,1
+; CHECK-NEXT: lg 6,24(5)
+; CHECK-NEXT: lg 5,16(5)
+; CHECK-NEXT: stg 1,2216(4)
+; CHECK-NEXT: stg 1,2208(4)
+; CHECK-NEXT: lghi 1,5
+; CHECK-NEXT: stg 2,2200(4)
+; CHECK-NEXT: lgr 3,2
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
+; CHECK-NEXT: b 2(7)
tail call void (i32, ...) @g(i32 noundef signext 5, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p, ptr addrspace(1) noundef %p)
ret void
}
@@ -249,6 +327,14 @@ declare void @g(i32 signext, ...)
; cast to __ptr32, setting the upper 32 bit to zero.
;
define signext i32 @setlength() {
+; CHECK-LABEL: setlength:
+; CHECK: basr 7,6
+; CHECK: lgr [[MALLOC:[0-9]+]],3
+; CHECK: basr 7,6
+; CHECK: lgr [[LENGTH:[0-9]+]],3
+; CHECK: la [[ADDR:[0-9]+]],4([[MALLOC]])
+; CHECK: llgtr [[ADDR]],[[ADDR]]
+; CHECK: stg [[LENGTH]],0([[ADDR]])
entry:
%call = tail call ptr @__malloc31(i64 noundef 8)
%call1 = tail call signext i32 @foo()
@@ -265,6 +351,14 @@ entry:
; the function now returns a __ptr32.
;
define signext i32 @setlength2() {
+; CHECK-LABEL: setlength2:
+; CHECK: basr 7,6
+; CHECK: lgr [[MALLOC:[0-9]+]],3
+; CHECK: basr 7,6
+; CHECK: lgr [[LENGTH:[0-9]+]],3
+; CHECK: ahi [[MALLOC]],4
+; CHECK: llgtr [[ADDR]],[[MALLOC]]
+; CHECK: stg [[LENGTH]],0([[ADDR]])
entry:
%call = tail call ptr addrspace(1) @domalloc(i64 noundef 8)
%call1 = tail call signext i32 @foo()
@@ -279,5 +373,3 @@ declare ptr @__malloc31(i64)
declare signext i32 @foo(...)
declare ptr addrspace(1) @domalloc(i64)
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/X86/vectorcall.ll b/llvm/test/CodeGen/X86/vectorcall.ll
index 07d906ce9960e..07446c6a7bfa4 100644
--- a/llvm/test/CodeGen/X86/vectorcall.ll
+++ b/llvm/test/CodeGen/X86/vectorcall.ll
@@ -1,23 +1,35 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=i686-pc-win32 -mattr=+sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=X86
; RUN: llc -mtriple=x86_64-pc-win32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=X64
; Test integer arguments.
define x86_vectorcallcc i32 @test_int_1() {
+; CHECK-LABEL: {{^}}test_int_1@@0:
+; CHECK: xorl %eax, %eax
ret i32 0
}
define x86_vectorcallcc i32 @test_int_2(i32 inreg %a) {
+; X86-LABEL: {{^}}test_int_2@@4:
+; X64-LABEL: {{^}}test_int_2@@8:
+; CHECK: movl %ecx, %eax
ret i32 %a
}
define x86_vectorcallcc i32 @test_int_3(i64 inreg %a) {
+; X86-LABEL: {{^}}test_int_3@@8:
+; X64-LABEL: {{^}}test_int_3@@8:
+; X86: movl %ecx, %eax
+; X64: movq %rcx, %rax
%at = trunc i64 %a to i32
ret i32 %at
}
define x86_vectorcallcc i32 @test_int_4(i32 inreg %a, i32 inreg %b) {
+; X86-LABEL: {{^}}test_int_4@@8:
+; X86: leal (%ecx,%edx), %eax
+; X64-LABEL: {{^}}test_int_4@@16:
+; X64: leal (%rcx,%rdx), %eax
%s = add i32 %a, %b
ret i32 %s
}
@@ -28,14 +40,23 @@ define x86_vectorcallcc i32 @"\01test_int_5"(i32, i32) {
}
define x86_vectorcallcc double @test_fp_1(double %a, double %b) {
+; CHECK-LABEL: {{^}}test_fp_1@@16:
+; CHECK: movaps %xmm1, %xmm0
ret double %b
}
define x86_vectorcallcc double @test_fp_2(double, double, double, double, double, double, double %r) {
+; CHECK-LABEL: {{^}}test_fp_2@@56:
+; CHECK: movsd {{[0-9]+\(%[re]sp\)}}, %xmm0
ret double %r
}
define x86_vectorcallcc {double, double, double, double} @test_fp_3() {
+; CHECK-LABEL: {{^}}test_fp_3@@0:
+; CHECK: xorps %xmm0
+; CHECK: xorps %xmm1
+; CHECK: xorps %xmm2
+; CHECK: xorps %xmm3
ret {double, double, double, double}
{ double 0.0, double 0.0, double 0.0, double 0.0 }
}
@@ -43,15 +64,26 @@ define x86_vectorcallcc {double, double, double, double} @test_fp_3() {
; FIXME: Returning via x87 isn't compatible, but its hard to structure the
; tablegen any other way.
define x86_vectorcallcc {double, double, double, double, double} @test_fp_4() {
+; CHECK-LABEL: {{^}}test_fp_4@@0:
+; CHECK: fldz
+; CHECK: xorps %xmm0
+; CHECK: xorps %xmm1
+; CHECK: xorps %xmm2
+; CHECK: xorps %xmm3
ret {double, double, double, double, double}
{ double 0.0, double 0.0, double 0.0, double 0.0, double 0.0 }
}
define x86_vectorcallcc <16 x i8> @test_vec_1(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: {{^}}test_vec_1@@32:
+; CHECK: movaps %xmm1, %xmm0
ret <16 x i8> %b
}
define x86_vectorcallcc <16 x i8> @test_vec_2(double, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> %r) {
+; CHECK-LABEL: {{^}}test_vec_2@@104:
+; X64: movq {{[0-9]*}}(%rsp), %rax
+; CHECK: movaps (%{{rax|ecx}}), %xmm0
ret <16 x i8> %r
}
@@ -61,6 +93,10 @@ define x86_vectorcallcc <16 x i8> @test_vec_2(double, <16 x i8>, <16 x i8>, <16
%struct.HVA2 = type { <4 x float>, <4 x float> }
define x86_vectorcallcc <4 x float> @test_mixed_1(i32 %a, %struct.HVA4 inreg %bb, i32 %c) {
+; CHECK-LABEL: test_mixed_1
+; CHECK: movaps %xmm1, 16(%{{(e|r)}}sp)
+; CHECK: movaps %xmm1, %xmm0
+; CHECK: ret{{q|l}}
entry:
%b = alloca %struct.HVA4, align 16
store %struct.HVA4 %bb, ptr %b, align 16
@@ -70,6 +106,10 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_2(%struct.HVA4 inreg %a, ptr %b, <4 x float> %c) {
+; CHECK-LABEL: test_mixed_2
+; X86: movaps %xmm0, (%esp)
+; X64: movaps %xmm2, %xmm0
+; CHECK: ret{{[ql]}}
entry:
%c.addr = alloca <4 x float>, align 16
store <4 x float> %c, ptr %c.addr, align 16
@@ -78,12 +118,19 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_3(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, ptr %f) {
+; CHECK-LABEL: test_mixed_3
+; CHECK: movaps (%{{[re][ac]}}x), %xmm0
+; CHECK: ret{{[ql]}}
entry:
%0 = load <4 x float>, ptr %f, align 16
ret <4 x float> %0
}
define x86_vectorcallcc <4 x float> @test_mixed_4(%struct.HVA4 inreg %a, ptr %bb, <4 x float> %c) {
+; CHECK-LABEL: test_mixed_4
+; X86: movaps 16(%eax), %xmm0
+; X64: movaps 16(%rdx), %xmm0
+; CHECK: ret{{[ql]}}
entry:
%y4 = getelementptr inbounds %struct.HVA2, ptr %bb, i32 0, i32 1
%0 = load <4 x float>, ptr %y4, align 16
@@ -91,6 +138,10 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_5(%struct.HVA3 inreg %a, ptr %b, <4 x float> %c, %struct.HVA2 inreg %dd) {
+; CHECK-LABEL: test_mixed_5
+; CHECK-DAG: movaps %xmm{{[0,5]}}, 16(%{{(e|r)}}sp)
+; CHECK-DAG: movaps %xmm5, %xmm0
+; CHECK: ret{{[ql]}}
entry:
%d = alloca %struct.HVA2, align 16
store %struct.HVA2 %dd, ptr %d, align 16
@@ -100,6 +151,12 @@ entry:
}
define x86_vectorcallcc %struct.HVA4 @test_mixed_6(%struct.HVA4 inreg %a, ptr %b) {
+; CHECK-LABEL: test_mixed_6
+; CHECK: movaps (%{{[re]}}sp), %xmm0
+; CHECK: movaps 16(%{{[re]}}sp), %xmm1
+; CHECK: movaps 32(%{{[re]}}sp), %xmm2
+; CHECK: movaps 48(%{{[re]}}sp), %xmm3
+; CHECK: ret{{[ql]}}
entry:
%retval = alloca %struct.HVA4, align 16
call void @llvm.memcpy.p0.p0.i32(ptr align 16 %retval, ptr align 16 %b, i32 64, i1 false)
@@ -112,6 +169,14 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado
declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1)
define x86_vectorcallcc void @test_mixed_7(ptr noalias sret(%struct.HVA5) %agg.result) {
+; CHECK-LABEL: test_mixed_7@@0
+; X64: mov{{[ql]}} %rcx, %rax
+; CHECK: movaps %xmm{{[0-9]}}, 64(%{{rcx|eax}})
+; CHECK: movaps %xmm{{[0-9]}}, 48(%{{rcx|eax}})
+; CHECK: movaps %xmm{{[0-9]}}, 32(%{{rcx|eax}})
+; CHECK: movaps %xmm{{[0-9]}}, 16(%{{rcx|eax}})
+; CHECK: movaps %xmm{{[0-9]}}, (%{{rcx|eax}})
+; CHECK: ret{{[ql]}}
entry:
%a = alloca %struct.HVA5, align 16
call void @llvm.memset.p0.i64(ptr align 16 %a, i8 0, i64 80, i1 false)
@@ -120,6 +185,10 @@ entry:
}
define x86_vectorcallcc <4 x float> @test_mixed_8(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, i32 %e, <4 x float> %f) {
+; CHECK-LABEL: test_mixed_8
+; X86: movaps %xmm4, %xmm0
+; X64: movaps %xmm5, %xmm0
+; CHECK: ret{{[ql]}}
entry:
%f.addr = alloca <4 x float>, align 16
store <4 x float> %f, ptr %f.addr, align 16
@@ -131,13 +200,17 @@ entry:
declare x86_vectorcallcc double @test_mixed_9_callee(%struct.HFA4 %x, double %y)
define x86_vectorcallcc double @test_mixed_9_caller(%struct.HFA4 inreg %b) {
+; CHECK-LABEL: test_mixed_9_caller
+; CHECK: movaps %xmm3, %xmm4
+; CHECK: movaps %xmm2, %xmm3
+; CHECK: movaps %xmm1, %xmm2
; X32: movasd %xmm0, %xmm1
+; X64: movap{{d|s}} %xmm5, %xmm1
+; CHECK: call{{l|q}} test_mixed_9_callee@@40
+; CHECK: addsd {{.*}}, %xmm0
+; CHECK: ret{{l|q}}
entry:
%call = call x86_vectorcallcc double @test_mixed_9_callee(%struct.HFA4 inreg %b, double 3.000000e+00)
%add = fadd double 1.000000e+00, %call
ret double %add
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
-; X64: {{.*}}
-; X86: {{.*}}
diff --git a/llvm/test/DebugInfo/ARM/constant-dbgloc.ll b/llvm/test/DebugInfo/ARM/constant-dbgloc.ll
index 721e20d06e810..c3b65ff6e19d5 100644
--- a/llvm/test/DebugInfo/ARM/constant-dbgloc.ll
+++ b/llvm/test/DebugInfo/ARM/constant-dbgloc.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -filetype=asm %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -35,5 +34,3 @@ entry:
!9 = !{i32 2, !"Debug Info Version", i32 3}
!10 = !{i32 1, !"wchar_size", i32 4}
!11 = !DILocation(line: 4, column: 5, scope: !4)
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
index e008125f94bba..30c3bd27b0a2a 100644
--- a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
+++ b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
@@ -1,4 +1,3 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -start-before=register-coalescer -stop-after=register-coalescer | FileCheck %s
--- |
@@ -41,11 +40,6 @@ registers:
- { id: 0, class: gr32, preferred-register: '' }
body: |
bb.0.entry:
- ; CHECK-LABEL: name: main
- ; CHECK: $eax = MOV32r0 implicit-def dead $eflags, debug-location !DILocation(line: 16, column: 3, scope: <0x612fb4e96a00>)
- ; CHECK-NEXT: DBG_VALUE $eax, $noreg, <0x612fb4e97f18>, !DIExpression(), debug-location !DILocation(line: 16, column: 3, scope: <0x612fb4e96a00>)
- ; CHECK-NEXT: DBG_VALUE $eax, $noreg, <0x612fb4e98528>, !DIExpression(), debug-location !DILocation(line: 13, column: 7, scope: <0x612fb4e96a00>)
- ; CHECK-NEXT: RET 0, killed $eax, debug-location !DILocation(line: 16, column: 3, scope: <0x612fb4e96a00>)
%0 = MOV32r0 implicit-def dead $eflags, debug-location !20
DBG_VALUE %0, _, !18, !DIExpression(), debug-location !21
DBG_VALUE %0, _, !19, !DIExpression(), debug-location !22
@@ -53,3 +47,7 @@ body: |
RET 0, killed $eax, debug-location !22
...
+
+# CHECK: $eax = MOV32r0
+# CHECK-NEXT: DBG_VALUE $eax
+# CHECK-NEXT: DBG_VALUE $eax
diff --git a/llvm/test/DebugInfo/XCOFF/empty-prolog.ll b/llvm/test/DebugInfo/XCOFF/empty-prolog.ll
index d5111d76c4d20..78e90cc5ffcf7 100644
--- a/llvm/test/DebugInfo/XCOFF/empty-prolog.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty-prolog.ll
@@ -1,6 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t %s
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t %s
; RUN: llvm-dwarfdump -debug-line %t | FileCheck %s
; CHECK: Address Line Column File ISA Discriminator OpIndex Flags
diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll
index d8853eb326a4c..af2f74fb82b8f 100644
--- a/llvm/test/DebugInfo/XCOFF/empty.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s --check-prefix=ASM32
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc64-ibm-aix-xcoff < %s | \
@@ -11,25 +10,6 @@ target datalayout = "E-m:a-p:32:32-i64:64-n32"
; Function Attrs: noinline nounwind optnone
define i32 @main() #0 !dbg !8 {
-; ASM32-LABEL: main:
-; ASM32: # %bb.0: # %entry
-; ASM32-NEXT: L..tmp0:
-; ASM32-NEXT: li 3, 0
-; ASM32-NEXT: stw 3, -4(1)
-; ASM32-NEXT: L..tmp1:
-; ASM32-NEXT: L..tmp2:
-; ASM32-NEXT: blr
-; ASM32-NEXT: L..tmp3:
-;
-; ASM64-LABEL: main:
-; ASM64: # %bb.0: # %entry
-; ASM64-NEXT: L..tmp0:
-; ASM64-NEXT: li 3, 0
-; ASM64-NEXT: stw 3, -4(1)
-; ASM64-NEXT: L..tmp1:
-; ASM64-NEXT: L..tmp2:
-; ASM64-NEXT: blr
-; ASM64-NEXT: L..tmp3:
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
diff --git a/llvm/test/DebugInfo/XCOFF/explicit-section.ll b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
index 3f591fa708076..0ae9289c08df3 100644
--- a/llvm/test/DebugInfo/XCOFF/explicit-section.ll
+++ b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s
@@ -8,36 +7,12 @@ target datalayout = "E-m:a-p:32:32-i64:64-n32"
; Function Attrs: noinline nounwind optnone
define i32 @bar() #0 !dbg !8 {
-; CHECK-LABEL: bar:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: L..tmp0:
-; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: blr
-; CHECK-NEXT: L..tmp1:
entry:
ret i32 1, !dbg !13
}
; Function Attrs: noinline nounwind optnone
define i32 @main() #0 section "explicit_main_sec" !dbg !14 {
-; CHECK-LABEL: main:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: L..tmp2:
-; CHECK-NEXT: mflr 0
-; CHECK-NEXT: stwu 1, -64(1)
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: stw 0, 72(1)
-; CHECK-NEXT: stw 3, 60(1)
-; CHECK-NEXT: L..tmp3:
-; CHECK-NEXT: L..tmp4:
-; CHECK-NEXT: bl .bar
-; CHECK-NEXT: nop
-; CHECK-NEXT: L..tmp5:
-; CHECK-NEXT: addi 1, 1, 64
-; CHECK-NEXT: lwz 0, 8(1)
-; CHECK-NEXT: mtlr 0
-; CHECK-NEXT: blr
-; CHECK-NEXT: L..tmp6:
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
diff --git a/llvm/test/DebugInfo/XCOFF/function-sections.ll b/llvm/test/DebugInfo/XCOFF/function-sections.ll
index bea47b77ca440..6a86ae6796fbc 100644
--- a/llvm/test/DebugInfo/XCOFF/function-sections.ll
+++ b/llvm/test/DebugInfo/XCOFF/function-sections.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -debugger-tune=gdb -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff -function-sections \
; RUN: < %s | FileCheck %s
@@ -279,7 +278,7 @@ entry:
; CHECK-NEXT: .byte 20 # Start sequence
; CHECK-NEXT: .byte 0 # Set address to L..func_end0
; CHECK-NEXT: .byte 5
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 2
; CHECK-NEXT: .vbyte 4, L..func_end0
; CHECK-NEXT: .byte 0 # End sequence
; CHECK-NEXT: .byte 1
@@ -300,5 +299,3 @@ entry:
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 1
; CHECK-NEXT: L..debug_line_end0:
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/Other/machine-size-remarks.ll b/llvm/test/Other/machine-size-remarks.ll
index 20c7a21c6c0e4..90d081ea8a60c 100644
--- a/llvm/test/Other/machine-size-remarks.ll
+++ b/llvm/test/Other/machine-size-remarks.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; REQUIRES: x86-registered-target
; RUN: llc -mtriple x86_64-apple-darwin %s -pass-remarks-analysis='size-info'\
; RUN: -pass-remarks-output=%t.yaml -o /dev/null < %s 2> %t; \
@@ -16,7 +15,7 @@
; CHECK: remark: <unknown>:0:0: X86 DAG->DAG Instruction Selection: Function:
; CHECK-SAME: main: MI Instruction count changed from 0
; CHECK-SAME: to [[INIT:[1-9][0-9]*]]; Delta: [[INIT]]
-; CHECK-NEXT: remark: <unknown>:0:0: Virtual Register Rewriter: Function: main:
+; CHECK-NEXT: remark: <unknown>:0:0: Register Coalescer: Function: main:
; CHECK-SAME: MI Instruction count changed from [[INIT]] to
; CHECK-SAME: [[FINAL:[1-9][0-9]*]];
; CHECK-SAME: Delta: [[DELTA:-?[1-9][0-9]*]]
@@ -40,7 +39,7 @@
; CHECK-NEXT: Name: FunctionMISizeChange
; CHECK-NEXT: Function: main
; CHECK-NEXT: Args:
-; CHECK-NEXT: - Pass: Virtual Register Rewriter
+; CHECK-NEXT: - Pass: Register Coalescer
; CHECK-NEXT: - String: ': Function: '
; CHECK-NEXT: - Function: main
; CHECK-NEXT: - String: ': '
@@ -58,5 +57,3 @@ entry:
}
attributes #0 = { noinline nounwind optnone ssp uwtable }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
>From a87843021495973283fea4212ffdf03a3c8793ee Mon Sep 17 00:00:00 2001
From: rez5427 <guanjian at stu.cdut.edu.cn>
Date: Wed, 15 Oct 2025 10:31:01 +0800
Subject: [PATCH 4/4] update tests
---
llvm/test/CodeGen/AArch64/arm64-vector-ext.ll | 1 +
llvm/test/CodeGen/AArch64/arm64-vshuffle.ll | 1 +
.../CodeGen/AVR/calling-conv/c/return_aggr.ll | 6 +-
llvm/test/CodeGen/BPF/BTF/filename.ll | 10 +-
llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll | 10 +-
.../CORE/intrinsic-fieldinfo-existence-4.ll | 7 +-
llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s | 18 --
llvm/test/CodeGen/BPF/fi_ri.ll | 8 +-
llvm/test/CodeGen/BPF/rodata_1.ll | 14 +-
llvm/test/CodeGen/BPF/rodata_2.ll | 10 +-
temp | 178 ------------------
11 files changed, 41 insertions(+), 222 deletions(-)
delete mode 100644 llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s
delete mode 100644 temp
diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
index 197a385b0e7cb..b462fe99cbf64 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll
@@ -20,6 +20,7 @@ define void @func30(%T0_30 %v0, ptr %p1) {
define <1 x i32> @autogen_SD7918() {
; CHECK-LABEL: autogen_SD7918
; CHECK: movi.2d v0, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
%ZE = zext <1 x i1> %I29 to <1 x i32>
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
index b225d9a1acaf5..86cf62304cc1c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
@@ -4,6 +4,7 @@ define <8 x i1> @test1() {
; CHECK-LABEL: test1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.16b v0, #0
+; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
index 6f154a9afffae..3065b4f46d476 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
@@ -6,9 +6,9 @@ start:
; for some reason the i16 is loaded to r24:r25
; and then moved to r23:r24
; CHECK: ldi r22, 64
- ; CHECK-NEXT: r23,
- ; CHECK-NEXT: r24,
- ; CHECK-NEXT: r25, 11
+ ; CHECK-NEXT: ldi r18, 0
+ ; CHECK-NEXT: ldi r19, 4
+ ; CHECK-NEXT: ldi r25, 11
%0 = insertvalue {i8, i16, i8} undef, i8 64, 0
%1 = insertvalue {i8, i16, i8} %0, i16 1024, 1
%2 = insertvalue {i8, i16, i8} %1, i8 11, 2
diff --git a/llvm/test/CodeGen/BPF/BTF/filename.ll b/llvm/test/CodeGen/BPF/BTF/filename.ll
index ae08aea71b2cb..1d8f7ce6bf4b3 100644
--- a/llvm/test/CodeGen/BPF/BTF/filename.ll
+++ b/llvm/test/CodeGen/BPF/BTF/filename.ll
@@ -47,8 +47,8 @@ define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 {
; CHECK-NEXT: .long 0
; CHECK-NEXT: .long 20
; CHECK-NEXT: .long 20
-; CHECK-NEXT: .long 28
-; CHECK-NEXT: .long 48
+; CHECK-NEXT: .long 44
+; CHECK-NEXT: .long 64
; CHECK-NEXT: .long 0
; CHECK-NEXT: .long 8 # FuncInfo
; CHECK-NEXT: .long 10 # FuncInfo section string offset=10
@@ -57,7 +57,11 @@ define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 {
; CHECK-NEXT: .long 3
; CHECK-NEXT: .long 16 # LineInfo
; CHECK-NEXT: .long 10 # LineInfo section string offset=10
-; CHECK-NEXT: .long 1
+; CHECK-NEXT: .long 2
+; CHECK-NEXT: .long .Lfunc_begin{{[0-9]+}}
+; CHECK-NEXT: .long 16
+; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long 1024 # Line 1 Col 0
; CHECK-NEXT: .long .Ltmp{{[0-9]+}}
; CHECK-NEXT: .long 16
; CHECK-NEXT: .long 0
diff --git a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
index f9439e606ae87..121669e18e0eb 100644
--- a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
+++ b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
@@ -52,8 +52,8 @@ define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 {
; CHECK-NEXT: .long 0
; CHECK-NEXT: .long 20
; CHECK-NEXT: .long 20
-; CHECK-NEXT: .long 28
-; CHECK-NEXT: .long 48
+; CHECK-NEXT: .long 44
+; CHECK-NEXT: .long 64
; CHECK-NEXT: .long 0
; CHECK-NEXT: .long 8 # FuncInfo
; CHECK-NEXT: .long 11 # FuncInfo section string offset=11
@@ -62,7 +62,11 @@ define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 {
; CHECK-NEXT: .long 3
; CHECK-NEXT: .long 16 # LineInfo
; CHECK-NEXT: .long 11 # LineInfo section string offset=11
-; CHECK-NEXT: .long 1
+; CHECK-NEXT: .long 2
+; CHECK-NEXT: .long .Lfunc_begin0
+; CHECK-NEXT: .long 17
+; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long 1024 # Line 1 Col 0
; CHECK-NEXT: .long .Ltmp{{[0-9]+}}
; CHECK-NEXT: .long 17
; CHECK-NEXT: .long 0
diff --git a/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll b/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll
index 67ad819108c7f..4e58b06e16a68 100644
--- a/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll
+++ b/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll
@@ -27,7 +27,12 @@ entry:
}
; CHECK: r0 = 1
-; CHECK-NEXT: exit
+; CHECK-NEXT: # kill: def $w0 killed $w0 killed $r0
+; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .loc 1 6 3 prologue_end # test.c:6:3
+; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: exit
; CHECK: .long 26 # BTF_KIND_STRUCT(id = 4)
; CHECK-NEXT: .long 67108865 # 0x4000001
diff --git a/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s b/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s
deleted file mode 100644
index 1ee14f5e0ed97..0000000000000
--- a/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s
+++ /dev/null
@@ -1,18 +0,0 @@
-// Make sure that llvm-objdump --mcpu=v3 enables ALU32 feature.
-//
-// Only test a few instructions here, assembler-disassembler.s is more
-// comprehensive but uses --mattr=+alu32 option.
-//
-// RUN: llvm-mc -triple bpfel --mcpu=v3 --assemble --filetype=obj %s -o %t
-// RUN: llvm-objdump -d --mcpu=v2 %t | FileCheck %s --check-prefix=V2
-// RUN: llvm-objdump -d --mcpu=v3 %t | FileCheck %s --check-prefix=V3
-
-w0 = *(u32 *)(r1 + 0)
-lock *(u32 *)(r1 + 0x1) &= w2
-
-
-// V2: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0x0)
-// V2: c3 21 01 00 50 00 00 00 <unknown>
-
-// V3: 61 10 00 00 00 00 00 00 w0 = *(u32 *)(r1 + 0x0)
-// V3: c3 21 01 00 50 00 00 00 lock *(u32 *)(r1 + 0x1) &= w2
diff --git a/llvm/test/CodeGen/BPF/fi_ri.ll b/llvm/test/CodeGen/BPF/fi_ri.ll
index 8d60d29b52726..c5049d8cabc67 100644
--- a/llvm/test/CodeGen/BPF/fi_ri.ll
+++ b/llvm/test/CodeGen/BPF/fi_ri.ll
@@ -5,10 +5,10 @@
; Function Attrs: nounwind uwtable
define i32 @test() #0 {
%key = alloca %struct.key_t, align 4
-; CHECK: r1 = 0
-; CHECK: *(u32 *)(r10 - 8) = r1
-; CHECK: *(u64 *)(r10 - 16) = r1
-; CHECK: *(u64 *)(r10 - 24) = r1
+; CHECK: r6 = 0
+; CHECK: *(u32 *)(r10 - 8) = r6
+; CHECK: *(u64 *)(r10 - 16) = r6
+; CHECK: *(u64 *)(r10 - 24) = r6
call void @llvm.memset.p0.i64(ptr align 4 %key, i8 0, i64 20, i1 false)
; CHECK: r1 = r10
; CHECK: r1 += -20
diff --git a/llvm/test/CodeGen/BPF/rodata_1.ll b/llvm/test/CodeGen/BPF/rodata_1.ll
index 26dd85caa1d21..560988b60115a 100644
--- a/llvm/test/CodeGen/BPF/rodata_1.ll
+++ b/llvm/test/CodeGen/BPF/rodata_1.ll
@@ -35,13 +35,13 @@ define i32 @test() local_unnamed_addr #0 {
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr @g1, ptr @test.t1, i64 3, i1 false)
tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g2, ptr align 4 @test.t2, i64 20, i1 false)
-; CHECK: r1 = g1
-; CHECK: r2 = 0
-; CHECK: *(u8 *)(r1 + 1) = r2
-; CHECK: r3 = 1
-; CHECK: *(u8 *)(r1 + 2) = r3
-; CHECK: r1 = g2
-; CHECK: *(u32 *)(r1 + 8) = r3
+; CHECK: r1 = g1 ll
+; CHECK: r0 = 0
+; CHECK: *(u8 *)(r1 + 1) = r0
+; CHECK: r2 = 1
+; CHECK: *(u8 *)(r1 + 2) = r2
+; CHECK: r1 = g2 ll
+; CHECK: *(u32 *)(r1 + 8) = r2
ret i32 0
}
; CHECK: .section .rodata,"a", at progbits
diff --git a/llvm/test/CodeGen/BPF/rodata_2.ll b/llvm/test/CodeGen/BPF/rodata_2.ll
index bb7bf4ba8ace7..19cca46afbb5c 100644
--- a/llvm/test/CodeGen/BPF/rodata_2.ll
+++ b/llvm/test/CodeGen/BPF/rodata_2.ll
@@ -39,11 +39,11 @@ entry:
; CHECK: *(u32 *)(r1 + 20) = r2
; CHECK: r2 = 1
; CHECK: *(u32 *)(r1 + 16) = r2
-; CHECK: r2 = 0
-; CHECK: *(u32 *)(r1 + 28) = r2
-; CHECK: *(u32 *)(r1 + 8) = r2
-; CHECK: *(u32 *)(r1 + 4) = r2
-; CHECK: *(u32 *)(r1 + 0) = r2
+; CHECK: r0 = 0
+; CHECK: *(u32 *)(r1 + 28) = r0
+; CHECK: *(u32 *)(r1 + 8) = r0
+; CHECK: *(u32 *)(r1 + 4) = r0
+; CHECK: *(u32 *)(r1 + 0) = r0
ret i32 0
}
; CHECK: .section .rodata.cst32,"aM", at progbits,32
diff --git a/temp b/temp
deleted file mode 100644
index 8101ff2bb0cac..0000000000000
--- a/temp
+++ /dev/null
@@ -1,178 +0,0 @@
- .file "filename.ll"
- .text
- .globl test # -- Begin function test
- .p2align 3
- .type test, at function
-test: # @test
-.Ltest$local:
- .type .Ltest$local, at function
-.Lfunc_begin0:
- .file 1 "/home/yhs/ttmp" "/home/yhs/ttmp/t.c"
- .loc 1 1 0 # /home/yhs/ttmp/t.c:1:0
- .cfi_startproc
-# %bb.0:
- w0 = 0
-.Ltmp0:
- .loc 1 1 14 prologue_end # /home/yhs/ttmp/t.c:1:14
-.Ltmp1:
-.Ltmp2:
- exit
-.Ltmp3:
-.Ltmp4:
-.Lfunc_end0:
- .size test, .Lfunc_end0-test
- .size .Ltest$local, .Lfunc_end0-test
- .cfi_endproc
- # -- End function
- .section .debug_abbrev,"", at progbits
- .byte 1 # Abbreviation Code
- .byte 17 # DW_TAG_compile_unit
- .byte 1 # DW_CHILDREN_yes
- .byte 37 # DW_AT_producer
- .byte 14 # DW_FORM_strp
- .byte 19 # DW_AT_language
- .byte 5 # DW_FORM_data2
- .byte 3 # DW_AT_name
- .byte 14 # DW_FORM_strp
- .byte 16 # DW_AT_stmt_list
- .byte 23 # DW_FORM_sec_offset
- .byte 27 # DW_AT_comp_dir
- .byte 14 # DW_FORM_strp
- .byte 17 # DW_AT_low_pc
- .byte 1 # DW_FORM_addr
- .byte 18 # DW_AT_high_pc
- .byte 6 # DW_FORM_data4
- .byte 0 # EOM(1)
- .byte 0 # EOM(2)
- .byte 2 # Abbreviation Code
- .byte 46 # DW_TAG_subprogram
- .byte 0 # DW_CHILDREN_no
- .byte 17 # DW_AT_low_pc
- .byte 1 # DW_FORM_addr
- .byte 18 # DW_AT_high_pc
- .byte 6 # DW_FORM_data4
- .byte 64 # DW_AT_frame_base
- .byte 24 # DW_FORM_exprloc
- .byte 3 # DW_AT_name
- .byte 14 # DW_FORM_strp
- .byte 58 # DW_AT_decl_file
- .byte 11 # DW_FORM_data1
- .byte 59 # DW_AT_decl_line
- .byte 11 # DW_FORM_data1
- .byte 73 # DW_AT_type
- .byte 19 # DW_FORM_ref4
- .byte 63 # DW_AT_external
- .byte 25 # DW_FORM_flag_present
- .byte 0 # EOM(1)
- .byte 0 # EOM(2)
- .byte 3 # Abbreviation Code
- .byte 36 # DW_TAG_base_type
- .byte 0 # DW_CHILDREN_no
- .byte 3 # DW_AT_name
- .byte 14 # DW_FORM_strp
- .byte 62 # DW_AT_encoding
- .byte 11 # DW_FORM_data1
- .byte 11 # DW_AT_byte_size
- .byte 11 # DW_FORM_data1
- .byte 0 # EOM(1)
- .byte 0 # EOM(2)
- .byte 0 # EOM(3)
- .section .debug_info,"", at progbits
-.Lcu_begin0:
- .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit
-.Ldebug_info_start0:
- .short 4 # DWARF version number
- .long .debug_abbrev # Offset Into Abbrev. Section
- .byte 8 # Address Size (in bytes)
- .byte 1 # Abbrev [1] 0xb:0x40 DW_TAG_compile_unit
- .long .Linfo_string0 # DW_AT_producer
- .short 12 # DW_AT_language
- .long .Linfo_string1 # DW_AT_name
- .long .Lline_table_start0 # DW_AT_stmt_list
- .long .Linfo_string2 # DW_AT_comp_dir
- .quad .Lfunc_begin0 # DW_AT_low_pc
- .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc
- .byte 2 # Abbrev [2] 0x2a:0x19 DW_TAG_subprogram
- .quad .Lfunc_begin0 # DW_AT_low_pc
- .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc
- .byte 1 # DW_AT_frame_base
- .byte 90
- .long .Linfo_string3 # DW_AT_name
- .byte 1 # DW_AT_decl_file
- .byte 1 # DW_AT_decl_line
- .long 67 # DW_AT_type
- # DW_AT_external
- .byte 3 # Abbrev [3] 0x43:0x7 DW_TAG_base_type
- .long .Linfo_string4 # DW_AT_name
- .byte 5 # DW_AT_encoding
- .byte 4 # DW_AT_byte_size
- .byte 0 # End Of Children Mark
-.Ldebug_info_end0:
- .section .debug_str,"MS", at progbits,1
-.Linfo_string0:
- .asciz "clang version 8.0.20181009 " # string offset=0
-.Linfo_string1:
- .asciz "/home/yhs/ttmp/t.c" # string offset=28
-.Linfo_string2:
- .asciz "/home/yhs/ttmp" # string offset=47
-.Linfo_string3:
- .asciz "test" # string offset=62
-.Linfo_string4:
- .asciz "int" # string offset=67
- .section .BTF,"", at progbits
- .short 60319 # 0xeb9f
- .byte 1
- .byte 0
- .long 24
- .long 0
- .long 40
- .long 40
- .long 35
- .long 0 # BTF_KIND_FUNC_PROTO(id = 1)
- .long 218103808 # 0xd000000
- .long 2
- .long 1 # BTF_KIND_INT(id = 2)
- .long 16777216 # 0x1000000
- .long 4
- .long 16777248 # 0x1000020
- .long 5 # BTF_KIND_FUNC(id = 3)
- .long 201326593 # 0xc000001
- .long 1
- .byte 0 # string offset=0
- .ascii "int" # string offset=1
- .byte 0
- .ascii "test" # string offset=5
- .byte 0
- .ascii ".text" # string offset=10
- .byte 0
- .ascii "/home/yhs/ttmp/t.c" # string offset=16
- .byte 0
- .section .BTF.ext,"", at progbits
- .short 60319 # 0xeb9f
- .byte 1
- .byte 0
- .long 32
- .long 0
- .long 20
- .long 20
- .long 44
- .long 64
- .long 0
- .long 8 # FuncInfo
- .long 10 # FuncInfo section string offset=10
- .long 1
- .long .Lfunc_begin0
- .long 3
- .long 16 # LineInfo
- .long 10 # LineInfo section string offset=10
- .long 2
- .long .Lfunc_begin0
- .long 16
- .long 0
- .long 1024 # Line 1 Col 0
- .long .Ltmp2
- .long 16
- .long 0
- .long 1038 # Line 1 Col 14
- .section .debug_line,"", at progbits
-.Lline_table_start0:
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