[clang] dd0fc25 - [Mips] Fix mcpu flag with i6400/i6500 (#161330)

[via cfe-commits]

Author: ArielCPU
Date: 2025-10-13T18:04:43+08:00
New Revision: dd0fc259c09967227edfe158f5d19aad942c6308

URL: https://github.com/llvm/llvm-project/commit/dd0fc259c09967227edfe158f5d19aad942c6308
DIFF: https://github.com/llvm/llvm-project/commit/dd0fc259c09967227edfe158f5d19aad942c6308.diff

LOG: [Mips] Fix mcpu flag with i6400/i6500 (#161330)

The compiler is missing cases where it checks mips64r6 but not
i6400/i6500 causing wrong defines to be generated

Added: 
    

Modified: 
    clang/lib/Basic/Targets/Mips.cpp
    clang/lib/Basic/Targets/Mips.h
    clang/lib/Driver/ToolChains/Arch/Mips.cpp
    clang/test/Preprocessor/init-mips.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 34837cc363a37..de6ccff64f4eb 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -72,7 +72,7 @@ unsigned MipsTargetInfo::getISARev() const {
       .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
       .Cases("mips32r3", "mips64r3", 3)
       .Cases("mips32r5", "mips64r5", "p5600", 5)
-      .Cases("mips32r6", "mips64r6", 6)
+      .Cases("mips32r6", "mips64r6", "i6400", "i6500", 6)
       .Default(0);
 }
 
@@ -270,8 +270,9 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
     return false;
   }
   // Mips revision 6 and -mfp32 are incompatible
-  if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
-      CPU == "mips64r6")) {
+  if (FPMode != FP64 && FPMode != FPXX &&
+      (CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" ||
+       CPU == "i6500")) {
     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
     return false;
   }

diff  --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index e199df32f56ee..930271cee73ff 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -83,7 +83,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
   }
 
   bool isIEEE754_2008Default() const {
-    return CPU == "mips32r6" || CPU == "mips64r6";
+    return CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" ||
+           CPU == "i6500";
   }
 
   enum FPModeEnum getDefaultFPMode() const {

diff  --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index 8787c8276721c..bac8681921877 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -442,6 +442,8 @@ bool mips::hasCompactBranches(StringRef &CPU) {
   return llvm::StringSwitch<bool>(CPU)
       .Case("mips32r6", true)
       .Case("mips64r6", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
 

diff  --git a/clang/test/Preprocessor/init-mips.c b/clang/test/Preprocessor/init-mips.c
index 125872a001bac..c829eebdc9ec9 100644
--- a/clang/test/Preprocessor/init-mips.c
+++ b/clang/test/Preprocessor/init-mips.c
@@ -1649,6 +1649,28 @@
 // MIPS-ARCH-OCTEONP:#define __OCTEON__ 1
 // MIPS-ARCH-OCTEONP:#define __mips_isa_rev 2
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN:            -target-cpu i6400 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-ARCH-I6400 %s
+//
+// MIPS-ARCH-I6400:#define _MIPS_ARCH "i6400"
+// MIPS-ARCH-I6400:#define _MIPS_ARCH_I6400 1
+// MIPS-ARCH-I6400:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-I6400:#define __mips_abs2008 1
+// MIPS-ARCH-I6400:#define __mips_isa_rev 6
+// MIPS-ARCH-I6400:#define __mips_nan2008 1
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN:            -target-cpu i6500 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-ARCH-I6500 %s
+//
+// MIPS-ARCH-I6500:#define _MIPS_ARCH "i6500"
+// MIPS-ARCH-I6500:#define _MIPS_ARCH_I6500 1
+// MIPS-ARCH-I6500:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-I6500:#define __mips_abs2008 1
+// MIPS-ARCH-I6500:#define __mips_isa_rev 6
+// MIPS-ARCH-I6500:#define __mips_nan2008 1
+
 // Check MIPS float ABI macros
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding \