[clang] [clang][Driver][RISCV] Rename `getRISCFeaturesFromMcpu`. NFCI (PR #162545)

[Min-Yih Hsu via cfe-commits]

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/162545

This function, which has a typo in the name btw, is no longer doing what it was created to do: instead of deducting non-extension target features from `-mcpu` -- a task that was (more or less) subsumed by `riscv::getRISCVTargetFeatures` -- it is only checking if the `-mcpu` value is valid or not now. Therefore, this patch renames it into `isValidRISCVCPU` and exits early if it's not.

NFCI.

>From 396a0229847546d4058c3f1ade591748e5ddfdf3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Wed, 8 Oct 2025 13:22:55 -0700
Subject: [PATCH] [clang][Driver][RISCV] Rename `getRISCFeaturesFromMcpu`. NFCI

---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 76dde0da8e849..f2e79e71f93d4 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -49,11 +49,8 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
   return true;
 }
 
-// Get features except standard extension feature
-static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
-                                    const llvm::Triple &Triple,
-                                    StringRef Mcpu,
-                                    std::vector<StringRef> &Features) {
+static bool isValidRISCVCPU(const Driver &D, const Arg *A,
+                            const llvm::Triple &Triple, StringRef Mcpu) {
   bool Is64Bit = Triple.isRISCV64();
   if (!llvm::RISCV::parseCPU(Mcpu, Is64Bit)) {
     // Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
@@ -63,7 +60,9 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
     else
       D.Diag(clang::diag::err_drv_unsupported_option_argument)
           << A->getSpelling() << Mcpu;
+    return false;
   }
+  return true;
 }
 
 void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
@@ -84,7 +83,8 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
     if (CPU == "native")
       CPU = llvm::sys::getHostCPUName();
 
-    getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features);
+    if (!isValidRISCVCPU(D, A, Triple, CPU))
+      return;
 
     if (llvm::RISCV::hasFastScalarUnalignedAccess(CPU))
       CPUFastScalarUnaligned = true;