[clang] [Headers][X86] VectorExprEvaluator::VisitCallExpr - allow SSE/AVX2/AVX512 pack intrinsics to be used in constexpr (PR #156003)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Sep 19 02:25:05 PDT 2025
================
@@ -2604,6 +2605,51 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool interp__builtin_x86_pack(
+ InterpState &S, CodePtr, const CallExpr *E,
+ llvm::function_ref<APSInt(const APSInt &)> narrowElement) {
+ const auto *VT0 = E->getArg(0)->getType()->castAs<VectorType>();
+ const auto *VT1 = E->getArg(1)->getType()->castAs<VectorType>();
+ assert(VT0 && VT1 && "pack builtin VT0 and VT1 must be VectorType");
+ assert(VT0->getElementType() == VT1->getElementType() &&
+ VT0->getNumElements() == VT1->getNumElements() &&
+ "pack builtin VT0 and VT1 ElementType must be same");
+
+ const Pointer &RHS = S.Stk.pop<Pointer>();
+ const Pointer &LHS = S.Stk.pop<Pointer>();
+ const Pointer &Dst = S.Stk.peek<Pointer>();
+
+ ASTContext &Ctx = S.getASTContext();
+ const unsigned SrcBits = Ctx.getIntWidth(VT0->getElementType());
+ const unsigned LHSVecLen = VT0->getNumElements();
+ const unsigned VectorBits = LHSVecLen * SrcBits;
+ const unsigned SrcPerLane = VectorBits >= 128 ? (128 / SrcBits) : LHSVecLen;
+ const unsigned Lanes = VectorBits >= 128 ? (VectorBits / 128) : 1;
+
+ PrimType SrcT = *S.getContext().classify(VT0->getElementType());
+ PrimType DstT = *S.getContext().classify(getElemType(Dst));
----------------
woruyu wrote:
if the two element means VT0 and VT1, they are the same.
https://github.com/llvm/llvm-project/pull/156003
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