[clang] [Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow AVX/AVX512 subvector insertion intrinsics to be used in constexpr #157709 (PR #158778)

via cfe-commits cfe-commits at lists.llvm.org
Thu Sep 18 04:46:47 PDT 2025


github-actions[bot] wrote:

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``````````bash
git-clang-format --diff origin/main HEAD --extensions c,cpp -- clang/lib/AST/ByteCode/InterpBuiltin.cpp clang/lib/AST/ExprConstant.cpp clang/test/CodeGen/X86/avx-builtins.c clang/test/CodeGen/X86/avx2-builtins.c clang/test/CodeGen/X86/avx512dq-builtins.c clang/test/CodeGen/X86/avx512f-builtins.c clang/test/CodeGen/X86/avx512vl-builtins.c clang/test/CodeGen/X86/avx512vldq-builtins.c
``````````

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The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
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View the diff from clang-format here.
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``````````diff
diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
index c0c641963..64962ee13 100644
--- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp
+++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
@@ -2935,7 +2935,8 @@ static bool interp__builtin_x86_insert_subvector(InterpState &S, CodePtr OpPC,
   unsigned BaseElements = BaseVec.getNumElems();
   unsigned SubElements = SubVec.getNumElems();
 
-  assert(SubElements != 0 && BaseElements != 0 && (BaseElements % SubElements) == 0);
+  assert(SubElements != 0 && BaseElements != 0 &&
+         (BaseElements % SubElements) == 0);
 
   unsigned NumLanes = BaseElements / SubElements;
   unsigned Lane = static_cast<unsigned>(Index % NumLanes);

``````````

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https://github.com/llvm/llvm-project/pull/158778


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