[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

[Brandon Wu via cfe-commits]

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@@ -23133,6 +23133,12 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
           &RISCV::VRN2M4RegClass}) {
       if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
         return std::make_pair(0U, RC);
+
+      if (VT.isFixedLengthVector() && Subtarget.useRVVForFixedLengthVectors()) {
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4vtomat wrote:

Yeah right, we should use `useRVVForFixedLengthVectorVT`

https://github.com/llvm/llvm-project/pull/150724