[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

[Craig Topper via cfe-commits]

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@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
+; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
+
+define dso_local void @prefetch_read(ptr noundef %a) {
+; RV32XMIPSPREFETCH-LABEL: prefetch_read:
+; RV32XMIPSPREFETCH:    mips.perf       8, 511(a0)
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_read:
+; RV64XMIPSPREFETCH:    mips.perf       8, 511(a0)
+entry:
+  %a.addr = alloca ptr, align 8
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topperc wrote:

Why do we need this `alloca`, `load`, and `store`. This looks like clang -O0 IR.

https://github.com/llvm/llvm-project/pull/145647