[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

[Craig Topper via cfe-commits]

================
@@ -2925,6 +2925,54 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
   return true;
 }
 
+/// Similar to SelectAddrRegImm, except that the offset restricted for
+/// nine bits.
+bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
+                                          SDValue &Offset) {
+  if (SelectAddrFrameIndex(Addr, Base, Offset))
+    return true;
+
+  SDLoc DL(Addr);
+  MVT VT = Addr.getSimpleValueType();
+
+  if (CurDAG->isBaseWithConstantOffset(Addr)) {
+
+    int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+    if (isUInt<9>(CVal)) {
+      Base = Addr.getOperand(0);
+
+      if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
+        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
+      Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
+      return true;
+    }
+
+    // Handle with 12 bit ofset  immediates with ADDI.
+    else if (Addr.getOpcode() == ISD::ADD &&
+             isa<ConstantSDNode>(Addr.getOperand(1))) {
+      int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+      assert(!isUInt<9>(CVal) && "uimm9 not already handled?");
+
+      if (isUInt<12>(CVal)) {
+        Base = SDValue(CurDAG->getMachineNode(
+                           RISCV::ADDI, DL, VT, Addr.getOperand(0),
+                           CurDAG->getSignedTargetConstant(CVal, DL, VT)),
+                       0);
+        Offset = CurDAG->getTargetConstant(0, DL, VT);
+        return true;
+      }
+    }
+  }
+  // Immediates more than 12 bits i.e LUI,ADDI,ADD
+  if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
----------------
topperc wrote:

The IsPrefetch flag for SelectConstantAddr matches a 12-bit immediate with 5 0s in the LSBs. That's not what you want for your instruction.

https://github.com/llvm/llvm-project/pull/145647