[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)
Boyao Wang via cfe-commits
cfe-commits at lists.llvm.org
Tue Jun 24 23:23:23 PDT 2025
https://github.com/BoyaoWang430 updated https://github.com/llvm/llvm-project/pull/127463
>From e740d8cfb8b689d766841396c5a6ab9a1d389ec7 Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Mon, 17 Feb 2025 17:35:52 +0800
Subject: [PATCH 1/3] [RISCV] Add Support of RISCV Zibimm Experimental
Extension
---
.../Driver/print-supported-extensions-riscv.c | 1 +
.../test/Preprocessor/riscv-target-features.c | 9 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 15 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 12 +
.../RISCV/GISel/RISCVInstructionSelector.cpp | 2 +-
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 20 ++
llvm/lib/Target/RISCV/RISCVFeatures.td | 6 +
llvm/lib/Target/RISCV/RISCVInstrFormats.td | 16 +
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 32 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td | 48 +++
llvm/test/CodeGen/RISCV/attributes.ll | 6 +
llvm/test/CodeGen/RISCV/zibimm.ll | 299 ++++++++++++++++++
llvm/test/MC/RISCV/zibimm-invalid.s | 34 ++
llvm/test/MC/RISCV/zibimm-valid.s | 63 ++++
.../TargetParser/RISCVISAInfoTest.cpp | 1 +
18 files changed, 566 insertions(+), 2 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td
create mode 100644 llvm/test/CodeGen/RISCV/zibimm.ll
create mode 100644 llvm/test/MC/RISCV/zibimm-invalid.s
create mode 100644 llvm/test/MC/RISCV/zibimm-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 5008c2b7f789d..17125ad2a6713 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -205,6 +205,7 @@
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD))
+// CHECK-NEXT: zibimm 0.1 'Zibimm' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 86085c21a95aa..7ac37bde70e05 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -122,6 +122,7 @@
// CHECK-NOT: __riscv_zfinx {{.*$}}
// CHECK-NOT: __riscv_zhinx {{.*$}}
// CHECK-NOT: __riscv_zhinxmin {{.*$}}
+// CHECK-NOT: __riscv_zibimm {{.*$}}
// CHECK-NOT: __riscv_zic64b {{.*$}}
// CHECK-NOT: __riscv_zicbom {{.*$}}
// CHECK-NOT: __riscv_zicbop {{.*$}}
@@ -1029,6 +1030,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZHINXMIN-EXT %s
// CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zibimm0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBIMM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zibimm0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBIMM-EXT %s
+// CHECK-ZIBIMM-EXT: __riscv_zibimm
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izic64b -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIC64B-EXT %s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index e5d8ab07891ac..7e6fcc373334b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -744,6 +744,17 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return isUImmPred([](int64_t Imm) { return Imm != 0 && isUInt<5>(Imm); });
}
+ bool isUImm5Zibimm() const {
+ if (!isImm())
+ return false;
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ Imm = fixImmediateForRV32(Imm, isRV64Imm());
+ return IsConstantImm && ((isUInt<5>(Imm) && Imm != 0) || Imm == -1) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
bool isUImm5GT3() const {
return isUImmPred([](int64_t Imm) { return isUInt<5>(Imm) && Imm > 3; });
}
@@ -1466,6 +1477,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
case Match_InvalidUImm5NonZero:
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
+ case Match_InvalidUImm5Zibimm:
+ return generateImmOutOfRangeError(
+ Operands, ErrorInfo, -1, (1 << 5) - 1,
+ "immediate must be non-zero in the range");
case Match_InvalidUImm5GT3:
return generateImmOutOfRangeError(Operands, ErrorInfo, 4, (1 << 5) - 1);
case Match_InvalidUImm5Plus1:
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 27e04c0cb1f8b..9e8e751e7f9c0 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -457,6 +457,18 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
}
+template <unsigned N>
+static DecodeStatus decodeUImmZibimmOperand(MCInst &Inst, uint32_t Imm,
+ int64_t Address,
+ const MCDisassembler *Decoder) {
+ assert(isUInt<N>(Imm) && "Invalid immediate");
+ if (Imm)
+ Inst.addOperand(MCOperand::createImm(Imm));
+ else
+ Inst.addOperand(MCOperand::createImm(-1));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus
decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index f83c2b6da8923..18ce5407f816c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -789,7 +789,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
RISCVCC::CondCode CC;
getOperandsForBranch(MI.getOperand(0).getReg(), CC, LHS, RHS, *MRI);
- auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS})
+ auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(STI, CC), {}, {LHS, RHS})
.addMBB(MI.getOperand(1).getMBB());
MI.eraseFromParent();
return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 3d304842fac13..983a94c8b8e77 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -301,6 +301,7 @@ enum OperandType : unsigned {
OPERAND_UIMM4,
OPERAND_UIMM5,
OPERAND_UIMM5_NONZERO,
+ OPERAND_UIMM5_ZIBIMM,
OPERAND_UIMM5_GT3,
OPERAND_UIMM5_PLUS1,
OPERAND_UIMM5_GE6_PLUS1,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index ce0fbc0ac0654..f2ef1b06a95ab 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -97,6 +97,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ uint64_t getImmOpValueZibimm(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
@@ -545,6 +549,22 @@ RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
return getImmOpValue(MI, OpNo, Fixups, STI);
}
+uint64_t
+RISCVMCCodeEmitter::getImmOpValueZibimm(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+
+ if (MO.isImm()) {
+ uint64_t Res = MO.getImm();
+ if (Res >= 1 && Res <= 31)
+ return Res;
+ if (Res == (uint64_t)-1)
+ return 0;
+ }
+ return getImmOpValue(MI, OpNo, Fixups, STI);
+}
+
uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 36b3aff51cda9..e7e8c8f4c5bbf 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -78,6 +78,12 @@ def FeatureStdExtE
: RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">,
RISCVExtensionBitmask<0, 4>;
+def FeatureStdExtZibimm
+ : RISCVExperimentalExtension<0, 1, "Branch with Immediate">;
+def HasStdExtZibimm : Predicate<"Subtarget->hasStdExtZibimm()">,
+ AssemblerPredicate<(all_of FeatureStdExtZibimm),
+ "'Zibimm' (Branch with Immediate)">;
+
def FeatureStdExtZic64b
: RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index b6b64b57b1b3e..19de5a0ac4005 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -496,6 +496,22 @@ class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
let Inst{6-0} = opcode.Value;
}
+class RVInstBIMM<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {
+ bits<12> imm12;
+ bits<5> cimm;
+ bits<5> rs1;
+ let Inst{31} = imm12{11};
+ let Inst{30-25} = imm12{9-4};
+ let Inst{24-20} = cimm;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-8} = imm12{3-0};
+ let Inst{7} = imm12{10};
+ let Inst{6-0} = opcode.Value;
+}
+
class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6e30ffce99c4d..94e93a974556c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -962,6 +962,10 @@ static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
switch (Opc) {
default:
return RISCVCC::COND_INVALID;
+ case RISCV::BEQI:
+ return RISCVCC::COND_EQ;
+ case RISCV::BNEI:
+ return RISCVCC::COND_NE;
case RISCV::BEQ:
return RISCVCC::COND_EQ;
case RISCV::BNE:
@@ -1039,14 +1043,31 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
+<<<<<<< HEAD
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
+=======
+unsigned RISCVCC::getBrCond(const RISCVSubtarget &STI, RISCVCC::CondCode CC,
+ bool Imm) {
+>>>>>>> 63ba04f2fad0 ([RISCV] Add Support of RISCV Zibimm Experimental Extension)
switch (CC) {
default:
llvm_unreachable("Unknown condition code!");
case RISCVCC::COND_EQ:
+<<<<<<< HEAD
return RISCV::BEQ;
case RISCVCC::COND_NE:
return RISCV::BNE;
+=======
+ return Imm ? (STI.hasStdExtZibimm()
+ ? RISCV::BEQI
+ : (STI.hasVendorXCVbi() ? RISCV::CV_BEQIMM : RISCV::BEQ))
+ : RISCV::BEQ;
+ case RISCVCC::COND_NE:
+ return Imm ? (STI.hasStdExtZibimm()
+ ? RISCV::BNEI
+ : (STI.hasVendorXCVbi() ? RISCV::CV_BNEIMM : RISCV::BNE))
+ : RISCV::BNE;
+>>>>>>> 63ba04f2fad0 ([RISCV] Add Support of RISCV Zibimm Experimental Extension)
case RISCVCC::COND_LT:
return RISCV::BLT;
case RISCVCC::COND_GE:
@@ -1086,8 +1107,14 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
}
}
+<<<<<<< HEAD
const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const {
return get(RISCVCC::getBrCond(CC));
+=======
+const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC,
+ bool Imm) const {
+ return get(RISCVCC::getBrCond(STI, CC, Imm));
+>>>>>>> 63ba04f2fad0 ([RISCV] Add Support of RISCV Zibimm Experimental Extension)
}
RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
@@ -1507,6 +1534,8 @@ bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
case RISCV::BGE:
case RISCV::BLTU:
case RISCV::BGEU:
+ case RISCV::BEQI:
+ case RISCV::BNEI:
case RISCV::CV_BEQIMM:
case RISCV::CV_BNEIMM:
case RISCV::QC_BEQI:
@@ -2703,6 +2732,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM2_LSB0:
Ok = isShiftedUInt<1, 1>(Imm);
break;
+ case RISCVOp::OPERAND_UIMM5_ZIBIMM:
+ Ok = (isUInt<5>(Imm) && Imm != 0) || Imm == -1;
+ break;
case RISCVOp::OPERAND_UIMM5_LSB0:
Ok = isShiftedUInt<4, 1>(Imm);
break;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 020be91e90e0b..986d5015de667 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -59,7 +59,7 @@ enum CondCode {
};
CondCode getOppositeBranchCondition(CondCode);
-unsigned getBrCond(CondCode CC);
+unsigned getBrCond(const RISCVSubtarget &STI, CondCode CC, bool Imm = false);
} // end of namespace RISCVCC
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index aa1ebba567824..9382203e967f4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2249,6 +2249,7 @@ include "RISCVInstrInfoZicbo.td"
include "RISCVInstrInfoZicond.td"
include "RISCVInstrInfoZicfiss.td"
include "RISCVInstrInfoZilsd.td"
+include "RISCVInstrInfoZibimm.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td
new file mode 100644
index 0000000000000..ad0164bd0fb6b
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td
@@ -0,0 +1,48 @@
+//===-- RISCVInstrInfoZibimm.td - 'Zibimm' instructions ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'Zibimm' (branch with imm).
+///
+//===----------------------------------------------------------------------===//
+// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
+def uimm5_zibimm : RISCVOp, ImmLeaf<XLenVT, [{
+ return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
+}]> {
+ let ParserMatchClass = UImmAsmOperand<5, "Zibimm">;
+ let EncoderMethod = "getImmOpValueZibimm";
+ let DecoderMethod = "decodeUImmZibimmOperand<5>";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return (Imm >= 1 && Imm <= 31) || Imm == -1;
+ }];
+ let OperandType = "OPERAND_UIMM5_ZIBIMM";
+}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Branch_imm<bits<3> funct3, string opcodestr>
+ : RVInstBIMM<funct3, OPC_BRANCH, (outs),
+ (ins GPR:$rs1, uimm5_zibimm:$cimm, simm13_lsb0:$imm12),
+ opcodestr, "$rs1, $cimm, $imm12">,
+ Sched<[WriteJmp, ReadJmp]> {
+ let isBranch = 1;
+ let isTerminator = 1;
+}
+let Predicates = [HasStdExtZibimm] in {
+def BEQI : Branch_imm<0b010, "beqi">;
+def BNEI : Branch_imm<0b011, "bnei">;
+} // Predicates = [HasStdExtZibimm]
+
+let Predicates = [HasStdExtZibimm] in {
+multiclass BccImmPat<CondCode Cond, Branch_imm Inst> {
+ def : Pat<(riscv_brcc (XLenVT GPR:$rs1), uimm5_zibimm:$cimm, Cond, bb:$imm12),
+ (Inst GPR:$rs1, uimm5_zibimm:$cimm, simm13_lsb0:$imm12)>;
+}
+defm : BccImmPat<SETEQ, BEQI>;
+defm : BccImmPat<SETNE, BNEI>;
+}// Predicates = [HasStdExtZibimm]
\ No newline at end of file
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index c5188aa1918bf..5da7f9c863c2e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -173,6 +173,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibimm %s -o - | FileCheck --check-prefix=RV32ZIBIMM %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -338,6 +339,9 @@
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibimm %s -o - | FileCheck --check-prefix=RV64ZIBIMM %s
; Tests for profile features.
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
@@ -526,6 +530,7 @@
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
+; RV32ZIBIMM: .attribute 5, "rv32i2p1_zibimm0p1"
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -688,6 +693,7 @@
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p3"
+; RV64ZIBIMM: .attribute 5, "rv64i2p1_zibimm0p1"
; RVI20U32: .attribute 5, "rv32i2p1"
; RVI20U64: .attribute 5, "rv64i2p1"
diff --git a/llvm/test/CodeGen/RISCV/zibimm.ll b/llvm/test/CodeGen/RISCV/zibimm.ll
new file mode 100644
index 0000000000000..d0cf335bc2a36
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zibimm.ll
@@ -0,0 +1,299 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibimm -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I-ZIBIMM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibimm -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I-ZIBIMM %s
+
+define void @test_bne_neg(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_bne_neg:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: bnei a1, -1, .LBB0_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB0_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_bne_neg:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: bnei a1, -1, .LBB0_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB0_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, -1
+ br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!0 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_neg(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_beq_neg:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: beqi a1, -1, .LBB1_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB1_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_beq_neg:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: beqi a1, -1, .LBB1_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB1_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, -1
+ br i1 %tst1, label %end, label %test2, !prof !1
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!1 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_zero(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_bne_zero:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: bnez a1, .LBB2_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB2_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_bne_zero:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: bnez a1, .LBB2_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB2_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 0
+ br i1 %tst1, label %end, label %test2, !prof !2
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!2 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_zero(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_beq_zero:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: beqz a1, .LBB3_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB3_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_beq_zero:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: beqz a1, .LBB3_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB3_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 0
+ br i1 %tst1, label %end, label %test2, !prof !3
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!3 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_1(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_bne_1:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: bnei a1, 1, .LBB4_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB4_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_bne_1:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: bnei a1, 1, .LBB4_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB4_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 1
+ br i1 %tst1, label %end, label %test2, !prof !4
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!4 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_1(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_beq_1:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: beqi a1, 1, .LBB5_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB5_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_beq_1:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: beqi a1, 1, .LBB5_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB5_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 1
+ br i1 %tst1, label %end, label %test2, !prof !5
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!5 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_31(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_bne_31:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: bnei a1, 31, .LBB6_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB6_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_bne_31:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: bnei a1, 31, .LBB6_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB6_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 31
+ br i1 %tst1, label %end, label %test2, !prof !6
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!6 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_31(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_beq_31:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: beqi a1, 1, .LBB7_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB7_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_beq_31:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: beqi a1, 1, .LBB7_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB7_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 1
+ br i1 %tst1, label %end, label %test2, !prof !7
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!7 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_32(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_bne_32:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: li a2, 32
+; RV32I-ZIBIMM-NEXT: bne a1, a2, .LBB8_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB8_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_bne_32:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: li a2, 32
+; RV64I-ZIBIMM-NEXT: bne a1, a2, .LBB8_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB8_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 32
+ br i1 %tst1, label %end, label %test2, !prof !8
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!8 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_32(ptr %b) nounwind {
+; RV32I-ZIBIMM-LABEL: test_beq_32:
+; RV32I-ZIBIMM: # %bb.0:
+; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV32I-ZIBIMM-NEXT: li a2, 32
+; RV32I-ZIBIMM-NEXT: beq a1, a2, .LBB9_2
+; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV32I-ZIBIMM-NEXT: .LBB9_2: # %end
+; RV32I-ZIBIMM-NEXT: ret
+;
+; RV64I-ZIBIMM-LABEL: test_beq_32:
+; RV64I-ZIBIMM: # %bb.0:
+; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
+; RV64I-ZIBIMM-NEXT: li a2, 32
+; RV64I-ZIBIMM-NEXT: beq a1, a2, .LBB9_2
+; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
+; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
+; RV64I-ZIBIMM-NEXT: .LBB9_2: # %end
+; RV64I-ZIBIMM-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 32
+ br i1 %tst1, label %end, label %test2, !prof !9
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!9 = !{!"branch_weights", i32 1, i32 99}
diff --git a/llvm/test/MC/RISCV/zibimm-invalid.s b/llvm/test/MC/RISCV/zibimm-invalid.s
new file mode 100644
index 0000000000000..120190a1f5411
--- /dev/null
+++ b/llvm/test/MC/RISCV/zibimm-invalid.s
@@ -0,0 +1,34 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zibimm %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zibimm %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+beqi a0, 0x0, 0x400
+# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31]
+# CHECK-ERROR-LABEL: beqi a0, 0x0, 0x400
+beqi a0, 0x21, 0x400
+# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31]
+# CHECK-ERROR-LABEL: beqi a0, 0x21, 0x400
+beqi a2, 0x10, -0x1f000
+# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+# CHECK-ERROR-LABEL: beqi a2, 0x10, -0x1f000
+beqi a2, 0x10, 0x1000
+# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+# CHECK-ERROR-LABEL: beqi a2, 0x10, 0x1000
+beqi a2, 0x10, 0x111
+# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+# CHECK-ERROR-LABEL: beqi a2, 0x10, 0x111
+bnei a0, 0x0, 0x400
+# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31]
+# CHECK-ERROR-LABEL: bnei a0, 0x0, 0x400
+bnei a0, 0x21, 0x400
+# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31]
+# CHECK-ERROR-LABEL: bnei a0, 0x21, 0x400
+bnei a2, 0x10, -0x1f000
+# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+# CHECK-ERROR-LABEL: bnei a2, 0x10, -0x1f000
+bnei a2, 0x10, 0x1000
+# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+# CHECK-ERROR-LABEL: bnei a2, 0x10, 0x1000
+bnei a2, 0x10, 0x111
+# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+# CHECK-ERROR-LABEL: bnei a2, 0x10, 0x111
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/zibimm-valid.s b/llvm/test/MC/RISCV/zibimm-valid.s
new file mode 100644
index 0000000000000..e3baba6efa8a0
--- /dev/null
+++ b/llvm/test/MC/RISCV/zibimm-valid.s
@@ -0,0 +1,63 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zibimm %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-ASM
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zibimm %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-ASM
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibimm %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zibimm --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-OBJ
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibimm %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zibimm %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+beqi a0, 1, 1024
+# CHECK-OBJ: beqi a0, 1, 0x400
+# CHECK-ASM: beqi a0, 1, 1024
+# CHECK-ENCODING: [0x63,0x20,0x15,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: 40152063 <unknown>
+beqi a5, -1, -1024
+# CHECK-OBJ: beqi a5, -1, 0xfffffc04
+# CHECK-ASM: beqi a5, -1, -1024
+# CHECK-ENCODING: [0xe3,0xa0,0x07,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: c007a0e3 <unknown>
+beqi s0, 22, 0xffe
+# CHECK-OBJ: beqi s0, 22, 0x1006
+# CHECK-ASM: beqi s0, 22, 4094
+# CHECK-ENCODING: [0xe3,0x2f,0x64,0x7f]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: 7f642fe3 <unknown>
+beqi s1, 11, -4096
+# CHECK-OBJ: beqi s1, 11, 0xfffff00c
+# CHECK-ASM: beqi s1, 11, -4096
+# CHECK-ENCODING: [0x63,0xa0,0xb4,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: 80b4a063 <unknown>
+bnei a0, 1, 1024
+# CHECK-OBJ: bnei a0, 1, 0x410
+# CHECK-ASM: bnei a0, 1, 1024
+# CHECK-ENCODING: [0x63,0x30,0x15,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: 40153063 <unknown>
+bnei a5, -1, -1024
+# CHECK-OBJ: bnei a5, -1, 0xfffffc14
+# CHECK-ASM: bnei a5, -1, -1024
+# CHECK-ENCODING: [0xe3,0xb0,0x07,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: c007b0e3 <unknown>
+bnei s0, 22, 0xffe
+# CHECK-OBJ: bnei s0, 22, 0x1016
+# CHECK-ASM: bnei s0, 22, 4094
+# CHECK-ENCODING: [0xe3,0x3f,0x64,0x7f]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: 7f643fe3 <unknown>
+bnei s1, 11, -4096
+# CHECK-OBJ: bnei s1, 11, 0xfffff01c
+# CHECK-ASM: bnei s1, 11, -4096
+# CHECK-ENCODING: [0x63,0xb0,0xb4,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-UNKNOWN: 80b4b063 <unknown>
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 66e335a33a3f7..6250732daabbc 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1176,6 +1176,7 @@ R"(All available -march extensions for RISC-V
Experimental extensions
p 0.14
+ zibimm 0.1
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
zalasr 0.1
>From 1c53dff803de0ca7bde3f0b24a5b4ca663edbe6a Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Tue, 18 Feb 2025 15:50:33 +0800
Subject: [PATCH 2/3] Remove unnecessary check in getImmOpValueZibimm
---
.../lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index f2ef1b06a95ab..370ccf660551c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -556,12 +556,13 @@ RISCVMCCodeEmitter::getImmOpValueZibimm(const MCInst &MI, unsigned OpNo,
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isImm()) {
- uint64_t Res = MO.getImm();
- if (Res >= 1 && Res <= 31)
- return Res;
- if (Res == (uint64_t)-1)
+ int64_t Res = MO.getImm();
+ if (Res == -1)
return 0;
+
+ return Res;
}
+
return getImmOpValue(MI, OpNo, Fixups, STI);
}
>From 0184e36c6162a7aca48ffa35104ea16b2a2ac869 Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Tue, 24 Jun 2025 20:08:34 +0800
Subject: [PATCH 3/3] [RISCV] Rebase and update extention name to zibi
---
.../Driver/print-supported-extensions-riscv.c | 2 +-
.../test/Preprocessor/riscv-target-features.c | 12 +-
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 14 +-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 14 +-
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 +-
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 26 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 33 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
...strInfoZibimm.td => RISCVInstrInfoZibi.td} | 33 +-
llvm/test/CodeGen/RISCV/attributes.ll | 11 +-
llvm/test/CodeGen/RISCV/features-info.ll | 1 +
llvm/test/CodeGen/RISCV/zibi.ll | 207 ++++++++++++
llvm/test/CodeGen/RISCV/zibimm.ll | 299 ------------------
.../{zibimm-invalid.s => zibi-invalid.s} | 4 +-
.../MC/RISCV/{zibimm-valid.s => zibi-valid.s} | 28 +-
.../TargetParser/RISCVISAInfoTest.cpp | 2 +-
19 files changed, 289 insertions(+), 413 deletions(-)
rename llvm/lib/Target/RISCV/{RISCVInstrInfoZibimm.td => RISCVInstrInfoZibi.td} (57%)
create mode 100644 llvm/test/CodeGen/RISCV/zibi.ll
delete mode 100644 llvm/test/CodeGen/RISCV/zibimm.ll
rename llvm/test/MC/RISCV/{zibimm-invalid.s => zibi-invalid.s} (92%)
rename llvm/test/MC/RISCV/{zibimm-valid.s => zibi-valid.s} (71%)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 17125ad2a6713..adfd2c41b16ec 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -205,7 +205,7 @@
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD))
-// CHECK-NEXT: zibimm 0.1 'Zibimm' (Branch with Immediate)
+// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 7ac37bde70e05..52a483100f829 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -122,7 +122,7 @@
// CHECK-NOT: __riscv_zfinx {{.*$}}
// CHECK-NOT: __riscv_zhinx {{.*$}}
// CHECK-NOT: __riscv_zhinxmin {{.*$}}
-// CHECK-NOT: __riscv_zibimm {{.*$}}
+// CHECK-NOT: __riscv_zibi {{.*$}}
// CHECK-NOT: __riscv_zic64b {{.*$}}
// CHECK-NOT: __riscv_zicbom {{.*$}}
// CHECK-NOT: __riscv_zicbop {{.*$}}
@@ -1031,12 +1031,12 @@
// CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zibimm0p1 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBIMM-EXT %s
+// RUN: -march=rv32i_zibi0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zibimm0p1 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBIMM-EXT %s
-// CHECK-ZIBIMM-EXT: __riscv_zibimm
+// RUN: -march=rv64i_zibi0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s
+// CHECK-ZIBI-EXT: __riscv_zibi
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izic64b -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7e6fcc373334b..de7f9c07c6c75 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -744,15 +744,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return isUImmPred([](int64_t Imm) { return Imm != 0 && isUInt<5>(Imm); });
}
- bool isUImm5Zibimm() const {
- if (!isImm())
- return false;
- int64_t Imm;
- RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
- bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
- Imm = fixImmediateForRV32(Imm, isRV64Imm());
- return IsConstantImm && ((isUInt<5>(Imm) && Imm != 0) || Imm == -1) &&
- VK == RISCVMCExpr::VK_RISCV_None;
+ bool isUImm5Zibi() const {
+ return isUImmPred(
+ [](int64_t Imm) { return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1; });
}
bool isUImm5GT3() const {
@@ -1477,7 +1471,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
case Match_InvalidUImm5NonZero:
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
- case Match_InvalidUImm5Zibimm:
+ case Match_InvalidUImm5Zibi:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -1, (1 << 5) - 1,
"immediate must be non-zero in the range");
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 9e8e751e7f9c0..a8d673f662cbd 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -457,15 +457,11 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
}
-template <unsigned N>
-static DecodeStatus decodeUImmZibimmOperand(MCInst &Inst, uint32_t Imm,
- int64_t Address,
- const MCDisassembler *Decoder) {
- assert(isUInt<N>(Imm) && "Invalid immediate");
- if (Imm)
- Inst.addOperand(MCOperand::createImm(Imm));
- else
- Inst.addOperand(MCOperand::createImm(-1));
+static DecodeStatus decodeUImmZibiOperand(MCInst &Inst, uint32_t Imm,
+ int64_t Address,
+ const MCDisassembler *Decoder) {
+ assert(isUInt<5>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL));
return MCDisassembler::Success;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 983a94c8b8e77..d488785d8297d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -301,7 +301,7 @@ enum OperandType : unsigned {
OPERAND_UIMM4,
OPERAND_UIMM5,
OPERAND_UIMM5_NONZERO,
- OPERAND_UIMM5_ZIBIMM,
+ OPERAND_UIMM5_ZIBI,
OPERAND_UIMM5_GT3,
OPERAND_UIMM5_PLUS1,
OPERAND_UIMM5_GE6_PLUS1,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 370ccf660551c..d6fd6a9323dd4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -97,9 +97,9 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- uint64_t getImmOpValueZibimm(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
+ uint64_t getImmOpValueZibi(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
@@ -550,20 +550,16 @@ RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
}
uint64_t
-RISCVMCCodeEmitter::getImmOpValueZibimm(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+RISCVMCCodeEmitter::getImmOpValueZibi(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
+ assert(MO.isImm() && "Zibi operand must be an immediate");
+ int64_t Res = MO.getImm();
+ if (Res == -1)
+ return 0;
- if (MO.isImm()) {
- int64_t Res = MO.getImm();
- if (Res == -1)
- return 0;
-
- return Res;
- }
-
- return getImmOpValue(MI, OpNo, Fixups, STI);
+ return Res;
}
uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e7e8c8f4c5bbf..8f97ddedb859d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -78,11 +78,11 @@ def FeatureStdExtE
: RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">,
RISCVExtensionBitmask<0, 4>;
-def FeatureStdExtZibimm
+def FeatureStdExtZibi
: RISCVExperimentalExtension<0, 1, "Branch with Immediate">;
-def HasStdExtZibimm : Predicate<"Subtarget->hasStdExtZibimm()">,
- AssemblerPredicate<(all_of FeatureStdExtZibimm),
- "'Zibimm' (Branch with Immediate)">;
+def HasStdExtZibi : Predicate<"Subtarget->hasStdExtZibi()">,
+ AssemblerPredicate<(all_of FeatureStdExtZibi),
+ "'Zibi' (Branch with Immediate)">;
def FeatureStdExtZic64b
: RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 13ee3ee63d1a6..7c54f9af1f144 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21483,7 +21483,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
// Insert appropriate branch.
if (MI.getOperand(2).isImm())
- BuildMI(HeadMBB, DL, TII.getBrCond(CC))
+ BuildMI(HeadMBB, DL, TII.getBrCond(CC, true))
.addReg(LHS)
.addImm(MI.getOperand(2).getImm())
.addMBB(TailMBB);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 94e93a974556c..96c6eaf05fc12 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1043,31 +1043,15 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
-<<<<<<< HEAD
-unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
-=======
unsigned RISCVCC::getBrCond(const RISCVSubtarget &STI, RISCVCC::CondCode CC,
bool Imm) {
->>>>>>> 63ba04f2fad0 ([RISCV] Add Support of RISCV Zibimm Experimental Extension)
switch (CC) {
default:
llvm_unreachable("Unknown condition code!");
case RISCVCC::COND_EQ:
-<<<<<<< HEAD
- return RISCV::BEQ;
+ return (Imm && STI.hasStdExtZibi()) ? RISCV::BEQI : RISCV::BEQ;
case RISCVCC::COND_NE:
- return RISCV::BNE;
-=======
- return Imm ? (STI.hasStdExtZibimm()
- ? RISCV::BEQI
- : (STI.hasVendorXCVbi() ? RISCV::CV_BEQIMM : RISCV::BEQ))
- : RISCV::BEQ;
- case RISCVCC::COND_NE:
- return Imm ? (STI.hasStdExtZibimm()
- ? RISCV::BNEI
- : (STI.hasVendorXCVbi() ? RISCV::CV_BNEIMM : RISCV::BNE))
- : RISCV::BNE;
->>>>>>> 63ba04f2fad0 ([RISCV] Add Support of RISCV Zibimm Experimental Extension)
+ return (Imm && STI.hasStdExtZibi()) ? RISCV::BNEI : RISCV::BNE;
case RISCVCC::COND_LT:
return RISCV::BLT;
case RISCVCC::COND_GE:
@@ -1107,14 +1091,9 @@ unsigned RISCVCC::getBrCond(const RISCVSubtarget &STI, RISCVCC::CondCode CC,
}
}
-<<<<<<< HEAD
-const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const {
- return get(RISCVCC::getBrCond(CC));
-=======
const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC,
bool Imm) const {
return get(RISCVCC::getBrCond(STI, CC, Imm));
->>>>>>> 63ba04f2fad0 ([RISCV] Add Support of RISCV Zibimm Experimental Extension)
}
RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
@@ -1291,8 +1270,10 @@ unsigned RISCVInstrInfo::insertBranch(
// Either a one or two-way conditional branch.
auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
- MachineInstr &CondMI =
- *BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
+ MachineInstr &CondMI = *BuildMI(&MBB, DL, getBrCond(CC, Cond[2].isImm()))
+ .add(Cond[1])
+ .add(Cond[2])
+ .addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);
@@ -2732,7 +2713,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM2_LSB0:
Ok = isShiftedUInt<1, 1>(Imm);
break;
- case RISCVOp::OPERAND_UIMM5_ZIBIMM:
+ case RISCVOp::OPERAND_UIMM5_ZIBI:
Ok = (isUInt<5>(Imm) && Imm != 0) || Imm == -1;
break;
case RISCVOp::OPERAND_UIMM5_LSB0:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 986d5015de667..4735670c3e96f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -79,7 +79,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
explicit RISCVInstrInfo(RISCVSubtarget &STI);
MCInst getNop() const override;
- const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
+ const MCInstrDesc &getBrCond(RISCVCC::CondCode CC, bool Imm = false) const;
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9382203e967f4..1f3e21015f89b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2249,7 +2249,7 @@ include "RISCVInstrInfoZicbo.td"
include "RISCVInstrInfoZicond.td"
include "RISCVInstrInfoZicfiss.td"
include "RISCVInstrInfoZilsd.td"
-include "RISCVInstrInfoZibimm.td"
+include "RISCVInstrInfoZibi.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
similarity index 57%
rename from llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td
rename to llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
index ad0164bd0fb6b..c61bcefdfc4ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZibimm.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
@@ -1,4 +1,4 @@
-//===-- RISCVInstrInfoZibimm.td - 'Zibimm' instructions ------*- tablegen -*-===//
+//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions ------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,43 +6,46 @@
//
//===----------------------------------------------------------------------===//
///
-/// This file describes the RISC-V instructions for 'Zibimm' (branch with imm).
+/// This file describes the RISC-V instructions for 'Zibi' (branch with imm).
///
//===----------------------------------------------------------------------===//
// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
-def uimm5_zibimm : RISCVOp, ImmLeaf<XLenVT, [{
+def uimm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
}]> {
- let ParserMatchClass = UImmAsmOperand<5, "Zibimm">;
- let EncoderMethod = "getImmOpValueZibimm";
- let DecoderMethod = "decodeUImmZibimmOperand<5>";
+ let ParserMatchClass = UImmAsmOperand<5, "Zibi">;
+ let EncoderMethod = "getImmOpValueZibi";
+ let DecoderMethod = "decodeUImmZibiOperand";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return (Imm >= 1 && Imm <= 31) || Imm == -1;
}];
- let OperandType = "OPERAND_UIMM5_ZIBIMM";
+ let OperandType = "OPERAND_UIMM5_ZIBI";
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+
class Branch_imm<bits<3> funct3, string opcodestr>
: RVInstBIMM<funct3, OPC_BRANCH, (outs),
- (ins GPR:$rs1, uimm5_zibimm:$cimm, simm13_lsb0:$imm12),
+ (ins GPR:$rs1, uimm5_zibi:$cimm, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $cimm, $imm12">,
Sched<[WriteJmp, ReadJmp]> {
let isBranch = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
+ let mayLoad = 0;
+ let mayStore = 0;
}
-let Predicates = [HasStdExtZibimm] in {
+let Predicates = [HasStdExtZibi] in {
def BEQI : Branch_imm<0b010, "beqi">;
def BNEI : Branch_imm<0b011, "bnei">;
-} // Predicates = [HasStdExtZibimm]
+} // Predicates = [HasStdExtZibi]
-let Predicates = [HasStdExtZibimm] in {
+let Predicates = [HasStdExtZibi] in {
multiclass BccImmPat<CondCode Cond, Branch_imm Inst> {
- def : Pat<(riscv_brcc (XLenVT GPR:$rs1), uimm5_zibimm:$cimm, Cond, bb:$imm12),
- (Inst GPR:$rs1, uimm5_zibimm:$cimm, simm13_lsb0:$imm12)>;
+ def : Pat<(riscv_brcc (XLenVT GPR:$rs1), uimm5_zibi:$cimm, Cond, bb:$imm12),
+ (Inst GPR:$rs1, uimm5_zibi:$cimm, bare_simm13_lsb0_bb:$imm12)>;
}
defm : BccImmPat<SETEQ, BEQI>;
defm : BccImmPat<SETNE, BNEI>;
-}// Predicates = [HasStdExtZibimm]
\ No newline at end of file
+}// Predicates = [HasStdExtZibi]
\ No newline at end of file
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 5da7f9c863c2e..a01c7272da0ae 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -173,7 +173,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibimm %s -o - | FileCheck --check-prefix=RV32ZIBIMM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV32ZIBI %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -338,10 +338,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
-
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibimm %s -o - | FileCheck --check-prefix=RV64ZIBIMM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV64ZIBI %s
; Tests for profile features.
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
@@ -530,7 +527,7 @@
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
-; RV32ZIBIMM: .attribute 5, "rv32i2p1_zibimm0p1"
+; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p1"
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -693,7 +690,7 @@
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p3"
-; RV64ZIBIMM: .attribute 5, "rv64i2p1_zibimm0p1"
+; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1"
; RVI20U32: .attribute 5, "rv32i2p1"
; RVI20U64: .attribute 5, "rv64i2p1"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 8b931f70aa5cc..c999550b7e713 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -46,6 +46,7 @@
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).
; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions).
+; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate).
; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).
; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).
; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements).
diff --git a/llvm/test/CodeGen/RISCV/zibi.ll b/llvm/test/CodeGen/RISCV/zibi.ll
new file mode 100644
index 0000000000000..e77acd0dc749d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zibi.ll
@@ -0,0 +1,207 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=ZIBI %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=ZIBI %s
+
+define void @test_bne_neg(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_neg:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: bnei a1, -1, .LBB0_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB0_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, -1
+ br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!0 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_neg(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_neg:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: beqi a1, -1, .LBB1_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB1_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, -1
+ br i1 %tst1, label %end, label %test2, !prof !1
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!1 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_zero(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_zero:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: bnez a1, .LBB2_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB2_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 0
+ br i1 %tst1, label %end, label %test2, !prof !2
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!2 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_zero(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_zero:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: beqz a1, .LBB3_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB3_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 0
+ br i1 %tst1, label %end, label %test2, !prof !3
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!3 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_1(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_1:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: bnei a1, 1, .LBB4_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB4_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 1
+ br i1 %tst1, label %end, label %test2, !prof !4
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!4 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_1(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_1:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: beqi a1, 1, .LBB5_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB5_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 1
+ br i1 %tst1, label %end, label %test2, !prof !5
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!5 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_31(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_31:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: bnei a1, 31, .LBB6_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB6_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 31
+ br i1 %tst1, label %end, label %test2, !prof !6
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!6 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_31(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_31:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: beqi a1, 1, .LBB7_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB7_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 1
+ br i1 %tst1, label %end, label %test2, !prof !7
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!7 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_bne_32(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_32:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: li a2, 32
+; ZIBI-NEXT: bne a1, a2, .LBB8_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB8_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp ne i32 %val1, 32
+ br i1 %tst1, label %end, label %test2, !prof !8
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!8 = !{!"branch_weights", i32 1, i32 99}
+
+define void @test_beq_32(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_32:
+; ZIBI: # %bb.0:
+; ZIBI-NEXT: lw a1, 0(a0)
+; ZIBI-NEXT: li a2, 32
+; ZIBI-NEXT: beq a1, a2, .LBB9_2
+; ZIBI-NEXT: # %bb.1: # %test2
+; ZIBI-NEXT: lw zero, 0(a0)
+; ZIBI-NEXT: .LBB9_2: # %end
+; ZIBI-NEXT: ret
+ %val1 = load volatile i32, ptr %b
+ %tst1 = icmp eq i32 %val1, 32
+ br i1 %tst1, label %end, label %test2, !prof !9
+test2:
+ %val2 = load volatile i32, ptr %b
+ br label %end
+end:
+ ret void
+}
+!9 = !{!"branch_weights", i32 1, i32 99}
diff --git a/llvm/test/CodeGen/RISCV/zibimm.ll b/llvm/test/CodeGen/RISCV/zibimm.ll
deleted file mode 100644
index d0cf335bc2a36..0000000000000
--- a/llvm/test/CodeGen/RISCV/zibimm.ll
+++ /dev/null
@@ -1,299 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibimm -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I-ZIBIMM %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibimm -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I-ZIBIMM %s
-
-define void @test_bne_neg(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_bne_neg:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: bnei a1, -1, .LBB0_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB0_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_bne_neg:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: bnei a1, -1, .LBB0_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB0_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp ne i32 %val1, -1
- br i1 %tst1, label %end, label %test2, !prof !0
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!0 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_beq_neg(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_beq_neg:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: beqi a1, -1, .LBB1_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB1_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_beq_neg:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: beqi a1, -1, .LBB1_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB1_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp eq i32 %val1, -1
- br i1 %tst1, label %end, label %test2, !prof !1
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!1 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_bne_zero(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_bne_zero:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: bnez a1, .LBB2_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB2_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_bne_zero:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: bnez a1, .LBB2_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB2_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp ne i32 %val1, 0
- br i1 %tst1, label %end, label %test2, !prof !2
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!2 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_beq_zero(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_beq_zero:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: beqz a1, .LBB3_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB3_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_beq_zero:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: beqz a1, .LBB3_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB3_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp eq i32 %val1, 0
- br i1 %tst1, label %end, label %test2, !prof !3
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!3 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_bne_1(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_bne_1:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: bnei a1, 1, .LBB4_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB4_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_bne_1:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: bnei a1, 1, .LBB4_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB4_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp ne i32 %val1, 1
- br i1 %tst1, label %end, label %test2, !prof !4
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!4 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_beq_1(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_beq_1:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: beqi a1, 1, .LBB5_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB5_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_beq_1:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: beqi a1, 1, .LBB5_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB5_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp eq i32 %val1, 1
- br i1 %tst1, label %end, label %test2, !prof !5
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!5 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_bne_31(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_bne_31:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: bnei a1, 31, .LBB6_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB6_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_bne_31:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: bnei a1, 31, .LBB6_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB6_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp ne i32 %val1, 31
- br i1 %tst1, label %end, label %test2, !prof !6
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!6 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_beq_31(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_beq_31:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: beqi a1, 1, .LBB7_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB7_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_beq_31:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: beqi a1, 1, .LBB7_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB7_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp eq i32 %val1, 1
- br i1 %tst1, label %end, label %test2, !prof !7
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!7 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_bne_32(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_bne_32:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: li a2, 32
-; RV32I-ZIBIMM-NEXT: bne a1, a2, .LBB8_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB8_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_bne_32:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: li a2, 32
-; RV64I-ZIBIMM-NEXT: bne a1, a2, .LBB8_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB8_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp ne i32 %val1, 32
- br i1 %tst1, label %end, label %test2, !prof !8
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!8 = !{!"branch_weights", i32 1, i32 99}
-
-define void @test_beq_32(ptr %b) nounwind {
-; RV32I-ZIBIMM-LABEL: test_beq_32:
-; RV32I-ZIBIMM: # %bb.0:
-; RV32I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV32I-ZIBIMM-NEXT: li a2, 32
-; RV32I-ZIBIMM-NEXT: beq a1, a2, .LBB9_2
-; RV32I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV32I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV32I-ZIBIMM-NEXT: .LBB9_2: # %end
-; RV32I-ZIBIMM-NEXT: ret
-;
-; RV64I-ZIBIMM-LABEL: test_beq_32:
-; RV64I-ZIBIMM: # %bb.0:
-; RV64I-ZIBIMM-NEXT: lw a1, 0(a0)
-; RV64I-ZIBIMM-NEXT: li a2, 32
-; RV64I-ZIBIMM-NEXT: beq a1, a2, .LBB9_2
-; RV64I-ZIBIMM-NEXT: # %bb.1: # %test2
-; RV64I-ZIBIMM-NEXT: lw zero, 0(a0)
-; RV64I-ZIBIMM-NEXT: .LBB9_2: # %end
-; RV64I-ZIBIMM-NEXT: ret
- %val1 = load volatile i32, ptr %b
- %tst1 = icmp eq i32 %val1, 32
- br i1 %tst1, label %end, label %test2, !prof !9
-test2:
- %val2 = load volatile i32, ptr %b
- br label %end
-end:
- ret void
-}
-!9 = !{!"branch_weights", i32 1, i32 99}
diff --git a/llvm/test/MC/RISCV/zibimm-invalid.s b/llvm/test/MC/RISCV/zibi-invalid.s
similarity index 92%
rename from llvm/test/MC/RISCV/zibimm-invalid.s
rename to llvm/test/MC/RISCV/zibi-invalid.s
index 120190a1f5411..4c725ef52ca0b 100644
--- a/llvm/test/MC/RISCV/zibimm-invalid.s
+++ b/llvm/test/MC/RISCV/zibi-invalid.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zibimm %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zibi %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zibimm %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zibi %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
beqi a0, 0x0, 0x400
# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31]
diff --git a/llvm/test/MC/RISCV/zibimm-valid.s b/llvm/test/MC/RISCV/zibi-valid.s
similarity index 71%
rename from llvm/test/MC/RISCV/zibimm-valid.s
rename to llvm/test/MC/RISCV/zibi-valid.s
index e3baba6efa8a0..b062c4cf1efb3 100644
--- a/llvm/test/MC/RISCV/zibimm-valid.s
+++ b/llvm/test/MC/RISCV/zibi-valid.s
@@ -1,63 +1,63 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zibimm %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zibi %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-ASM
-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zibimm %s \
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zibi %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-ASM
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibimm %s \
-# RUN: | llvm-objdump -d --mattr=+experimental-zibimm --no-print-imm-hex - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibi %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zibi --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-OBJ
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibimm %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibi %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zibimm %s \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zibi %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
beqi a0, 1, 1024
# CHECK-OBJ: beqi a0, 1, 0x400
# CHECK-ASM: beqi a0, 1, 1024
# CHECK-ENCODING: [0x63,0x20,0x15,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: 40152063 <unknown>
beqi a5, -1, -1024
# CHECK-OBJ: beqi a5, -1, 0xfffffc04
# CHECK-ASM: beqi a5, -1, -1024
# CHECK-ENCODING: [0xe3,0xa0,0x07,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: c007a0e3 <unknown>
beqi s0, 22, 0xffe
# CHECK-OBJ: beqi s0, 22, 0x1006
# CHECK-ASM: beqi s0, 22, 4094
# CHECK-ENCODING: [0xe3,0x2f,0x64,0x7f]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: 7f642fe3 <unknown>
beqi s1, 11, -4096
# CHECK-OBJ: beqi s1, 11, 0xfffff00c
# CHECK-ASM: beqi s1, 11, -4096
# CHECK-ENCODING: [0x63,0xa0,0xb4,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: 80b4a063 <unknown>
bnei a0, 1, 1024
# CHECK-OBJ: bnei a0, 1, 0x410
# CHECK-ASM: bnei a0, 1, 1024
# CHECK-ENCODING: [0x63,0x30,0x15,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: 40153063 <unknown>
bnei a5, -1, -1024
# CHECK-OBJ: bnei a5, -1, 0xfffffc14
# CHECK-ASM: bnei a5, -1, -1024
# CHECK-ENCODING: [0xe3,0xb0,0x07,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: c007b0e3 <unknown>
bnei s0, 22, 0xffe
# CHECK-OBJ: bnei s0, 22, 0x1016
# CHECK-ASM: bnei s0, 22, 4094
# CHECK-ENCODING: [0xe3,0x3f,0x64,0x7f]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: 7f643fe3 <unknown>
bnei s1, 11, -4096
# CHECK-OBJ: bnei s1, 11, 0xfffff01c
# CHECK-ASM: bnei s1, 11, -4096
# CHECK-ENCODING: [0x63,0xb0,0xb4,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zibimm' (Branch with Immediate){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}}
# CHECK-UNKNOWN: 80b4b063 <unknown>
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 6250732daabbc..f289f969e7a51 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1176,7 +1176,7 @@ R"(All available -march extensions for RISC-V
Experimental extensions
p 0.14
- zibimm 0.1
+ zibi 0.1
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
zalasr 0.1
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