[clang] f952af3 - [clang][docs][RISCV] Prepend the HelpText for -mrvv-vector-bits into the DocBrief. (#144128)

[via cfe-commits]

Author: Craig Topper
Date: 2025-06-13T12:25:31-07:00
New Revision: f952af30fd2efbf6effa3e845f0e49a9f0e2302d

URL: https://github.com/llvm/llvm-project/commit/f952af30fd2efbf6effa3e845f0e49a9f0e2302d
DIFF: https://github.com/llvm/llvm-project/commit/f952af30fd2efbf6effa3e845f0e49a9f0e2302d.diff

LOG: [clang][docs][RISCV] Prepend the HelpText for -mrvv-vector-bits into the DocBrief. (#144128)

The DocBrief is used to generate the webpage description of the option.
The current text only talks about the possible values, but not what the
option does.

Added: 
    

Modified: 
    clang/include/clang/Driver/Options.td

Removed: 
    


################################################################################
diff  --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 5951687b095e4..1b07deb4a8482 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5056,9 +5056,10 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>,
   Visibility<[ClangOption, FlangOption]>,
   HelpText<"Specify the size in bits of an RVV vector register">,
   DocBrief<!strconcat(
-    "Defaults to the vector length agnostic value of \"scalable\". "
-    "Accepts power of 2 values between 64 and 65536. Also accepts "
-    "\"zvl\" to use the value implied by -march/-mcpu.",
+    "Specify the size in bits of an RVV vector register. Defaults to the "
+    "vector length agnostic value of \"scalable\". Accepts power of 2 values "
+    "between 64 and 65536. Also accepts \"zvl\" to use the value implied by "
+    "-march/-mcpu.",
     !cond(
       // Flang does not set the preprocessor define.
       !eq(GlobalDocumentation.Program, "Flang") : "",