[clang] [llvm] [mlir] [AMDGPU] Add a new amdgcn.load.to.lds intrinsic (PR #137425)

[Krzysztof Drewniak via cfe-commits]

krzysz00 wrote:

>  (that means addrspacecast 7-> 8 is not invertible by 8-> 7, right? it would discard some bits, in invisible breakage sort of way? is there an RFC for that design?)

I'm not aware of anything requiring addrspacecast to be invertible? (In specific, cast 7 -> 8 isn't a thing at the moment)

https://github.com/llvm/llvm-project/pull/137425