[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)
Jim Lin via cfe-commits
cfe-commits at lists.llvm.org
Tue May 20 23:59:08 PDT 2025
https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/140681
>From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Tue, 20 May 2025 10:13:26 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition
Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable
CPUs that implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions.
They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider.
The overviews for A25/AX25:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25/
Scheduling model will be implemented in a later PR.
---
clang/test/Driver/riscv-cpus.c | 36 +++++++++++++++++++
.../test/Misc/target-invalid-cpu-note/riscv.c | 12 ++++---
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 32 +++++++++++++++++
4 files changed, 77 insertions(+), 4 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index dacdb03fd09d9..cebf41aa626a7 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -699,6 +699,42 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s
+// MCPU-ANDES-A25: "-target-cpu" "andes-a25"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+m"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+a"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+f"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+d"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+c"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+zbc"
+// MCPU-ANDES-A25-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s
+// MTUNE-ANDES-A25: "-tune-cpu" "andes-a25"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s
+// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+m"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+a"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+f"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+d"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+c"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbc"
+// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s
+// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
+
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index b4e83e59d296f..c57bde8aa531a 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} andes-a45
+// RISCV32-SAME: {{^}} andes-a25
+// RISCV32-SAME: {{^}}, andes-a45
// RISCV32-SAME: {{^}}, andes-n45
// RISCV32-SAME: {{^}}, generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
@@ -26,7 +27,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} andes-ax45
+// RISCV64-SAME: {{^}} andes-ax25
+// RISCV64-SAME: {{^}}, andes-ax45
// RISCV64-SAME: {{^}}, andes-nx45
// RISCV64-SAME: {{^}}, generic-rv64
// RISCV64-SAME: {{^}}, mips-p8700
@@ -57,7 +59,8 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
-// TUNE-RISCV32-SAME: {{^}} andes-a45
+// TUNE-RISCV32-SAME: {{^}} andes-a25
+// TUNE-RISCV32-SAME: {{^}}, andes-a45
// TUNE-RISCV32-SAME: {{^}}, andes-n45
// TUNE-RISCV32-SAME: {{^}}, generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
@@ -82,7 +85,8 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
-// TUNE-RISCV64-SAME: {{^}} andes-ax45
+// TUNE-RISCV64-SAME: {{^}} andes-ax25
+// TUNE-RISCV64-SAME: {{^}}, andes-ax45
// TUNE-RISCV64-SAME: {{^}}, andes-nx45
// TUNE-RISCV64-SAME: {{^}}, generic-rv64
// TUNE-RISCV64-SAME: {{^}}, mips-p8700
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 9c8cc599a8daf..1ce796fc4a5a5 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -189,6 +189,7 @@ Changes to the RISC-V Backend
* Adds assembler support for the Andes `XAndesvdot` (Andes Vector Dot Product extension).
* Adds assembler support for the standard `Q` (Quad-Precision Floating Point)
extension.
+* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index db57f5c4da24e..6d0627fa2c329 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs]>;
+
+def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs]>;
+
def ANDES_N45 : RISCVProcessorModel<"andes-n45",
NoSchedModel,
[Feature32Bit,
>From eb75b32db4c8be4243eb7d99e8d0578df3be732c Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 21 May 2025 09:48:07 +0800
Subject: [PATCH 2/4] Check print-enabled-extensions instead of checking
-target-feature
---
.../riscv-andes-a25.c | 29 +++++++++++++++++++
.../riscv-andes-ax25.c | 28 ++++++++++++++++++
clang/test/Driver/riscv-cpus.c | 26 ++---------------
3 files changed, 60 insertions(+), 23 deletions(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
new file mode 100644
index 0000000000000..85adf0398dce2
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
@@ -0,0 +1,29 @@
+// RUN: %clang --target=riscv32 -mcpu=andes-a25 --print-enabled-extensions | FileCheck %s
+// REQUIRES: riscv-registered-target
+
+// CHECK: Extensions enabled for the given RISC-V target
+// CHECK-EMPTY:
+// CHECK-NEXT: Name Version Description
+// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
+// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
+// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
+// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
+// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
+// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
+// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
+// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
+// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
+// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
+// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
+// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
+// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
+// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
+// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
+// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
+// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
+// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
+// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
+// CHECK-EMPTY:
+// CHECK-NEXT: Experimental extensions
+// CHECK-EMPTY:
+// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
new file mode 100644
index 0000000000000..7b139a7e87423
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
@@ -0,0 +1,28 @@
+// RUN: %clang --target=riscv64 -mcpu=andes-ax25 --print-enabled-extensions | FileCheck %s
+// REQUIRES: riscv-registered-target
+
+// CHECK: Extensions enabled for the given RISC-V target
+// CHECK-EMPTY:
+// CHECK-NEXT: Name Version Description
+// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
+// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
+// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
+// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
+// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
+// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
+// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
+// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
+// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
+// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
+// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
+// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
+// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
+// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
+// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
+// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
+// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
+// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
+// CHECK-EMPTY:
+// CHECK-NEXT: Experimental extensions
+// CHECK-EMPTY:
+// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index cebf41aa626a7..91b9bee6d6691 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -701,17 +701,7 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s
// MCPU-ANDES-A25: "-target-cpu" "andes-a25"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+m"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+a"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+f"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+d"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+c"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+zicsr"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+zifencei"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+zba"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+zbb"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+zbc"
-// MCPU-ANDES-A25-SAME: "-target-feature" "+zbs"
+// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-a25.c`
// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d"
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s
@@ -719,18 +709,8 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s
// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+m"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+a"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+f"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+d"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+c"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+zicsr"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+zifencei"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+zba"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbb"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbc"
-// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbs"
-// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d"
+// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax25.c`
+// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s
// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
>From 7b7928cc2f7c3039894fb6b87446edccfab9ab18 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 21 May 2025 09:50:46 +0800
Subject: [PATCH 3/4] Replace Zba, Zbb and Zbs with B.
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6d0627fa2c329..a63342f8a0eff 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -659,10 +659,8 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbc,
- FeatureStdExtZbs]>;
+ FeatureStdExtB,
+ FeatureStdExtZbc]>;
def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
NoSchedModel,
@@ -675,10 +673,8 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbc,
- FeatureStdExtZbs]>;
+ FeatureStdExtB,
+ FeatureStdExtZbc]>;
def ANDES_N45 : RISCVProcessorModel<"andes-n45",
NoSchedModel,
>From ba436f58391782858880f28b1873de664af8d113 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 21 May 2025 13:58:46 +0800
Subject: [PATCH 4/4] Add extension xandesperf for A25/AX25
---
.../test/Driver/print-enabled-extensions/riscv-andes-a25.c | 3 ++-
.../test/Driver/print-enabled-extensions/riscv-andes-ax25.c | 3 ++-
llvm/lib/Target/RISCV/RISCVProcessors.td | 6 ++++--
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
index 85adf0398dce2..d8b3848d84520 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
@@ -23,7 +23,8 @@
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0
+// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
index 7b139a7e87423..3f933ecd8ac83 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
@@ -22,7 +22,8 @@
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0
+// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index a63342f8a0eff..9cd017fc374bc 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -660,7 +660,8 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
- FeatureStdExtZbc]>;
+ FeatureStdExtZbc,
+ FeatureVendorXAndesPerf]>;
def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
NoSchedModel,
@@ -674,7 +675,8 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
- FeatureStdExtZbc]>;
+ FeatureStdExtZbc,
+ FeatureVendorXAndesPerf]>;
def ANDES_N45 : RISCVProcessorModel<"andes-n45",
NoSchedModel,
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