[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)
Jim Lin via cfe-commits
cfe-commits at lists.llvm.org
Tue May 20 23:12:06 PDT 2025
================
@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs]>;
+
+def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs]>;
----------------
tclin914 wrote:
Done.
https://github.com/llvm/llvm-project/pull/140681
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