[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

[Min-Yih Hsu via cfe-commits]

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@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
                                           FeatureStdExtZcb,
                                           FeatureStdExtZcmp]>;
 
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+                                    NoSchedModel,
+                                    [Feature32Bit,
+                                     FeatureStdExtI,
+                                     FeatureStdExtZicsr,
+                                     FeatureStdExtZifencei,
+                                     FeatureStdExtM,
+                                     FeatureStdExtA,
+                                     FeatureStdExtF,
+                                     FeatureStdExtD,
+                                     FeatureStdExtC,
+                                     FeatureStdExtZba,
+                                     FeatureStdExtZbb,
+                                     FeatureStdExtZbc,
+                                     FeatureStdExtZbs]>;
+
+def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
+                                     NoSchedModel,
+                                     [Feature64Bit,
+                                      FeatureStdExtI,
+                                      FeatureStdExtZicsr,
+                                      FeatureStdExtZifencei,
+                                      FeatureStdExtM,
+                                      FeatureStdExtA,
+                                      FeatureStdExtF,
+                                      FeatureStdExtD,
+                                      FeatureStdExtC,
+                                      FeatureStdExtZba,
+                                      FeatureStdExtZbb,
+                                      FeatureStdExtZbc,
+                                      FeatureStdExtZbs]>;
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mshockwave wrote:

FeatureStdExtB + FeatureStdExtZbc?

https://github.com/llvm/llvm-project/pull/140681